CN115527871A - 多芯片封装方法及封装结构 - Google Patents

多芯片封装方法及封装结构 Download PDF

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Publication number
CN115527871A
CN115527871A CN202211262174.6A CN202211262174A CN115527871A CN 115527871 A CN115527871 A CN 115527871A CN 202211262174 A CN202211262174 A CN 202211262174A CN 115527871 A CN115527871 A CN 115527871A
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chip
packaging
package
metal column
metal
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CN202211262174.6A
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叶义军
俞国庆
郝杰
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Lixin Precision Intelligent Manufacturing Kunshan Co ltd
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Lixin Precision Intelligent Manufacturing Kunshan Co ltd
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Priority to CN202211262174.6A priority Critical patent/CN115527871A/zh
Publication of CN115527871A publication Critical patent/CN115527871A/zh
Priority to TW112115045A priority patent/TWI856619B/zh
Priority to US18/196,530 priority patent/US20240128141A1/en
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Abstract

本发明公开了一种多芯片封装方法及封装结构，其属于芯片封装技术领域，包括如下步骤：在固设有第一金属柱的衬底上倒装第一芯片，第一金属柱和第一芯片间隔设置于衬底的同一表面；塑封第一金属柱及第一芯片，得到第一封装体；在第一封装体的表面制作第一重布线层；在第一重布线层的表面上倒装第二芯片，并对第二芯片塑封处理，得到第二封装体；去除衬底，并在第一封装体的表面制作第二重布线层；在第二重布线层的表面制作相互间隔开的第二金属柱及倒装第三芯片，并对第三芯片及第二金属柱塑封处理，得到第三封装体；在第三封装体的表面上制作焊球，焊球通过第二金属柱电连接于第二重布线层。本发明制造多芯片封装结构的难度较低且具有较低的成本。

Description

多芯片封装方法及封装结构
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种多芯片封装方法及封装结构。
背景技术
目前，物联网、大数据、云计算等要求电子封装件集成度越来越高，芯片与芯片之间、芯片与基板之间的电连接越来越短，而多芯片的三维封装体的散热性能较好。
鉴于芯片封装技术、基板技术在技术上与芯片制造技术存在巨大的技术差距，业界普遍认为，由芯片封装技术提升为主导方向，借以提高电子产品的性价比时代已经来临，系统级封装(SiP，system in package)将是超越摩尔定律的必然途径之一。SiP技术通过混合各种技术如传统封装技术、先进封装技术、基板技术、表面贴装技术等，把芯片和被动元件电信号连接而成的具有子系统功能的产品。作为SiP技术不可或缺的先进封装技术即晶圆级封装(WLP)，自2000年以来得到了快速的发展。
现有技术中，基于硅通孔TSV的硅转接板技术(Si interposer)和基于TSV的三维封装技术被认为是高集成度封装多芯片的理想选择方案。硅转接板技术可以使相临芯片之间的连接使用TSV转接板，然而，由于TSV的制作技术难度极高，如电镀形成铜柱时较容易产生飞屑，费用也高昂，成本较高。
发明内容
本发明的目的在于提供一种多芯片封装方法及封装结构，制造难度较低且具有较低的成本。
如上构思，本发明所采用的技术方案是：
多芯片封装方法，包括如下步骤：
S1、在固设有第一金属柱的衬底上倒装第一芯片，所述第一金属柱和所述第一芯片间隔设置于所述衬底的同一表面；
S2、通过塑封工艺将所述第一金属柱及所述第一芯片塑封，得到设于所述衬底上的第一封装体，所述第一封装体包括第一金属柱、第一芯片及第一塑封体；
S3、在所述第一封装体远离所述衬底的表面上制作第一重布线层，所述第一金属柱电连接于所述第一重布线层；
S4、在所述第一重布线层远离所述衬底的表面上倒装第二芯片，并对所述第二芯片塑封处理，得到设于所述第一重布线层上的第二封装体，所述第二封装体包括第二芯片及第二塑封体，所述第二芯片电连接于所述第一重布线层，所述第一重布线层介于所述第一芯片和所述第二芯片之间；
S5、去除所述衬底，并在所述第一封装体远离所述第二封装体的表面制作第二重布线层，所述第一芯片及所述第一金属柱分别电连接于所述第二重布线层；
S6、在所述第二重布线层远离所述第一封装体的表面制作相互间隔开的第二金属柱及倒装第三芯片，对所述第三芯片及所述第二金属柱塑封处理，得到第三封装体，所述第三芯片及所述第二金属柱分别电连接于所述第二重布线层；
S7、在所述第三封装体远离所述第一封装体的表面上制作焊球，得到晶圆，所述焊球通过所述第二金属柱电连接于所述第二重布线层。
可选地，所述第一封装体还包括被动元件组，在步骤S2之前，所述多芯片封装方法还包括将所述被动元件组贴装到所述衬底上，在步骤S2中，通过所述塑封工艺将所述第一金属柱、所述第一芯片及所述被动元件组塑封。
可选地，步骤S2包括：
S21、通过塑封工艺将所述第一金属柱及所述第一芯片塑封，得到第一临时塑封体；
S22、对所述第一临时塑封体减薄处理，以露出所述第一芯片的背面及所述第一金属柱，并得到第一封装体。
可选地，步骤S6包括：
S61、在所述第二重布线层远离所述第一封装体的表面通过电镀的方式形成第二金属柱，所述第二金属柱与所述第二重布线层电连接；
S62、将所述第三芯片倒装在所述第二重布线层远离所述第一封装体的表面，所述第三芯片与所述第二重布线层电连接；
S63、通过塑封工艺将所述第二金属柱及所述第三芯片塑封，得到第二临时塑封体；
S64、对所述第二临时塑封体减薄处理，以露出所述第三芯片的背面及所述第二金属柱，并得到第三封装体。
可选地，步骤S7包括：
S71、通过光刻工艺在所述第三封装体远离所述第一封装体的表面上制作球下焊垫层；
S72、在所述球下焊垫层上通过电镀或植球的方式制作焊球。
可选地，在步骤S7之后，所述多芯片封装方法还包括如下步骤：
S8、将所述晶圆通过切割分割成多颗单体；
S9、将所述单体的焊球与转接件焊接，得到多芯片封装体。
多芯片封装结构，包括自上往下依次设置的第二封装体、第一重布线层、第一封装体、第二重布线层及第三封装体；
所述第一封装体包括第一金属柱、第一芯片及第一塑封体，所述第一金属柱的两端分别电连接于所述第一重布线层和所述第二重布线层；
所述第二封装体包括第二芯片及第二塑封体，所述第二芯片电连接于所述第一重布线层；
所述第三封装体包括第二金属柱及第三芯片，所述第二金属柱的一端电连接于所述第二重布线层，所述第一芯片及所述第三芯片分别电连接于所述第二重布线层，所述第一芯片、所述第二芯片及所述第三芯片的电信号分别通过所述第二金属柱传出。
可选地，所述第一封装体还包括多个被动元件组，每个所述被动元件组包括至少一个被动元件，所述被动元件为电容、电阻或电感。
可选地，还包括一一对应的多个球下焊垫和多个焊球，所述第二金属柱设有多个，多个所述球下焊垫与多个所述第二金属柱一一对应，且所述球下焊垫电连接于与其对应的所述第二金属柱的另一端，所述焊球焊接于与其对应的所述球下焊垫。
可选地，还包括转接件，所述转接件包括转接板及多个转接凸部，多个所述焊球分别焊接于所述转接板的上表面，多个所述转接凸部设于所述转接板的下表面，且所述转接凸部的数量大于所述焊球的数量。
本发明的有益效果：本发明提供的多芯片封装方法及封装结构，第一芯片的电信号通过第二重布线层及第二金属柱传至焊球，第二芯片的电信号通过第一重布线层、第一金属柱、第二重布线层及第二金属柱传至焊球，第三芯片的电信号通过第二重布线层及第二金属柱传至焊球，通过第一重布线层及第二重布线层实现了芯片与芯片之间的短距离电信号连接及芯片电信号的传出，无需TSV的制作工艺，具有较低的制造难度和较低的成本。
附图说明
图1是本发明实施例提供的多芯片封装方法的流程图；
图2是本发明实施例提供的多芯片封装结构的示意图；
图3是本发明实施例提供的形成第一金属柱后的示意图；
图4是本发明实施例提供的形成被动元件组后的示意图；
图5是本发明实施例提供的形成第一芯片后的示意图；
图6是本发明实施例提供的形成第一临时塑封体后的示意图；
图7是本发明实施例提供的形成第一封装体后的示意图；
图8是本发明实施例提供的形成第一重布线层后的示意图；
图9是本发明实施例提供的形成第二芯片后的示意图；
图10是本发明实施例提供的形成第二塑封体后的示意图；
图11是本发明实施例提供的去除衬底时的示意图；
图12是本发明实施例提供的形成第二重布线层后的示意图；
图13是本发明实施例提供的形成第二金属柱后的示意图；
图14是本发明实施例提供的形成第二芯片后的示意图；
图15是本发明实施例提供的形成第二临时塑封体后的示意图；
图16是本发明实施例提供的形成第三封装体后的示意图；
图17是本发明实施例提供的形成球下焊垫层后的示意图；
图18是本发明实施例提供的形成焊球后的示意图；
图19是本发明实施例提供的焊接转接件前的示意图。
图中：
1、第一封装体；11、第一金属柱；12、第一芯片；13、第一塑封体；
2、第一重布线层；
3、第二封装体；31、第二芯片；32、第二塑封体；
4、第二重布线层；
5、第三封装体；51、第二金属柱；52、第三芯片；53、第三塑封体；
6、焊球；7、被动元件组；71、被动元件；8、球下焊垫层；81、球下焊垫；9、转接件；91、转接板；92、转接凸部；
100、衬底；200、第一临时塑封体；300、第二临时塑封体。
具体实施方式
为使本发明解决的技术问题、采用的技术方案和达到的技术效果更加清楚，下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部。
在本发明的描述中，除非另有明确的规定和限定，术语“相连”、“连接”、“固定”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本实施例的描述中，术语“上”、“下”、“右”、等方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述和简化操作，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅仅用于在描述上加以区分，并没有特殊的含义。
实施例一
本实施例提供了一种多芯片封装方法，用于制造多芯片封装结构，制造难度较低且具有较低的成本。多芯片封装结构的如图2所示，该结构还可以称为硅基SIP。
如图1所示，多芯片封装方法包括如下步骤
S1、在固设有第一金属柱11的衬底100上倒装第一芯片12，第一金属柱11和第一芯片12间隔设置于衬底100的同一表面。
本实施例中，衬底100可以为玻璃、蓝宝石晶片等，在执行步骤S1之前，可以对衬底100进行预处理，如对衬底100进行抛光、除锈等处理。第一芯片12为具有凸块的芯片，将第一芯片12倒装在衬底100上是指第一芯片12的凸块朝向衬底100安装，本实施例中，第一芯片12具有凸块的表面称为正面，与正面相对的表面称为背面。
在步骤S1之前，可以在衬底100上制作第一金属柱11，在一些实施例中，可以利用磁控溅射、光刻技术和电镀技术，得到第一金属柱11。例如，在整片玻璃或蓝宝石晶片(即衬底100)上溅射金属层，在衬底100表面旋涂光刻胶、曝光、显影，把掩模板上的图形化转移到衬底100上，利用光刻胶软掩膜特性，在衬底100上进行电镀得到所需要的第一金属柱11。本实施例中，第一金属柱11设有多个，多个第一金属柱11间隔设置。图3为在衬底100上设置第一金属柱11的示意图。如图3所示，存在两组第一金属柱11，每组第一金属柱11中的两个第一金属柱11距离较近。本实施例中，在执行步骤S1后，第一金属柱11的高度大于第一芯片12的厚度，第一金属柱11的材质为铜、金等。需要说明的是，如图4所示，第一金属柱11和第一芯片12间隔设置于衬底100的同一表面。
可选地，在步骤S1之前，多芯片封装方法还包括将被动元件组7贴装到衬底100上，其中，被动元件组7设有多个，每个被动元件组7包括多个被动元件71，将多个被动元件71依次贴装在衬底100上。本实施例中，每个被动元件组7位于较靠近的相邻两个第一金属柱11之间。被动元件71示例为电容、电阻、电感等，本实施例对此不作限定。贴装被动元件组7后的结构如图4所示。
在贴装完被动元件组7后，将第一芯片12倒装在衬底100上，形成如图5所示的结构。
S2、通过塑封工艺将第一金属柱11及第一芯片12塑封，得到设于衬底100上的第一封装体1，第一封装体1包括第一金属柱11、第一芯片12及第一塑封体13。
在步骤S2中，将第一芯片12和第一金属柱11嵌入塑封材料之内进行塑封整理，以形成第一塑封体13，第一芯片12和第一金属柱11嵌设在第一塑封体13内。塑封工艺的基本原理及工程请参见现有技术。
可选地，步骤S2包括如下步骤：
S21、通过塑封工艺将第一金属柱11及第一芯片12塑封，得到第一临时塑封体200。
其中，第一临时塑封体200如图6所示，可见，第一临时塑封体200用于包裹第一金属柱11和第一芯片12的胶体的厚度大于第一金属柱11的厚度及第一芯片12的厚度，此时，第一金属柱11和第一芯片12均完全嵌设在胶体中。
S22、对第一临时塑封体200减薄处理，以露出第一芯片12的背面及第一金属柱11，并得到第一封装体1。
在得到第一临时塑封体200后，可以利用机械研磨设备对第一临时塑封体200进行减薄处理，并将第一芯片12的背面及第一金属柱11露出，便于第一金属柱11与其他电路电连接。在执行步骤S22后，如图7所示，第一金属柱11的高度等于第一芯片12的厚度。通过步骤S22，使得得到的多芯片封装结构可以较薄。
可选地，对第一临时塑封体200研磨处理后，可以进行抛光处理，以得到表面平整的第一封装体1。
本实施例中，当多芯片封装结构包括被动元件组7时，在步骤S2中，通过塑封工艺将第一金属柱11、第一芯片12及被动元件组7塑封，并形成包括被动元件组7的第一封装体1。
S3、在第一封装体1远离衬底100的表面上制作第一重布线层2，第一金属柱11电连接于第一重布线层2。
在得到第一封装体1后，在第一封装体1上制造第一重布线层2，以得到如图8所示的结构。其中，第一金属柱11远离衬底100的一端与第一重布线层2接触并电连接。在步骤S3中，可以通过光刻工艺制作第一重布线层2，也即是，在第一封装体1旋涂光刻胶、曝光、显影，把掩模板上的图形化转移到第一封装体1上，利用光刻胶软掩膜特性，在第一封装体1上进行电镀得到所需要的第一重布线层2，具体可以参见现有技术。
S4、在第一重布线层2远离衬底100的表面上倒装第二芯片31，并对第二芯片31塑封处理，得到设于第一重布线层2上的第二封装体3，第二封装体3包括第二芯片31及第二塑封体32，第二芯片31电连接于第一重布线层2，且第一重布线层2介于第一芯片12和第二芯片31之间。
在步骤S4中，在第一重布线层2上倒装第二芯片31，也即是，如图9所示，第二芯片31具有凸块，并将第二芯片31具有凸块的面朝向第一重布线层2设置，使得第二芯片31通过其凸块电连接于第一重布线层2。本实施例中，第二芯片31设有多个，在第一重布线层2上倒装多个第二芯片31以形成电信号连接。在安装多个第二芯片31后，采用塑封工艺将多个第二芯片31塑封，形成如图10所示的结构，其中，多个第二芯片31分别嵌入在第二塑封体32中。第二塑封体32的厚度大于第二芯片31的厚度，以能够有效地保护第二芯片31，但是，第二塑封体32的厚度稍大于第二芯片31的厚度，以避免第二封装体3的厚度较厚。
S5、去除衬底100，并在第一封装体1远离第二封装体3的表面制作第二重布线层4，第一芯片12及第一金属柱11分别电连接于第二重布线层4。
在步骤S5中，去除第一封装体1底部的衬底100，且在得到第二封装体3后，衬底100上沿远离其的方向依次设置有第一封装体1、第一重布线层2及第二封装体3。在步骤S5中，如图11所示，将衬底100与第一封装体1分离，也即是，临时解键合。在一些实施例中，将衬底100通过激光或高温湿法工艺去除衬底100。
在去除衬底100后，在第一封装体1远离第二封装体3的表面制作第二重布线层4，也即是，在第一封装体1的衬底面制作第二重布线层4。第二重布线层4的制作方法可以参考第一重布线层2的制作方法，本实施例不作赘述。
由于第一金属柱11和第一芯片12的凸块直接接触衬底100，因此，制作第二重布线层4后，如图12所示，第一金属柱11与第一芯片12分别与第二重布线层4接触且电连接，使得第一金属柱11的两端分别与第一重布线层2和第二重布线层4电连接，实现了第一重布线层2和第二重布线层4的连接及信号传输。本实施例中，第一金属柱11的厚度等于第一芯片12的厚度，使得第一金属柱11的设置并为额外增加第一封装体1的厚度，还能够实现芯片与芯片之间、芯片与金属层之间的连接。
S6、在第二重布线层4远离第一封装体1的表面制作相互间隔开的第二金属柱51及倒装的第三芯片52，并对第三芯片52及第二金属柱51塑封处理，得到第三封装体5，第三芯片52及第二金属柱51分别电连接于第二重布线层4。
需要说明的是，当第一封装体1包括被动元件组7时，每个被动元件71分别接触并电连接于第二重布线层4。
可选地，步骤S6可以包括如下步骤：
S61、在第二重布线层4远离第一封装体1的表面通过电镀的方式形成第二金属柱51，第二金属柱51与第二重布线层4电连接。
在步骤S61中，第二金属柱51与第一金属柱11分别设置在第二重布线层4的上下两侧。图13为形成第二金属柱51后的结构。第二金属柱51的形成方式与第一金属柱11的形成方式相同，本实施例在此不做赘述。第二金属柱51间隔设有多个。
S62、将第三芯片52倒装在第二重布线层4远离第一封装体1的表面，第三芯片52与第二重布线层4电连接。
在步骤S62中，第二重布线层4设置第二金属柱51的表面设置第三芯片52，且第三芯片52的凸块朝向第二重布线层4，使得第三芯片52的信号能够通过第二重布线层4及第二金属柱51传出。第三芯片52设有一个或多个，本实施例对此不作限定。图14为第二重布线层4上设置第三芯片52后的示意图。
S63、通过塑封工艺将第二金属柱51及第三芯片52塑封，得到第二临时塑封体300。
在步骤S63中，通过塑封工艺将第二金属柱51和第三芯片52塑封，并得到用于供第二金属柱51和第三芯片52嵌设的胶体。如图15所示，该胶体的高度大于第二金属柱51和第三芯片52。本实施例中，第三封装体5包括第三塑封体53，第二金属柱51和第三芯片52嵌在第三塑封体53上。
S64、对第二临时塑封体300减薄处理，以露出第三芯片52的背面及第二金属柱51，并得到第三封装体5。
与处理第一临时塑封体300类似的方式处理第二临时塑封体300，并使第三芯片52的背面及第二金属柱51露出，得到如图16所示的第三封装体5。第三芯片52的厚度等于第二金属柱51的高度。本实施例中，第三封装体5包括第二金属柱51、第三芯片52及第三塑封体53。
S7、在第三封装体5远离第一封装体1的表面上制作焊球6，得到晶圆，焊球6通过第二金属柱51电连接于第二重布线层4。
本实施例中，通过焊球6将多芯片封装结构的电信号传出，具体地，第一芯片12的电信号通过第二重布线层4及第二金属柱51传至焊球6，第二芯片31的电信号通过第一重布线层2、第一金属柱11、第二重布线层4及第二金属柱51传至焊球6，第三芯片52的电信号通过第二重布线层4及第二金属柱51传至焊球6。本实施例中的晶圆如图18所示。
本实施例提供的多芯片封装方法，第一芯片12的电信号通过第二重布线层4及第二金属柱51传至焊球6，第二芯片31的电信号通过第一重布线层2、第一金属柱11、第二重布线层4及第二金属柱51传至焊球6，第三芯片52的电信号通过第二重布线层4及第二金属柱51传至焊球6，通过第一重布线层2及第二重布线层4实现了芯片与芯片之间的短距离电信号连接及芯片电信号的传出，无需TSV的制作工艺，具有较低的制造难度和较低的成本。
并且，本实施例中，芯片的密度较高，封装的厚度相较于现有技术有所降低，三维立体结构的多芯片封装结构的热性能有所提高。
可选地，步骤S7包括如下步骤：
S71、通过光刻工艺在第三封装体5远离第一封装体1的表面上制作球下焊垫层8。
在步骤S71中，在第三封装体5上形成球下焊垫层8，本实施例中，如图17所示，球下焊垫层8包括多个球下焊垫81，多个球下焊垫81与多个第二金属柱51一一对应，且每个球下焊垫81与其对应的第二金属柱51接触且电连接。可选地，球下焊垫层8可以通过光刻工艺制造，光刻工艺包括涂覆光刻胶、曝光、显影、刻蚀、电铸(或电镀)等步骤，具体参见现有技术。
S72、在球下焊垫层8上通过电镀或植球的方式制作焊球6。
在步骤S72中，在球下焊垫层8远离第三封装体5的表面制作焊球6，得到如图18所示的结构。其中，焊球6设有多个，多个焊球6与多个球下焊垫81一一对应，且每个焊球6与其对应的球下焊垫81接触且电连接。可选地，焊球6为微凸点或吸球，本实施例对此不作限定。
可选地，如图1所示，在步骤S7之后，多芯片封装方法还包括如下步骤：
S8、将晶圆通过切割分割成多颗单体，每棵单体包括至少一个第一芯片12、第二芯片31或第三芯片52，并且，每棵单体包括至少两个焊球6。
S9、将单体的焊球6与转接件9焊接，得到多芯片封装体。
在步骤S9中，将每棵单体的所有焊球6分别焊接在转接件9上，得到如图2所示的多芯片封装体。其中，如图2所示，转接件9包括转接板91及多个转接凸部92，多个焊球6分别焊接于转接板91的上表面，多个转接凸部92设于转接板91的下表面，且转接凸部92的数量大于焊球6的数量。
实施例二
本实施例提供了一种多芯片封装结构，通过上述多芯片封装方法制造，具有较小的厚度和较高的热性能。
如图2所示，多芯片封装结构包括自上往下依次设置的第二封装体3、第一重布线层2、第一封装体1、第二重布线层4及第三封装体5。
其中，第一封装体1包括第一金属柱11、第一芯片12及第一塑封体13，第一金属柱11的两端分别电连接于第一重布线层2和第二重布线层4。第二封装体3包括第二芯片31及第二塑封体32，第二芯片31电连接于第一重布线层2。第三封装体5包括第二金属柱51、第三芯片52及第三塑封体53，第二金属柱51的一端电连接于第二重布线层4，第一芯片12及第三芯片52分别电连接于第二重布线层4，第一芯片12、第二芯片31及第三芯片52的电信号分别通过第二金属柱51传出。
本实施例提供的多芯片封装结构，第一芯片12的电信号通过第二重布线层4及第二金属柱51传至焊球6，第二芯片31的电信号通过第一重布线层2、第一金属柱11、第二重布线层4及第二金属柱51传至焊球6，第三芯片52的电信号通过第二重布线层4及第二金属柱51传至焊球6，通过第一重布线层2及第二重布线层4实现了芯片与芯片之间的短距离电信号连接及芯片电信号的传出，制作过程无需TSV的制作工艺，具有较低的制造难度和较低的成本。
可选地，第一封装体1还包括多个被动元件组7，每个被动元件组7包括至少一个被动元件71，被动元件71为电容、电阻或电感。本实施例中，每个被动元件71均电连接于第二重布线层4，以使得被动元件71能够正常工作。
可选地，本实施例中，多芯片封装结构还包括一一对应的多个球下焊垫81和多个焊球6。多个球下焊垫81形成球下焊垫层8。第二金属柱51设有多个，多个球下焊垫81与多个第二金属柱51一一对应，且每个球下焊垫81电连接于与其对应的第二金属柱51的另一端，每个焊球6焊接于与其对应的球下焊垫81。
本实施例中，如图2所示，多芯片封装结构还包括转接件9。其中，转接件9包括转接板91及多个转接凸部92，多个焊球6分别焊接于转接板91的上表面，多个转接凸部92固设于转接板91的下表面，且转接凸部92的数量大于焊球6的数量，以实现传输点的加密。本实施例中，转接凸部92呈球状。转接板91可以为PCB板。
以上实施方式只是阐述了本发明的基本原理和特性，本发明不受上述实施方式限制，在不脱离本发明精神和范围的前提下，本发明还有各种变化和改变，这些变化和改变都落入要求保护的本发明范围内。本发明要求保护范围由所附的权利要求书及其等效物界定。

Claims (10)

1.多芯片封装方法，其特征在于，包括如下步骤：
S1、在固设有第一金属柱(11)的衬底(100)上倒装第一芯片(12)，所述第一金属柱(11)和所述第一芯片(12)间隔设置于所述衬底(100)的同一表面；
S2、通过塑封工艺将所述第一金属柱(11)及所述第一芯片(12)塑封，得到设于所述衬底(100)上的第一封装体(1)，所述第一封装体(1)包括第一金属柱(11)、第一芯片(12)及第一塑封体(13)；
S3、在所述第一封装体(1)远离所述衬底(100)的表面上制作第一重布线层(2)，所述第一金属柱(11)电连接于所述第一重布线层(2)；
S4、在所述第一重布线层(2)远离所述衬底(100)的表面上倒装第二芯片(31)，并对所述第二芯片(31)塑封处理，得到设于所述第一重布线层(2)上的第二封装体(3)，所述第二封装体(3)包括第二芯片(31)及第二塑封体(32)，所述第二芯片(31)电连接于所述第一重布线层(2)，所述第一重布线层(2)介于所述第一芯片(12)和所述第二芯片(31)之间；
S5、去除所述衬底(100)，并在所述第一封装体(1)远离所述第二封装体(3)的表面制作第二重布线层(4)，所述第一芯片(12)及所述第一金属柱(11)分别电连接于所述第二重布线层(4)；
S6、在所述第二重布线层(4)远离所述第一封装体(1)的表面制作相互间隔开的第二金属柱(51)及倒装第三芯片(52)，并对所述第三芯片(52)及所述第二金属柱(51)塑封处理，得到第三封装体(5)，所述第三芯片(52)及所述第二金属柱(51)分别电连接于所述第二重布线层(4)；
S7、在所述第三封装体(5)远离所述第一封装体(1)的表面上制作焊球(6)，得到晶圆，所述焊球(6)通过所述第二金属柱(51)电连接于所述第二重布线层(4)。
2.根据权利要求1所述的多芯片封装方法，其特征在于，所述第一封装体(1)还包括被动元件组(7)，在步骤S2之前，所述多芯片封装方法还包括将所述被动元件组(7)贴装到所述衬底(100)上，在步骤S2中，通过所述塑封工艺将所述第一金属柱(11)、所述第一芯片(12)及所述被动元件组(7)塑封。
3.根据权利要求1所述的多芯片封装方法，其特征在于，步骤S2包括：
S21、通过塑封工艺将所述第一金属柱(11)及所述第一芯片(12)塑封，得到第一临时塑封体(200)；
S22、对所述第一临时塑封体(200)减薄处理，以露出所述第一芯片(12)的背面及所述第一金属柱(11)，并得到第一封装体(1)。
4.根据权利要求1所述的多芯片封装方法，其特征在于，步骤S6包括：
S61、在所述第二重布线层(4)远离所述第一封装体(1)的表面通过电镀的方式形成第二金属柱(51)，所述第二金属柱(51)与所述第二重布线层(4)电连接；
S62、将所述第三芯片(52)倒装在所述第二重布线层(4)远离所述第一封装体(1)的表面，所述第三芯片(52)与所述第二重布线层(4)电连接；
S63、通过塑封工艺将所述第二金属柱(51)及所述第三芯片(52)塑封，得到第二临时塑封体(300)；
S64、对所述第二临时塑封体(300)减薄处理，以露出所述第三芯片(52)的背面及所述第二金属柱(51)，并得到第三封装体(5)。
5.根据权利要求1所述的多芯片封装方法，其特征在于，步骤S7包括：
S71、通过光刻工艺在所述第三封装体(5)远离所述第一封装体(1)的表面上制作球下焊垫层(8)；
S72、在所述球下焊垫层(8)上通过电镀或植球的方式制作焊球(6)。
6.根据权利要求1所述的多芯片封装方法，其特征在于，在步骤S7之后，所述多芯片封装方法还包括如下步骤：
S8、将所述晶圆通过切割分割成多颗单体；
S9、将所述单体的焊球(6)与转接件(9)焊接，得到多芯片封装体。
7.多芯片封装结构，其特征在于，包括自上往下依次设置的第二封装体(3)、第一重布线层(2)、第一封装体(1)、第二重布线层(4)及第三封装体(5)；
所述第一封装体(1)包括第一金属柱(11)、第一芯片(12)及第一塑封体(13)，所述第一金属柱(11)的两端分别电连接于所述第一重布线层(2)和所述第二重布线层(4)；
所述第二封装体(3)包括第二芯片(31)及第二塑封体(32)，所述第二芯片(31)电连接于所述第一重布线层(2)；
所述第三封装体(5)包括第二金属柱(51)及第三芯片(52)，所述第二金属柱(51)的一端电连接于所述第二重布线层(4)，所述第一芯片(12)及所述第三芯片(52)分别电连接于所述第二重布线层(4)，所述第一芯片(12)、所述第二芯片(31)及所述第三芯片(52)的电信号分别通过所述第二金属柱(51)传出。
8.根据权利要求7所述的多芯片封装结构，其特征在于，所述第一封装体(1)还包括多个被动元件组(7)，每个所述被动元件组(7)包括至少一个被动元件(71)，所述被动元件(71)为电容、电阻或电感。
9.根据权利要求7所述的多芯片封装结构，其特征在于，还包括一一对应的多个球下焊垫(81)和多个焊球(6)，所述第二金属柱(51)设有多个，多个所述球下焊垫(81)与多个所述第二金属柱(51)一一对应，且所述球下焊垫(81)电连接于与其对应的所述第二金属柱(51)的另一端，所述焊球(6)焊接于与其对应的所述球下焊垫(81)。
10.根据权利要求9所述的多芯片封装结构，其特征在于，还包括转接件(9)，所述转接件(9)包括转接板(91)及多个转接凸部(92)，多个所述焊球(6)分别焊接于所述转接板(91)的上表面，多个所述转接凸部(92)设于所述转接板(91)的下表面，且所述转接凸部(92)的数量大于所述焊球(6)的数量。
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