CN102024781A - 集成电路结构 - Google Patents

集成电路结构 Download PDF

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Publication number
CN102024781A
CN102024781A CN2010102837900A CN201010283790A CN102024781A CN 102024781 A CN102024781 A CN 102024781A CN 2010102837900 A CN2010102837900 A CN 2010102837900A CN 201010283790 A CN201010283790 A CN 201010283790A CN 102024781 A CN102024781 A CN 102024781A
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China
Prior art keywords
metal
guide hole
integrated circuit
semiconductor substrate
substrate
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CN102024781B (zh
Inventor
陈明发
邱文智
眭晓林
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Advanced Manufacturing Innovation Co
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路结构，包括一半导体基板，具有一正面与一背面；一导孔，贯穿半导体基板；一金属结构，位于半导体基板的背面上，金属结构包括一金属垫，覆盖并接触导孔；以及一金属线，位于导孔上，其中金属线包括一双镶嵌结构；以及一凸块，于金属线上。使用双镶嵌工艺形成背侧内连线结构，可堆叠多个内连线层以提供大的可绕线性。

Description

集成电路结构
技术领域
本发明涉及集成电路结构，特别涉及形成于晶片背侧上且连接贯穿基板导孔(through-substrate via；TSV)的内连线结构。
背景技术
由于各种电子组件(例如晶体管、二极管、电阻、电容等)的集成密度(integration density)不断提高，半导体工业已经历了连续的快速成长。在大多数的情况下，集成密度的提高是来自于最小特征尺寸(minimum feature size)一再地缩小，且最小特征尺寸的缩小可使更多的组件集成到一给定的芯片区域中。
集成的进步实际上是在二维(平面)上的进步，因为集成组件所占据的体积基本上是在半导体晶片的表面上。虽然光刻技术的显著提升已使得二维集成电路的形成有显著的进步，然而，在二维上可达到的密度有物理上的限制。这些限制其中之一是需要制作这些组件的最小尺寸。再者，当把更多的元件置入一芯片中时，会需要更复杂的设计。
当元件的数量增加时，一额外的限制是来自于元件间的内连线的数量与长度的显著增加。当内连线的数量与长度增加时，电路的RC延迟(RC delay)与耗电量(power consumption)都会增加。
在欲解决上述限制的诸多努力中，普遍使用的是三维的集成电路(three-dimensional integrated circuit，3D IC)以及堆叠式芯片(stacked dies)。因此，将贯穿基板导孔用于三维的集成电路以及堆叠式芯片中以连接芯片。在此，贯穿基板导孔常被用来连接一芯片上的集成电路至该芯片的背侧。此外，贯穿基板导孔也被用来提供短接地路径，以使集成电路经由芯片的背侧接地，其中一接地金属膜可覆盖芯片的背侧。
由于接合多个包括贯穿基板导孔的芯片需要相对大的贯穿基板导孔间距，因此，贯穿基板导孔的位置受到限制且贯穿基板导孔的间距需要够大以提供例如焊球足够的空间。此外，以现行的形成晶片背侧结构的方法，使贯穿基板导孔的电性连接结构远离各自的贯穿基板导孔是不可能的。
发明内容
为克服现有技术中的缺陷，本发明一实施例提供一种集成电路结构，包括一半导体基板，具有一正面与一背面；一导孔，贯穿半导体基板；一金属结构，位于半导体基板的背面上，金属结构包括一金属垫，覆盖并接触导孔；以及一金属线，位于导孔上，其中金属线包括一双镶嵌结构；以及一凸块，于金属线上。
本发明另一实施例提供一种集成电路结构，包括一半导体基板，具有一正面与一背面；一导孔，位于半导体基板中；一第一金属结构，从半导体基板的背面延伸至半导体基板中并接触导孔；以及一凸块，于第一金属结构上并电性连接第一金属结构。
本发明又一实施例提供一种集成电路结构，包括一半导体基板，具有一正面与一背面；一导孔，贯穿半导体基板；一第一金属结构，形成于半导体基板的背面上并接触导孔，其中第一金属结构包括一双镶嵌结构；以及一凸块，形成于第一金属结构上。
使用双镶嵌工艺形成背侧内连线结构，可堆叠多个内连线层以提供大的可绕线性。
附图说明
图1-图11、图12A、图12B示出本发明一实施例的制作一背侧内连线结构的中间阶段的剖面图，其中一基板的背面以及一贯穿基板导孔为凹陷的。
图13-图22、图23A、图23B示出本发明另一实施例的制作一背侧内连线结构的中间阶段的剖面图，其中一基板的背面是凹陷的。
图24-图28、图29A、图29B示出本发明又一实施例的制作一背侧内连线结构的中间阶段的剖面图，其中背侧内连线结构形成在一基板的背面上。
其中，附图标记说明如下：
2～芯片；
10～基板；
10b～背面；
10f～前侧；
12～内连线结构；
14～接垫；
15～方块；
20～贯穿基板导孔；
22～绝缘层；
24～开口；
25～载体；
26、31～光致抗蚀剂；
27～(沟槽)开口；
28～底部；
30～介电绝缘层；
32、128、148、236～导电阻挡层；
33、136、226～导孔开口；
34～铜；
36～金属结构；
36-1～金属线；
36-2～金属结构、金属垫；
38、48、222～介电层；
40～光致抗蚀剂；
42～凸块；
46、220～蚀刻终止层；
50、146～导孔；
52～金属线；
60～附加层、内连线附加层；
124、124’～介电层；
125～介电层；
126～开口；
130～金属材料；
132～金属线/垫；
132-1～金属结构、金属垫；
132-2、234～金属线；
134～光致抗蚀剂；
138、228～沟槽开口；
140～光致抗蚀剂、附加光致抗蚀剂、图案化光致抗蚀剂；
144～金属线；
232～通孔；
D1～凹陷深度；
D2～回蚀刻深度。
具体实施方式
以下将详述本发明的多个实施例的制作与使用方式。然应注意的是，这些实施例提供许多可供应用的发明概念，其可在多种特定的环境中实施。文中所讨论的特定实施例仅用以说明以特定的方式去制作与使用本发明，并非用以限制本发明的范围。
本发明提供一连接至贯穿基板导孔的背侧连线结构及其形成方法。以下将说明制作一实施例的中间阶段，并讨论实施例的多种变化。在全部的附图与说明实施例中，相似的标号将用以标示相似的元件。
请参照图1，提供芯片2，其内包括基板10与集成电路(未示出)。芯片2可为一部分的晶片。基板10可为一半导体基板，例如一块状硅基板(bulk silicon substrate)，但基板10亦可包括其他的半导体材料，例如三族、四族及/或五族元素。有源式的半导体元件(例如晶体管，以方块15表示)可形成在基板10的前侧10f上。在本文中，“背侧”一词是指基板10相对于具有有源式半导体元件的一侧。内连线结构12形成在基板10的前侧10f上并连接至有源式半导体元件，其中内连线结构12包括金属线以及形成于其内的导孔(未示出)。金属线以及导孔可以是由铜或是铜合金所构成的，并可用熟知的镶嵌工艺(damascene process)来制作。内连线结构12可包括一般所知的层间介电层(inter-layer dielectric，ILD)以及金属间介电层(inter-metal dielectrics，IMDs)。接垫14形成在基板10的前侧10f上。
贯穿基板导孔20形成于基板10中，并从前侧10f延伸进基板10中。在一实施例中，如图1所示，在形成内连线结构12之前，利用先导孔法(Via-first approach)形成贯穿基板导孔20。因此，贯穿基板导孔20只延伸至内连线结构12中的层间介电层而不延伸至金属间介电层中，其中层间介电层用以覆盖有源元件。在其他实施例中，在形成内连线结构12之后，利用后导孔法(via-last approach)形成贯穿基板导孔20。因此，贯穿基板导孔20贯穿基板10与内连线结构12。绝缘层(isolation layer)22形成于贯穿基板导孔20的侧壁与端部上，并使贯穿基板导孔20与基板10电性绝缘。绝缘层22一般可用介电材料来形成，其中介电材料例如为氮化硅、氧化硅(例如四乙基硅酸盐氧化物，tetra-ethyl-ortho-silicate oxide，TEOS oxide)及其相似物。将芯片2以及对应的晶片粘着至载体25。
请参照图2，进行一背侧研磨工艺(backside grinding)，以使贯穿基板导孔20经由基板10的背面10b暴露出来。可利用贯穿基板导孔20作为背侧研磨工艺中的终止层(stop layer)。然后，如图3所示，使贯穿基板导孔20凹陷，因此，其上表面低于基板10的背面10b。凹陷深度D1可以是约略大于0.5微米，而且在一示范性的实施例中可为3微米。由于该凹陷工艺，形成开口24。
图4介绍基板10的凹陷工艺，且是以光致抗蚀剂26为掩模来进行凹陷工艺。由于该凹陷工艺，开口24的水平尺寸增加并大于贯穿基板导孔20的水平尺寸。尽管图4所示出的背面10b的开口24的底部28齐平于贯穿基板导孔20的外露端。在其他实施例中，底部28亦可以是高于或是低于贯穿基板导孔20的外露端，亦如同(图4中的)虚线所示。开口24与(沟槽)开口27同时形成。
请参照图5，沉积介电绝缘层30。沉积方法包括低温化学气相沉积(10w-temperature chemical vapor deposition，LTCVD)，但是亦可使用其他普遍使用的方法。在一示范性的实施例中，介电绝缘层30包括氮化硅(silicon nitride，SiNx)且介电绝缘层30的厚度可为数百埃(angstrom)。然后，如图6所示，通过涂布光致抗蚀剂31以及进行光刻工艺使介电绝缘层30的覆盖贯穿基板导孔20的端部的部分暴露于一导孔开口(via opening)33中，以使之后形成的凸块(bump)可电性连接至贯穿基板导孔20。
图7-图9示出重配置线路(redistribution line)与接垫的工艺。请参照图7，例如以溅镀(sputtering)的方法形成导电阻挡层(conductive barrier layer)32，导电阻挡层32的材质可包括钛、氮化钛(titanium nitride)、钽(tantalum)、氮化钽(tantalum nitride)或其相似物。然后，镀铜34(如图8所示)。之后，进行化学机械研磨(chemical mechanical polish，CMP)以形成金属结构(metal feature)36(图中标示为36-1与36-2)，其最终结构如图9所示。金属结构36可包括金属线36-1，其实际上可连接其他的贯穿基板导孔(未示出)。因此，金属线36-1用以作为重配置线路。金属结构36-2可为金属垫或金属线。金属垫的尺寸可大于贯穿基板导孔20的尺寸(当俯视金属垫与贯穿基板导孔20时)，而且在全部的水平方向上，金属垫可延伸过贯穿基板导孔20的边缘。因此，金属垫36-2与贯穿基板导孔20之间的接合面积(interface area)大且具有可靠的连接，故接触阻抗(contact resistance)小。再者，金属垫36-2对准贯穿基板导孔20的准确度要求(accuracy requirement)可较为宽松。
图10-图12A示出凸块42的工艺。请参照图10，全面沉积介电层38。在一示范性的实施例中，介电层38包括氮化硅，且介电层38的厚度可例如约为0.2微米。之后，如图11所示，利用光致抗蚀剂40在介电层38中形成一开口，以暴露出金属垫36-2。图12A示出凸块42的工艺，凸块42亦可称为微凸块(micro-bump，U-bump)，因为其水平尺寸(长度或宽度)约小于30微米。凸块42的形成方法包括电化学镀(electrical chemical plating，ECP)、无电镀(electroless plating)以及浸镀(immersion)。产生的凸块42可具有化镍浸金(electroless nickel immersion gold，ENIG)结构、化镍化钯浸金(nickel electroless palladium immersion gold，ENEPIG)结构或是镍钯结构(nickel palladium structure)。可以了解的是，虽然图12A示出的是凸块42位于金属垫36-2正上方，但凸块42也可不位于金属垫36-2正上方而是实际上通过重配置线路(类似金属线36-1)连接金属垫36-2，其中重配置线路与金属结构36同时形成。
图12B示出本发明的另一实施例。可形成额外的重配置线路层以取代将凸块42形成在金属垫36-2的正上方。举例来说，可在金属垫36-2与凸块42之间插入一附加层(additional layer)60，附加层60包括蚀刻终止层(etch stop layer)46、介电层48、导孔50以及金属线52。若是情况需要，可在附加层60上堆叠更多相似于附加层60的膜层以增加内连线结构背侧的可绕线性(routability)。附加层60的形成细节可实质上与图18-21相同，其将于下文中详述。
图13-图23B示出本发明另一实施例。本实施例一开始的步骤如同图1-2所示。之后，请参照图13，从背侧回蚀刻(etch back)基板10，以使贯穿基板导孔20突出于基板10的背面。在一示范性的实施例中，回蚀刻深度D2约大于0.5微米，且可约为1微米。也可从贯穿基板导孔20的顶面回蚀刻绝缘层22，以使绝缘层22低于贯穿基板导孔20的顶面例如约0.5微米。因此，暴露出贯穿基板导孔20的侧壁的局部。
请参照图14，介电层124形成在基板10的背面并覆盖贯穿基板导孔20。在一实施例中，介电层124是由聚酰亚胺(polyimide)所构成，且其厚度可约大于2微米，一示范性的厚度约为3微米。在另一实施例中，也可使用其他的介电材料。
图15-图17示出本发明一实施例的金属线的工艺。请参照图15，例如在一光致抗蚀剂(未示出)的帮助下，通过蚀刻介电层124形成多个开口126。在一实施例中，例如用时间模式(time mode)来控制开口的形成过程，以使贯穿基板导孔20经由其中一开口126暴露出来，同时，保留介电层124的底部(标示为介电层124’)以分隔开口126与基板10。
请参照图16，进行预清洗工艺(pre-clean)并例如以溅镀的方式沉积导电阻挡层(conductive barrier layer)128。导电阻挡层128可包括钛、钽或其相似物。然后，将金属材料130镀至高于介电层124的顶面。金属材料130可包括铜，但也可使用其他的金属，例如铝、钨或其相似物。之后，进行化学机械研磨(如图17所示)，从而形成金属线/垫132(标示为132-1与132-2)。金属线132-2可电性连接芯片中的多个贯穿基板导孔之一。因此，金属线132-2可用来作为重配置线路。金属结构132-1可为金属垫或是金属线(metal trace)。金属垫的尺寸(当俯视时)可大于贯穿基板导孔20的尺寸，其中，在俯视图中，在所有的横向方向上，金属垫132-1可延伸超过贯穿基板导孔20的边缘。
图18-图21示出本发明一实施例的内连线的附加层的工艺。请参照图18，形成介电层125。在一实施例中，介电层125是由聚酰亚胺所构成，其厚度可约为数微米，例如约为2.5微米。之后，涂布并图案化光致抗蚀剂134。然后，通过图案化光致抗蚀剂134蚀刻介电层125直到暴露出金属线132-2，以形成多个导孔开口136。
请参照图19，移除光致抗蚀剂134，并形成以及图案化附加光致抗蚀剂140。之后，如图20所示，通过图案化光致抗蚀剂140进一步蚀刻介电层125以形成多个沟槽开口(trench opening)138。可用时间模式来进行蚀刻工艺，以使蚀刻工艺停止于介电层125的中间。然后，例如以灰化(ashing)的方式移除光致抗蚀剂140。可以了解的是，图18-图20所示的步骤为先导孔法，其是在沟槽开口138形成之前形成导孔开口136。本领域普通技术人员将可了解图20所示的结构可以先沟槽法形成，其中图19-图20所示的步骤可在图18所示的步骤之前进行。
图21示出本发明一实施例的包括金属线144与导孔146的镶嵌结构的工艺，其可包括沉积导电阻挡层148(例如一钛层)、镀铜以及进行化学机械研磨以移除过多的铜。图22-23A示出介电层38与凸块42的工艺。该工艺基本上相同于上述实施例，故于此不再重复。图23B示出本发明另一实施例，其中金属线144与导孔146形成于介电层124中。
图24-图29B示出本发明又一实施例。本实施例的初始步骤与图1-图2相同。之后，如图24所示，形成蚀刻终止层220。在一实施例中，蚀刻终止层220是由氮化硅所形成的，且其厚度可例如约为750埃
Figure BSA00000272680300081
然后，在蚀刻终止层220上形成介电层222。在一实施例中，可以各种化学气相沉积法中的一种来形成介电层222，且介电层222可包括例如氧化物。化学气相沉积的介电层222的厚度可例如约为8000埃
Figure BSA00000272680300082
在另一实施例中，介电层222可以是由聚酰亚胺所构成的，因此，可具有一厚度明显大于以化学气相沉积法制成的介电层的厚度。聚酰亚胺所构成的介电层222的厚度约可大于2微米，且在一示范性的实施例中，可约为5微米。
图25-图27示出导孔开口226与沟槽开口228的工艺。形成细节实质上与图18-图20相同，故于此不再重复。之后，如图28所示，形成一双镶嵌结构(dual damascene structure)，双镶嵌结构包括通孔232以及覆盖于通孔232上的金属线234，其中金属线234可以是由铜所构成的。亦形成导电阻挡层236。
图29A示出介电层38以及凸块42的工艺。介电层38以及凸块42的材质以及工艺可基本上与图10-12A相同。图29B示出另一具有内连线附加层60的实施例，内连线附加层60包括附加的双镶嵌结构。若是有必要的话，可插入更多的内连线层。
这些实施例具有许多优点。使用双镶嵌工艺形成背侧内连线结构，可堆叠多个内连线层以提供大的可绕线性。通过在基板上制作凹槽以形成金属垫(图10中的36-2以及图17中的132-1)并使金属垫接触贯穿基板导孔，金属垫可具有大尺寸，以使金属垫对准贯穿基板导孔的准确度要求可较为宽松。再者，由于金属垫与其下的贯穿基板导孔的接触面积大，因此，可降低接触阻抗。
本发明虽以优选实施例公开如上，然其并非用以限定本发明的范围，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (10)

1.一种集成电路结构，包括：
一半导体基板，具有一正面与一背面；
一导孔，贯穿该半导体基板；
一金属结构，位于该半导体基板的背面上，该金属结构包括：
一金属垫，覆盖并接触该导孔；以及
一金属线，位于该导孔上，其中该金属线包括一双镶嵌结构；以及
一凸块，于该金属线上。
2.如权利要求1所述的集成电路结构，其中该金属垫还包括：
一第一底面，接触该导孔的一顶面；以及
一第二底面，高于该半导体基板的该背面并低于该第一底面。
3.如权利要求1所述的集成电路结构，其中该双镶嵌结构与该金属垫位于同一介电层中。
4.如权利要求1所述的集成电路结构，其中该双镶嵌结构位于一该金属垫上的介电层中。
5.如权利要求1所述的集成电路结构，其中该金属垫的所有的水平尺寸分别大于该导孔的水平尺寸。
6.一种集成电路结构，包括：
一半导体基板，具有一正面与一背面；
一导孔，位于该半导体基板中；
一第一金属结构，从该半导体基板的该背面延伸至该半导体基板中并接触该导孔；以及
一凸块，位于该第一金属结构上并电性连接该第一金属结构。
7.如权利要求6所述的集成电路结构，还包括：
一第二金属结构，形成于该第一金属结构与该凸块之间，其中该第二金属结构包括一双镶嵌结构。
8.如权利要求6所述的集成电路结构，其中该第一金属结构的所有的水平尺寸分别大于该导孔的水平尺寸。
9.如权利要求6所述的集成电路结构，其中该第一金属结构包括一顶面，该顶面实质上与该半导体基板的该背面齐平。
10.如权利要求6所述的集成电路结构，其中该第一金属结构包括：
一导电阻挡层，接触该导孔；以及
一含铜的金属材料，位于该导电阻挡层上。
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US9716074B2 (en) 2017-07-25
TWI453879B (zh) 2014-09-21
CN102024781B (zh) 2013-04-17
KR101319701B1 (ko) 2013-10-17
US8791549B2 (en) 2014-07-29
US20140322909A1 (en) 2014-10-30
US9978708B2 (en) 2018-05-22
US20170005069A1 (en) 2017-01-05
US9449875B2 (en) 2016-09-20

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