TWI453879B - 積體電路結構 - Google Patents

積體電路結構 Download PDF

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Publication number
TWI453879B
TWI453879B TW099130601A TW99130601A TWI453879B TW I453879 B TWI453879 B TW I453879B TW 099130601 A TW099130601 A TW 099130601A TW 99130601 A TW99130601 A TW 99130601A TW I453879 B TWI453879 B TW I453879B
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TW
Taiwan
Prior art keywords
metal
substrate
integrated circuit
semiconductor substrate
dielectric layer
Prior art date
Application number
TW099130601A
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English (en)
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TW201112371A (en
Inventor
Ming Fa Chen
Wen Chih Chiou
Shau Lin Shue
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Taiwan Semiconductor Mfg
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Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201112371A publication Critical patent/TW201112371A/zh
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Publication of TWI453879B publication Critical patent/TWI453879B/zh

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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Description

積體電路結構
本發明關於積體電路結構，特別是關於形成於晶圓背側上且連接貫穿基板導孔(through-substrate via；TSV)的內連線結構。
由於各種電子組件(例如電晶體、二極體、電阻、電容等)的積體密度(integration density)不斷提高，半導體工業已經歷了連續的快速成長。在大多數的情況下，積體密度的提高是來自於最小特徵尺寸(minimum feature size)一再地縮小，且最小特徵尺寸的縮小可使更多的組件集成到一給定的晶片區域中。
積體的進步實際上是在二維(平面)上的進步，因為積體組件所佔據的體積基本上是在半導體晶圓的表面上。雖然微影技術的顯著提昇已使得二維積體電路的形成有顯著的進步，然而，在二維上可達到的密度有物理上的限制。這些限制其中之一是需要製作這些組件的最小尺寸。再者，當把更多的元件置入一晶片中時，會需要更複雜的設計。
當元件的數量增加時，一額外的限制是來自於元件間的內連線的數量與長度的顯著增加。當內連線的數量與長度增加時，電路的RC延遲(RC delay)與耗電量(power consumption)都會增加。
在欲解決上述限制的諸多努力中，普遍使用的是三維的積體電路(three-dimensional integrated circuit，3D IC)以及堆疊式晶片(stacked dies)。因此，將貫穿基板導孔用於三維的積體電路以及堆疊式晶片中以連接晶片。在此，貫穿基板導孔常被用來連接一晶片上的積體電路至該晶片的背側。此外，貫穿基板導孔亦被用來提供短接地路徑，以使積體電路經由晶片的背側接地，其中一接地金屬膜可覆蓋晶片的背側。
由於接合多個包括貫穿基板導孔的晶片需要相對大的貫穿基板導孔間距，因此，貫穿基板導孔的位置受到限制且貫穿基板導孔的間距需要夠大以提供例如銲球足夠的空間。此外，以現行的形成晶圓背側結構的方法，使貫穿基板導孔的電性連接結構遠離各自的貫穿基板導孔是不可能的。
本發明一實施例提供一種積體電路結構，包括一半導體基板，具有一正面與一背面；一導孔，貫穿半導體基板；一金屬結構，位於半導體基板的背面上，金屬結構包括一金屬墊，覆蓋並接觸導孔；以及一金屬線，位於導孔上，其中金屬線包括一雙鑲嵌結構；以及一凸塊，於金屬線上。
本發明另一實施例提供一種積體電路結構，包括一半導體基板，具有一正面與一背面；一導孔，位於半導體基板中；一第一金屬結構，從半導體基板的背面延伸至半導體基板中並接觸導孔；以及一凸塊，於第一金屬結構上並電性連接第一金屬結構。
本發明又一實施例提供一種積體電路結構，包括一半導體基板，具有一正面與一背面；一導孔，貫穿半導體基板；一第一金屬結構，形成於半導體基板的背面上並接觸導孔，其中第一金屬結構包括一雙鑲嵌結構；以及一凸塊，形成於第一金屬結構上。
以下將詳述本發明之多個實施例的製作與使用方式。然應注意的是，這些實施例提供許多可供應用的發明概念，其可在多種特定的環境中實施。文中所討論的特定實施例僅用以說明以特定的方式去製作與使用本發明，並非用以限制本發明之範圍。
本發明提供一連接至貫穿基板導孔的背側連線結構及其形成方法。以下將說明製作一實施例的中間階段，並討論實施例的多種變化。在全部的圖示與說明實施例中，相似之標號將用以標示相似之元件。
請參照第1圖，提供晶片2，其內包括基板10與積體電路(未繪示)。晶片2可為一部分的晶圓。基板10可為一半導體基板，例如一塊狀矽基板(bulk silicon substrate)，但基板10亦可包括其他的半導體材料，例如三族、四族及/或五族元素。主動式的半導體元件(例如電晶體，以方塊15表示)可形成在基板10的前側10f上。在本文中，『背側』一詞是指基板10相對於具有主動式半導體元件的一側。內連線結構12形成在基板10的前側10f上並連接至主動式半導體元件，其中內連線結構12包括金屬線以及形成於其內的導孔(未繪示)。金屬線以及導孔可以是由銅或是銅合金所構成的，並可用熟知的鑲嵌製程(damascene process)來製作。內連線結構12可包括一般所知的層間介電層(inter-layer dielectric，ILD)以及金屬間介電層(inter-metal dielectrics，IMDs)。接墊14形成在基板10的前側10f上。
貫穿基板導孔20形成於基板10中，並從前側10f延伸進基板10中。在一實施例中，如第1圖所示，在形成內連線結構12之前，利用先導孔法(Via-first approach)形成貫穿基板導孔20。因此，貫穿基板導孔20只延伸至內連線結構12中的層間介電層而不延伸至金屬間介電層中，其中層間介電層係用以覆蓋主動元件。在其他實施例中，在形成內連線結構12之後，利用後導孔法(via-last approach)形成貫穿基板導孔20。因此，貫穿基板導孔20貫穿基板10與內連線結構12。絕緣層(isolation layer)22形成於貫穿基板導孔20的側壁與端部上，並使貫穿基板導孔20與基板10電性絕緣。絕緣層22一般可用介電材料來形成，其中介電材料例如為氮化矽、氧化矽(例如四乙基矽酸鹽氧化物，tetra-ethyl-ortho-silicate oxide，TEOS oxide)及其相似物。將晶片2以及對應的晶圓黏著至載體25。
請參照第2圖，進行一背側研磨製程(backside grinding)，以使貫穿基板導孔20經由基板10的背面10b暴露出來。可利用貫穿基板導孔20作為背側研磨製程中的終止層(stop layer)。然後，如第3圖所示，使貫穿基板導孔20凹陷，因此，其上表面低於基板10的背面10b。凹陷深度D1可以是約略大於0.5微米，而且在一示範性的實施例中可為3微米。由於該凹陷製程，形成開口24。
第4圖介紹基板10的凹陷製程，且是以光阻26為罩幕來進行凹陷製程。由於該凹陷製程，開口24的水平尺寸增加並大於貫穿基板導孔20的水平尺寸。儘管第4圖所繪示的背面10b的開口24的底部28係齊平於貫穿基板導孔20的外露端。在其他實施例中，底部28亦可以是高於或是低於貫穿基板導孔20的外露端，亦如同(第4圖中的)虛線所示。開口24與(溝槽)開口27係同時形成。
請參照第5圖，沈積介電絕緣層30。沈積方法包括低溫化學氣相沈積(low-temperature chemical vapor deposition，LTCVD)，但是亦可使用其他普遍使用的方法。在一示範性的實施例中，介電絕緣層30包括氮化矽(silicon nitride，SiNx )且介電絕緣層30的厚度可為數百埃(angstrom)。然後，如第6圖所示，藉由塗佈光阻31以及進行微影製程使介電絕緣層30之覆蓋貫穿基板導孔20之端部的部分暴露於一導孔開口(via opening)33中，以使之後形成的凸塊(bump)可電性連接至貫穿基板導孔20。
第7-9圖繪示重配置線路(redistribution line)與接墊的製程。請參照第7圖，例如以濺鍍(sputtering)的方法形成導電阻障層(conductive barrier layer)32，導電阻障層32的材質可包括鈦、氮化鈦(titanium nitride)、鉭(tantalum)、氮化鉭(tantalum nitride)或其相似物。然後，鍍銅34(如第8圖所示)。之後，進行化學機械研磨(chemical mechanical polish，CMP)以形成金屬結構(metal feature)36(圖中標示為36-1與36-2)，其最終結構如第9圖所示。金屬結構36可包括金屬線36-1，其實際上可連接其他的貫穿基板導孔(未繪示)。因此，金屬線36-1係用以作為重配置線路。金屬結構36-2可為金屬墊或金屬線。金屬墊的尺寸可大於貫穿基板導孔20的尺寸(當俯視金屬墊與貫穿基板導孔20時)，而且在全部的水平方向上，金屬墊可延伸過貫穿基板導孔20的邊緣。因此，金屬墊36-2與貫穿基板導孔20之間的接合面積(interface area)大且具有可靠的連接，故接觸阻抗(contact resistance)小。再者，金屬墊36-2對準貫穿基板導孔20的準確度要求(accuracy requirement)可較為寬鬆。
第10-12A圖繪示凸塊42的製程。請參照第10圖，全面沈積介電層38。在一示範性的實施例中，介電層38包括氮化矽，且介電層38的厚度可例如約為0.2微米。之後，如第11圖所示，利用光阻40在介電層38中形成一開口，以暴露出金屬墊36-2。第12A圖繪示凸塊42的製程，凸塊42亦可稱為微凸塊(micro-bump，U-bump)，因為其水平尺寸(長度或寬度)約小於30微米。凸塊42的形成方法包括電化學鍍(electrical chemical plating，ECP)、無電鍍(electroless plating)以及浸鍍(immersion)。產生的凸塊42可具有化鎳浸金(electroless nickel immersion gold，ENIG)結構、化鎳化鈀浸金(nickel electroless palladium immersion gold，ENEPIG)結構或是鎳鈀結構(nickel palladium structure)。可以了解的是，雖然第12A圖繪示的是凸塊42位於金屬墊36-2正上方，但凸塊42亦可不位於金屬墊36-2正上方而是實際上透過重配置線路(類似金屬線36-1)連接金屬墊36-2，其中重配置線路與金屬結構36同時形成。
第12B圖繪示本發明之另一實施例。可形成額外的重配置線路層以取代將凸塊42形成在金屬墊36-2的正上方。舉例來說，可在金屬墊36-2與凸塊42之間插入一附加層(additional layer)60，附加層60包括蝕刻終止層(etch stop layer)46、介電層48、導孔50以及金屬線52。若是情況需要，可在附加層60上堆疊更多相似於附加層60的膜層以增加內連線結構背側的可繞線性(routability)。附加層60的形成細節可實質上與第18-21圖相同，其將於下文中詳述。
第13-23B圖繪示本發明另一實施例。本實施例一開始的步驟如同第1-2圖所示。之後，請參照第13圖，從背側回蝕刻(etch back)基板10，以使貫穿基板導孔20突出於基板10的背面。在一示範性的實施例中，回蝕刻深度D2約大於0.5微米，且可約為1微米。亦可從貫穿基板導孔20的頂面回蝕刻絕緣層22，以使絕緣層22低於貫穿基板導孔20的頂面例如約0.5微米。因此，暴露出貫穿基板導孔20的側壁的局部。
請參照第14圖，介電層124形成在基板10的背面並覆蓋貫穿基板導孔20。在一實施例中，介電層124是由聚亞醯胺(polyimide)所構成，且其厚度可約大於2微米，一示範性的厚度約為3微米。在另一實施例中，亦可使用其他的介電材料。
第15-17圖繪示本發明一實施例之金屬線的製程。請參照第15圖，例如在一光阻(未繪示)的幫助下，藉由蝕刻介電層124形成多個開口126。在一實施例中，例如用時間模式(time mode)來控制開口的形成過程，以使貫穿基板導孔20經由其中一開口126暴露出來，同時，保留介電層124的底部(標示為介電層124’)以分隔開口126與基板10。
請參照第16圖，進行預清洗製程(pre-clean)並例如以濺鍍的方式沈積導電阻障層(conductive barrier layer)128。導電阻障層128可包括鈦、鉭或其相似物。然後，將金屬材料130鍍至高於介電層124的頂面。金屬材料130可包括銅，但亦可使用其他的金屬，例如鋁、鎢或其相似物。之後，進行化學機械研磨(如第17圖所示)，從而形成金屬線/墊132(標示為132-1與132-2)。金屬線132-2可電性連接晶片中的多個貫穿基板導孔之一。因此，金屬線132-2可用來作為重配置線路。金屬結構132-1可為金屬墊或是金屬線(metal trace)。金屬墊的尺寸(當俯視時)可大於貫穿基板導孔20的尺寸，其中，在上視圖中，在所有的橫向方向上，金屬墊132-1可延伸超過貫穿基板導孔20的邊緣。
第18-21圖繪示本發明一實施例之內連線的附加層的製程。請參照第18圖，形成介電層125。在一實施例中，介電層125是由聚亞醯胺所構成，其厚度可約為數微米，例如約為2.5微米。之後，塗佈並圖案化光阻134。然後，藉由圖案化光阻134蝕刻介電層125直到暴露出金屬線132-2，以形成多個導孔開口136。
請參照第19圖，移除光阻134，並形成以及圖案化附加光阻140。之後，如第20圖所示，藉由圖案化光阻140進一步蝕刻介電層125以形成多個溝槽開口(trench opening)138。可用時間模式來進行蝕刻製程，以使蝕刻製程停止於介電層125的中間。然後，例如以灰化(ashing)的方式移除光阻140。可以了解的是，第18-20圖所示的步驟為先導孔法，其是在溝槽開口138形成之前形成導孔開口136。本領域具有通常知識者將可了解第20圖所示的結構可以先溝槽法形成，其中第19-20圖所示的步驟可在第18圖所示的步驟之前進行。
第21圖繪示本發明一實施例之包括金屬線144與導孔146的鑲嵌結構的製程，其可包括沈積導電阻障層148(例如一鈦層)、鍍銅以及進行化學機械研磨以移除過多的銅。第22-23A圖繪示介電層38與凸塊42的製程。該製程基本上相同於上述實施例，故於此不再重複。第23B圖繪示本發明另一實施例，其中金屬線144與導孔146形成於介電層124中。
第24-29B圖繪示本發明又一實施例。本實施例之初始步驟與第1-2圖相同。之後，如第24圖所示，形成蝕刻終止層220。在一實施例中，蝕刻終止層220是由氮化矽所形成的，且其厚度可例如約為750埃()。然後，在蝕刻終止層220上形成介電層222。在一實施例中，可以各種化學氣相沈積法中的一種來形成介電層222，且介電層222可包括例如氧化物。化學氣相沈積之介電層222的厚度可例如約為8000埃(8 K)。在另一實施例中，介電層222可以是由聚亞醯胺所構成的，因此，可具有一厚度係明顯大於以化學氣相沈積法製成的介電層的厚度。聚亞醯胺所構成的介電層222的厚度約可大於2微米，且在一示範性的實施例中，可約為5微米。
第25-27圖繪示導孔開口226與溝槽開口228的製程。形成細節實質上與第18-20圖相同，故於此不再重複。之後，如第28圖所示，形成一雙鑲嵌結構(dual damascene structure)，雙鑲嵌結構包括通孔232以及覆蓋於通孔232上的金屬線234，其中金屬線234可以是由銅所構成的。亦形成導電阻障層236。
第29A圖繪示介電層38以及凸塊42的製程。介電層38以及凸塊42的材質以及製程可基本上與第10-12A圖相同。第29B圖繪示另一具有內連線附加層60的實施例，內連線附加層60包括附加的雙鑲嵌結構。若是有必要的話，可插入更多的內連線層。
這些實施例具有許多優點。使用雙鑲嵌製程形成背側內連線結構，可堆疊多個內連線層以提供大的可繞線性。藉由在基板上製作凹槽以形成金屬墊(第10圖中的36-2以及第17圖中的132-1)並使金屬墊接觸貫穿基板導孔，金屬墊可具有大尺寸，以使金屬墊對準貫穿基板導孔的準確度要求可較為寬鬆。再者，由於金屬墊與其下的貫穿基板導孔的接觸面積大，因此，可降低接觸阻抗。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
2．．．晶片
10．．．基板
10b．．．背面
10f．．．前側
12．．．內連線結構
14．．．接墊
15．．．方塊
20．．．貫穿基板導孔
22．．．絕緣層
24．．．開口
25．．．載體
26、31．．．光阻
27．．．(溝槽)開口
28．．．底部
30．．．介電絕緣層
32、128、148、236．．．導電阻障層
33、136、226．．．導孔開口
34．．．銅
36．．．金屬結構
36-1．．．金屬線
36-2．．．金屬結構、金屬墊
38、48、222．．．介電層
40‧‧‧光阻
42‧‧‧凸塊
46、220‧‧‧蝕刻終止層
50、146‧‧‧導孔
52‧‧‧金屬線
60‧‧‧附加層、內連線附加層
124、124’‧‧‧介電層
125‧‧‧介電層
126‧‧‧開口
130‧‧‧金屬材料
132‧‧‧金屬線/墊
132-1‧‧‧金屬結構、金屬墊
132-2、234‧‧‧金屬線
134‧‧‧光阻
138、228‧‧‧溝槽開口
140‧‧‧光阻、附加光阻、圖案化光阻
144‧‧‧金屬線
232‧‧‧通孔
D1‧‧‧凹陷深度
D2‧‧‧回蝕刻深度
第1-11、12A、12B圖繪示本發明一實施例之製作一背側內連線結構的中間階段的剖面圖，其中一基板的背面以及一貫穿基板導孔為凹陷的。
第13-22、23A、23B圖繪示本發明另一實施例之製作一背側內連線結構的中間階段的剖面圖，其中一基板的背面是凹陷的。
第24-28、29A、29B圖繪示本發明又一實施例之製作一背側內連線結構的中間階段的剖面圖，其中背側內連線結構係形成在一基板的背面上。
2．．．晶片
10．．．基板
12．．．內連線結構
14．．．接墊
25．．．載體
30．．．介電絕緣層
32．．．導電阻障層
36．．．金屬結構
36-1．．．金屬線
36-2．．．金屬結構、金屬墊
38．．．介電層
42．．．凸塊

Claims (8)

  1. 一種積體電路結構，包括：一半導體基板，具有一正面與一背面；一導孔，貫穿該半導體基板；一金屬結構，位於該半導體基板的背面上，該金屬結構包括：一金屬墊，覆蓋並接觸該導孔；以及一金屬線，位於該導孔上，其中該金屬線包括一雙鑲嵌結構，該雙鑲嵌結構與該金屬墊位於同一介電層中；以及一凸塊，於該金屬線上。
  2. 如申請專利範圍第1項所述之積體電路結構，其中該金屬墊更包括：一第一底面，接觸該導孔的一頂面；以及一第二底面，高於該半導體基板的該背面並低於該第一底面。
  3. 如申請專利範圍第1項所述之積體電路結構，其中該雙鑲嵌結構位於一該金屬墊上的介電層中。
  4. 如申請專利範圍第1項所述之積體電路結構，其中該金屬墊之所有的水平尺寸分別大於該導孔的水平尺寸。
  5. 一種積體電路結構，包括：一半導體基板，具有一正面與一背面；一導孔，位於該半導體基板中；一第一金屬結構，從該半導體基板的該背面延伸至 該半導體基板中並接觸該導孔，該第一金屬結構包括一頂面，該頂面實質上與該半導體基板的該背面齊平；以及一凸塊，位於該第一金屬結構上並電性連接該第一金屬結構。
  6. 如申請專利範圍第5項所述之積體電路結構，更包括：一第二金屬結構，形成於該第一金屬結構與該凸塊之間，其中該第二金屬結構包括一雙鑲嵌結構。
  7. 如申請專利範圍第5項所述之積體電路結構，其中該第一金屬結構之所有的水平尺寸分別大於該導孔的水平尺寸。
  8. 如申請專利範圍第5項所述之積體電路結構，其中該第一金屬結構包括：一導電阻障層，接觸該導孔；以及一含銅的金屬材料，位於該導電阻障層上。
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Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8716867B2 (en) 2010-05-12 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Forming interconnect structures using pre-ink-printed sheets
US9190325B2 (en) * 2010-09-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation
KR101697573B1 (ko) 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
KR101789765B1 (ko) * 2010-12-16 2017-11-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR20120090417A (ko) * 2011-02-08 2012-08-17 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8853072B2 (en) 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
JP2012256679A (ja) 2011-06-08 2012-12-27 Elpida Memory Inc 半導体装置及びその製造方法
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
CN103000571B (zh) * 2011-09-19 2015-07-08 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法
WO2013062590A1 (en) * 2011-10-28 2013-05-02 Intel Corporation 3d interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
WO2013062593A1 (en) * 2011-10-28 2013-05-02 Intel Corporation 3d interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
US20130313710A1 (en) * 2012-05-22 2013-11-28 Micron Technology, Inc. Semiconductor Constructions and Methods of Forming Semiconductor Constructions
KR101931115B1 (ko) 2012-07-05 2018-12-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20140023055A (ko) * 2012-08-16 2014-02-26 에스케이하이닉스 주식회사 반도체 소자 및 그 형성 방법
KR102021884B1 (ko) * 2012-09-25 2019-09-18 삼성전자주식회사 후면 본딩 구조체를 갖는 반도체 소자
US8859425B2 (en) 2012-10-15 2014-10-14 Micron Technology, Inc. Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs
KR102018885B1 (ko) * 2012-12-20 2019-09-05 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US10483132B2 (en) * 2012-12-28 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US9466578B2 (en) * 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
US20150179580A1 (en) * 2013-12-24 2015-06-25 United Microelectronics Corp. Hybrid interconnect structure and method for fabricating the same
US9093503B1 (en) * 2014-01-03 2015-07-28 International Business Machines Corporation Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure
US9865523B2 (en) * 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
KR102222485B1 (ko) * 2014-09-18 2021-03-04 에스케이하이닉스 주식회사 관통 전극을 갖는 반도체 소자, 이를 구비하는 반도체 패키지 및 반도체 소자의 제조방법
DE102014115105B4 (de) 2014-10-09 2023-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
KR102279729B1 (ko) * 2014-12-01 2021-07-21 삼성전자주식회사 Ｔｓｖ, 전면 범핑 패드 및 후면 범핑 패드를 갖는 반도체 소자
US9431343B1 (en) 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
US9666523B2 (en) 2015-07-24 2017-05-30 Nxp Usa, Inc. Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof
US9472490B1 (en) 2015-08-12 2016-10-18 GlobalFoundries, Inc. IC structure with recessed solder bump area and methods of forming same
KR20170023643A (ko) 2015-08-24 2017-03-06 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10121812B2 (en) * 2015-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked substrate structure with inter-tier interconnection
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
JP6955864B2 (ja) * 2016-12-26 2021-10-27 ラピスセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
WO2018136712A1 (en) * 2017-01-20 2018-07-26 Tokyo Electon Limited Interconnect structure and method of forming the same
KR102406573B1 (ko) * 2017-04-28 2022-06-09 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10515921B2 (en) 2017-07-27 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
US11843020B2 (en) 2017-10-30 2023-12-12 Samsung Electronics Co., Ltd. Image sensor
KR102542614B1 (ko) 2017-10-30 2023-06-15 삼성전자주식회사 이미지 센서
US11521923B2 (en) * 2018-05-24 2022-12-06 Intel Corporation Integrated circuit package supports
US10903142B2 (en) * 2018-07-31 2021-01-26 Intel Corporation Micro through-silicon via for transistor density scaling
KR102635832B1 (ko) 2018-09-28 2024-02-15 삼성전자주식회사 반도체 소자 및 그 제조방법
US10727124B2 (en) 2018-10-29 2020-07-28 International Business Machines Corporation Structure and method for forming fully-aligned trench with an up-via integration scheme
JP7353748B2 (ja) * 2018-11-29 2023-10-02 キヤノン株式会社 半導体装置の製造方法および半導体装置
US11195810B2 (en) 2019-08-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure and method of forming same
US11398408B2 (en) * 2019-09-24 2022-07-26 Advanced Semiconductor Engineering, Inc. Semiconductor substrate with trace connected to via at a level within a dielectric layer
US11094580B2 (en) * 2019-10-01 2021-08-17 International Business Machines Corporation Structure and method to fabricate fully aligned via with reduced contact resistance
US11217481B2 (en) * 2019-11-08 2022-01-04 International Business Machines Corporation Fully aligned top vias
US11295978B2 (en) * 2020-04-29 2022-04-05 International Business Machines Corporation Interconnects having spacers for improved top via critical dimension and overlay tolerance
KR20210133524A (ko) 2020-04-29 2021-11-08 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지
KR20220129924A (ko) * 2021-03-17 2022-09-26 삼성전자주식회사 인터포저, 이의 제조 방법, 및 이를 가지는 반도체 패키지
CN113078119B (zh) * 2021-03-26 2022-03-18 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
KR20220167423A (ko) 2021-06-11 2022-12-21 삼성전자주식회사 관통 전극들을 포함하는 반도체 소자
KR20240019456A (ko) * 2022-08-04 2024-02-14 삼성전자주식회사 반도체 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020182855A1 (en) * 2001-06-01 2002-12-05 Agarwala Birendra N. Dual damascene multi-level metallization
TW531892B (en) * 2000-04-05 2003-05-11 Hitachi Ltd Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device
TW200737551A (en) * 2005-12-27 2007-10-01 Shinko Electric Ind Co Semiconductor device and method for manufacturing the same
US20080136023A1 (en) * 2006-12-06 2008-06-12 Sony Corporation Method for manufacturing semiconductor device and semiconductor device
US20090152602A1 (en) * 2007-12-17 2009-06-18 Kazutaka Akiyama Semiconductor device and method for manufacturing the same

Family Cites Families (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2034900B (en) * 1978-11-17 1982-10-20 Marconi Instruments Ltd Spectrum analyser
US4872750A (en) * 1982-07-14 1989-10-10 Nec Home Electronics Ltd. Image projection apparatus
US4799050A (en) * 1986-10-23 1989-01-17 Litton Systems Canada Limited Full color liquid crystal display
JP2554724B2 (ja) * 1987-12-11 1996-11-13 株式会社リコー レーザーダイオードアレイを用いる光走査光学系
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US5646067A (en) 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
EP1798592A3 (en) * 1996-01-17 2007-09-19 Nippon Telegraph And Telephone Corporation Optical device and three-dimensional display device
KR100377033B1 (ko) 1996-10-29 2003-03-26 트러시 테크날러지스 엘엘시 Ｉｃ 및 그 제조방법
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
JPH10163315A (ja) * 1996-11-28 1998-06-19 Nec Ic Microcomput Syst Ltd 半導体回路装置
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3600470B2 (ja) * 1998-06-22 2004-12-15 パイオニア株式会社 プラズマディスプレイパネル
KR100281897B1 (ko) 1998-07-21 2001-03-02 윤종용 도전층을 갖는 반도체 장치의 제조방법
US6706189B2 (en) 1998-10-09 2004-03-16 Zenon Environmental Inc. Cyclic aeration system for submerged membrane modules
EP1074875A4 (en) * 1998-10-28 2006-07-26 Dainippon Printing Co Ltd LIQUID CRYSTAL DISPLAY
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
JP3998373B2 (ja) 1999-07-01 2007-10-24 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6785028B1 (en) * 1999-11-24 2004-08-31 Ricoh Company, Ltd. Optical scanning device having a temperature compensation unit
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6417087B1 (en) * 1999-12-16 2002-07-09 Agere Systems Guardian Corp. Process for forming a dual damascene bond pad structure over active circuitry
US6292285B1 (en) * 1999-12-20 2001-09-18 Xerox Corporation Single rotating polygon mirror with v-shaped facets for a multiple beam ROS
JP3626058B2 (ja) 2000-01-25 2005-03-02 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US7053465B2 (en) 2000-11-28 2006-05-30 Texas Instruments Incorporated Semiconductor varactor with reduced parasitic resistance
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6498381B2 (en) 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US6696360B2 (en) * 2001-03-15 2004-02-24 Micron Technology, Inc. Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
JP2002296714A (ja) * 2001-03-30 2002-10-09 Fuji Photo Film Co Ltd 放射線画像情報読取方法
KR100404479B1 (ko) * 2001-06-21 2003-11-05 주식회사 하이닉스반도체 듀얼 다마신 배선 형성방법
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
WO2003063242A1 (en) 2002-01-16 2003-07-31 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
CN1215551C (zh) * 2002-04-12 2005-08-17 台湾积体电路制造股份有限公司 阻绝气体释放及凸出结构产生的双镶嵌方法
JP2003318178A (ja) 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
JP3774715B2 (ja) * 2002-10-21 2006-05-17 キヤノン株式会社 投射型表示装置
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US7354798B2 (en) * 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
JP4072677B2 (ja) 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP2004297019A (ja) 2003-03-28 2004-10-21 Seiko Epson Corp 半導体装置、回路基板及び電子機器
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
JP4248928B2 (ja) 2003-05-13 2009-04-02 ローム株式会社 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US6897125B2 (en) 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
TWI251313B (en) * 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US6878616B1 (en) * 2003-11-21 2005-04-12 International Business Machines Corporation Low-k dielectric material system for IC application
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP4339152B2 (ja) * 2004-03-08 2009-10-07 富士通マイクロエレクトロニクス株式会社 配線構造の形成方法
JP4074862B2 (ja) 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
JP4327644B2 (ja) * 2004-03-31 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP4439976B2 (ja) * 2004-03-31 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
CN101048868B (zh) 2004-08-20 2010-06-09 佐伊科比株式会社 具有三维层叠结构的半导体器件的制造方法
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
KR20060054689A (ko) 2004-11-16 2006-05-23 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
KR101052366B1 (ko) 2004-11-16 2011-07-28 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
KR20060054690A (ko) 2004-11-16 2006-05-23 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
JP2006339584A (ja) * 2005-06-06 2006-12-14 Sharp Corp 半導体装置およびその製造方法
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7429529B2 (en) 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7772116B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20070081239A1 (en) * 2005-10-06 2007-04-12 May Gregory J Optical characteristics of a screen
US7609442B2 (en) * 2005-10-13 2009-10-27 Hewlett-Packard Development Company, L.P. Synchronizing screen
TW200733270A (en) * 2005-10-19 2007-09-01 Koninkl Philips Electronics Nv Redistribution layer for wafer-level chip scale package and method therefor
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7514775B2 (en) 2006-10-09 2009-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
US7544605B2 (en) 2006-11-21 2009-06-09 Freescale Semiconductor, Inc. Method of making a contact on a backside of a die
US8247322B2 (en) * 2007-03-01 2012-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Via/contact and damascene structures and manufacturing methods thereof
US7697183B2 (en) * 2007-04-06 2010-04-13 Prysm, Inc. Post-objective scanning beam systems
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
KR20080101635A (ko) 2007-05-18 2008-11-21 삼성전자주식회사 반도체 패키지, 그 제조 방법, 및 반도체 패키지를 이용한패키지 모듈 및 전자 제품
JP4937842B2 (ja) 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20090057909A1 (en) 2007-06-20 2009-03-05 Flipchip International, Llc Under bump metallization structure having a seed layer for electroless nickel deposition
TW200910557A (en) 2007-06-20 2009-03-01 Flipchip Int Llc Under bump metallization structure having a seed layer for electroless nickel deposition
TWI351751B (en) 2007-06-22 2011-11-01 Ind Tech Res Inst Self-aligned wafer or chip structure, self-aligned
US8556430B2 (en) * 2007-06-27 2013-10-15 Prysm, Inc. Servo feedback control based on designated scanning servo beam in scanning beam display systems with light-emitting screens
US8193092B2 (en) 2007-07-31 2012-06-05 Micron Technology, Inc. Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices
KR101387701B1 (ko) * 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
JP2009055004A (ja) * 2007-08-24 2009-03-12 Honda Motor Co Ltd 貫通配線構造
US20090102052A1 (en) * 2007-10-22 2009-04-23 Sang Wook Ryu Semiconductor Device and Fabricating Method Thereof
JP5358089B2 (ja) 2007-12-21 2013-12-04 スパンション エルエルシー 半導体装置
US7804119B2 (en) 2008-04-08 2010-09-28 International Business Machines Corporation Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP5324822B2 (ja) * 2008-05-26 2013-10-23 ラピスセミコンダクタ株式会社 半導体装置
US7939449B2 (en) * 2008-06-03 2011-05-10 Micron Technology, Inc. Methods of forming hybrid conductive vias including small dimension active surface ends and larger dimension back side ends
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US20100013060A1 (en) 2008-06-22 2010-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench
US7800238B2 (en) * 2008-06-27 2010-09-21 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods
US7869112B2 (en) * 2008-07-25 2011-01-11 Prysm, Inc. Beam scanning based on two-dimensional polygon scanner for display and other applications
US8384224B2 (en) 2008-08-08 2013-02-26 International Business Machines Corporation Through wafer vias and method of making same
KR20100021856A (ko) 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
US7855455B2 (en) * 2008-09-26 2010-12-21 International Business Machines Corporation Lock and key through-via method for wafer level 3 D integration and structures produced
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US7956442B2 (en) 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
KR20100045857A (ko) * 2008-10-24 2010-05-04 삼성전자주식회사 반도체 칩, 스택 모듈, 메모리 카드 및 반도체 칩의 제조 방법
US7935571B2 (en) * 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US8017515B2 (en) 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8736050B2 (en) * 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US7999320B2 (en) 2008-12-23 2011-08-16 International Business Machines Corporation SOI radio frequency switch with enhanced signal fidelity and electrical isolation
US8264077B2 (en) * 2008-12-29 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
US8097964B2 (en) * 2008-12-29 2012-01-17 Texas Instruments Incorporated IC having TSV arrays with reduced TSV induced stress
US7910473B2 (en) 2008-12-31 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with air gap
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8399354B2 (en) 2009-01-13 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with low-K dielectric liner
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8531015B2 (en) * 2009-03-26 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a thin wafer without a carrier
US8158489B2 (en) * 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8294261B2 (en) * 2010-01-29 2012-10-23 Texas Instruments Incorporated Protruding TSV tips for enhanced heat dissipation for IC devices
JP5019303B2 (ja) * 2010-03-03 2012-09-05 Ｓｍｃ株式会社 電磁弁駆動回路、電磁弁及び電磁弁の駆動方法
US8587121B2 (en) * 2010-03-24 2013-11-19 International Business Machines Corporation Backside dummy plugs for 3D integration
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8174124B2 (en) * 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW531892B (en) * 2000-04-05 2003-05-11 Hitachi Ltd Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device
US20020182855A1 (en) * 2001-06-01 2002-12-05 Agarwala Birendra N. Dual damascene multi-level metallization
TW200737551A (en) * 2005-12-27 2007-10-01 Shinko Electric Ind Co Semiconductor device and method for manufacturing the same
US20080136023A1 (en) * 2006-12-06 2008-06-12 Sony Corporation Method for manufacturing semiconductor device and semiconductor device
US20090152602A1 (en) * 2007-12-17 2009-06-18 Kazutaka Akiyama Semiconductor device and method for manufacturing the same

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US9716074B2 (en) 2017-07-25
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US8791549B2 (en) 2014-07-29
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US20170005069A1 (en) 2017-01-05
US9449875B2 (en) 2016-09-20

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