CN101079372A - 基板处理方法和半导体装置的制造方法 - Google Patents

基板处理方法和半导体装置的制造方法 Download PDF

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CN101079372A
CN101079372A CNA2007101045067A CN200710104506A CN101079372A CN 101079372 A CN101079372 A CN 101079372A CN A2007101045067 A CNA2007101045067 A CN A2007101045067A CN 200710104506 A CN200710104506 A CN 200710104506A CN 101079372 A CN101079372 A CN 101079372A
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substrate
semiconductor chip
supporting substrate
chip
semiconductor
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CN100580869C (zh
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波多野正喜
浅见博
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Sony Corp
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Sony Corp
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Abstract

本发明提供一种基板处理方法和半导体装置的制备方法。该基板处理方法包括步骤：将被处理基板的一侧表面接合到支撑基板；在被处理基板被支撑基板支撑的状态下处理被处理基板；以及从被处理基板除去支撑基板。将被处理基板接合到支撑基板的步骤包括熔化形成在被处理基板上以接合被处理基板到支撑基板的接合凸点，以及从被处理基板除去支撑基板的步骤包括抛光支撑基板以除去支撑基板。

Description

基板处理方法和半导体装置的制造方法
本发明包含与在2006年5月25日向日本专利局提交的日本专利申请JP2006-144893有关的主题，其全文在此作参照引用。
技术领域
本发明涉及一种例如半导体基板的被处理基板在其被支撑基板支撑的状态下被处理的基板处理方法，和一种利用所述基板处理方法制造半导体装置的方法。
背景技术
近年来，伴随着要求提高电子装置的性能和减小电子装置的厚度和尺寸，电子部件的集成密度和安装密度日益提高，并且采用倒装芯片安装的MCM(多芯片模块)或SIP(系统封装)型半导体装置已经成为主流。这类半导体装置包括基于其中采用第二半导体芯片在第一半导体芯片上的倒装芯片安装的构造的那些装置。
图3是剖面视图，示出了过去这类半导体装置的一般构成。示出的半导体装置包括第一半导体芯片1和第二半导体芯片2。通过使用了多个凸点3的倒装芯片安装，第二半导体芯片2安装在第一半导体芯片1的主表面的基本中央区。在第一半导体芯片1的周边，按照围绕其中安装第二半导体芯片2的区域的方式，形成了多个电极衬垫4。另外，在第一半导体芯片1的主表面上，在芯片安装区和电极衬垫4的形成区之间提供坝5。在电极衬垫4的形成区的内侧，按照环绕芯片安装区的方式，坝5形成为平面视图上的矩形框状形状。此外，第一半导体芯片1与第二半导体芯片2之间的间隙被底填充材料6填充。
如上构造的现有技术的半导体装置经由粘结材料层8粘结到安装基板7上，如图3所示，然后经由焊接线10进行第一半导体芯片1上的电极衬垫4与安装基板7上的连接盘9之间的电连接。
近年来，关于MCM或SIP型的这些半导体装置，需要更高的信号处理速度、更小的安装面积等。尤其是，图3所示通过引线键合系统安装的半导体装置存在由于焊接线10的布线长度而导致的信号传输延迟的问题，以及存在确保围绕焊接线10布置所需安装面积的问题。
鉴于此，可采用一种构成，其中如图4的示意性图示，第一半导体芯片1提供有通路(贯通电极)11，以建立接合到上层侧的第二半导体芯片2的凸点3与接合到下层侧的安装基板7的凸点12之间的层间连接。这种构成非常有利，因为由此可以同时实现更高的信号处理速度和更小的安装面积。
至于形成所述通路，为了实现更短的加工时间和减小的间距，可能需要减小晶片的厚度。关于减薄晶片，已经实施了背面研磨。于是，作为形成通路的方法，公知的一种方法是：从晶片的表面侧埋入形成通路，然后研磨晶片的背面侧使通路的端面露出到外部(见日本专利公开第2004-241479号)。
同时，由于晶片的厚度减小，晶片变得更容易弯曲，且变得更难操作晶片。考虑到此，可能需要粘结支撑基板到晶片的表面侧，从而增强晶片的支撑性，并且在完成被处理基板的处理后，从被处理基板适当地除去支撑基板。
如上所述，用于支撑基板和晶片之间的粘结的粘接剂需要具有耐受晶片加工的良好临时固定性能和完成晶片加工后将其除去的良好剥离性。关于剥离(除去)粘结剂的技术，已经提出，例如，通过在溶剂中溶解除去粘结剂的方法，和利用紫外线照射来降低粘结剂粘性的方法(见日本专利公开第2003-171624号和日本专利公开第2005-191550号)。
图5A-5J是步骤剖面视图，示出了作为第一现有技术例子的半导体装置的制造方法。
首先，如图5A所示，制备了晶片100，其中在硅构成的基板体(半导体基板)101的表面侧上形成包括例如晶体管的半导体器件、布线103、绝缘层104等的器件层102。与部分布线层103导通的电极衬垫105形成在器件层102的表面侧上，和与部分布线层103导通的埋入导体层106P形成在基板体101的表面侧上。
接着，如图5B所示，在位于器件层102表面侧上的电极衬垫105上形成焊料凸点107。随后，如图5C所示，粘结剂被涂敷到包括焊料凸点107的器件层102的整个表面区域，以形成粘结材料层108，和将支撑基板109粘结到粘结材料层108上。支撑基板109由玻璃基板或硅基板构成，在该基板中提供了用于供应剥离液的多个通孔109a。
随后，如图5D所示，在晶片100被支撑基板109支撑的状态下，研磨基板体101的背面侧，以减薄基板体101到预定厚度和从减薄的基板体101t的背面侧露出通路(埋入导体层)106的尖端部106a。顺便提及，尽管图中简化示出，但是实际上减薄的基板体101t形成得厚于器件层102，以及实际上支撑基板109形成得厚于基板体101t。另外，在图5D和后面的附图中，晶片101图示为上侧朝下的状态(相比其在前面视图中的姿态)。
此后，如图5E所示，绝缘膜111形成在基板体101t的背面侧上，外部连接端子112形成在通路106的尖端部106a上。接着，如图5F所示，半导体芯片113通过倒装芯片安装被安装在外部连接端子113上；然后，如图5G所示，底填充层114形成在半导体芯片113的安装区中。
接下来，如图5H所示，从粘结材料层108释放(剥离)支撑基板109。经由形成在支撑基板109内部中的多个通孔109a供应剥离液(如酒精)来溶解粘结材料层108，从而释放(剥离)支撑基板109。接着，如图5I所示，粘结材料层108被溶解除去，此后以芯片为单位划片晶片100，从而制造出图5J所示具有通路(贯通电极)106的芯片上芯片(chip-on-chip)结构的半导体装置100A。
接下来，图6A-6I是步骤剖面视图，示出了作为第二现有技术例子的半导体装置的制造方法。顺便提及，在图中，与上述第一现有技术例子对应的部分以上面所用的同样标记表示，将省略这些部分的详细说明。
在现有技术的这个例子中，在晶片100的表面侧上形成焊料凸点107及此后粘结支撑基板的步骤与第一现有技术例子中的那些步骤相同(图6A至6C)。应注意这个例子不同于第一现有技术例子，其中支撑基板119经由其粘性因紫外线照射而劣化的粘结剂所形成的粘结材料层118粘结到晶片100的表面层。支撑基板119由透过紫外线的玻璃基板构成。
接着，类似于第一现有技术例子，进行减薄基板体101(图6D)、形成外部连接端子112(图6E)、安装半导体芯片113(图6F)和形成底填充层114(图6G)的步骤。此后，进行经由支撑基板119利用紫外线照射粘结材料层118从而从晶片100释放(剥离)支撑基板119的步骤(图6H)。接着，以芯片为单位划片晶片100，从而制造出如图6I所示具有通路(贯通电极)106的芯片上芯片结构的半导体装置100A。
发明内容
如上所述，用于晶片100与支撑基板109、119之间粘结的粘结材料108、118需要具有耐受晶片加工的良好临时固定性能和完成晶片加工后将其除去的良好剥离性能。上述现有技术的例子中，因此，可溶于有机溶剂中的粘结剂或者其粘结力可通过紫外线照射降低的粘结剂已经用于形成粘结材料层108、118。
然而，这些粘结剂通常耐热性低，当它们被加热到高于其耐热温度时，会产生粘性降低或者其剥离性能。这引起晶片加工期间不实施高于粘结材料层108、118的耐热温度的高温处理的问题。
例如，在例如SiO2膜的绝缘膜的情况下，由于膜形成温度较高，膜质量更优和膜对硅基板的粘附性更好。然而，由于如上所述不对通过粘结剂被支撑在支撑基板上的基板实施这种高温处理，从而需要采用低温膜形成工艺，例如低温CVD工艺。结果，在形成绝缘膜111于基板体101t的背面侧上的步骤中(图5E、图6E)，难以确保绝缘膜111的可靠性。另外，在接合半导体芯片113的步骤中(图5F、图6F)，需要使用在粘结材料层108、118的耐热温度以下可熔融的低温焊料，造成材料选择的限制。
此外，上述粘结材料层108、118不仅耐热性低，而且化学稳定性低；因此，存在用于处理它们而不造成其损伤(例如溶解和变质劣化)的化学制品或方法受限的问题。尤其是，粘结材料层108对抗含有例如PGMEA(Propylene Glycol Monomethyl Ether Acetate，丙二醇一甲基醚醋酸盐)、ECA(Ethyl Cellosolve Acetate，乙基乙酸溶纤剂)等的溶剂的剥离液的耐性低。因此，存在如下问题，在构图绝缘膜111的步骤中或者在形成外部连接端子112的步骤中(图5E)，图案抗蚀剂的处理方法会受限(例如，不进行浸渍)。
于是，需要一种基板处理方法和半导体装置的制造方法，通过该方法可适当地支撑基板，不使用需要具有良好临时固定性能和良好剥离性能(可除去性)的粘结材料层，且通过该方法可适当地除去支撑基板。
按照本发明的一个实施例，一种基板处理方法包括以下步骤：将被处理基板的一侧表面接合到支撑基板；在被处理基板被支撑基板支撑的状态下处理被处理基板；以及从被处理基板除去支撑基板。将被处理基板接合到支撑基板的步骤包括熔化形成在被处理基板上的接合凸点以接合被处理基板到支撑基板，以及从被处理基板除去支撑基板的步骤包括抛光支撑基板以除去支撑基板。
在本发明的一个实施例中，通过熔化形成在被处理基板上的接合凸点进行支撑基板与被处理基板之间的接合，和通过抛光支撑基板进行支撑基板的除去，从而可以不需要现有技术中所需的具有良好临时固定性能和良好剥离性(可去除性)的粘结剂。这就确保了被处理基板的加工可以在不受粘结剂的耐热温度或化学稳定性的约束下进行。因此，例如可以形成粘性优异的绝缘膜和可以稳定构图端子表面。
另外，利用按照本发明一个实施例的基板处理方法，可以高精度且高可靠地制造其中下层侧的半导体芯片被提供有用于层间连接的通路(贯通电极)的芯片上芯片结构的半导体装置。
按照本发明的另一实施例，一种半导体装置的制造方法包括如下步骤：制备在其表面上每个提供有用于外部连接的凸点的多个第一半导体芯片；经由凸点将多个第一半导体芯片与支撑基板接合；利用绝缘材料填充多个第一半导体芯片之间的空间以在支撑基板上形成假拟晶片；抛光假拟晶片以减小各第一半导体芯片的厚度；在各第一半导体芯片的背面上，形成电连接到凸点的外部连接端子；在外部连接端子上安装第二半导体芯片；通过抛光除去支撑基板以露出凸点；以及以芯片为单位划片假拟晶片。
通过以芯片为单位划片公共半导体晶片生产出多个第一半导体芯片。鉴于此，当从生产的单个芯片中选取的合格芯片用作被凸点接合到支撑基板上的半导体芯片时，可以设想到制造的半导体装置的产量被提高。
可以在第一半导体芯片被支撑基板支撑的状态下进行的减薄步骤期间或者之后进行第一半导体芯片中通路的形成。此种情况下，当利用绝缘材料填充安装在支撑基板上的多个第一半导体芯片之间的空间(间隙)以得到假拟晶片中的第一半导体芯片时，可通过抛光假拟晶片同时减薄多个第一半导体芯片，且可以通过保持被抛光表面的平坦性策划适当的抛光处理。
关于减薄第一半导体芯片的步骤期间形成通路的方法，电连接到凸点的埋入导体层在晶片级阶段被预先形成，和在减薄芯片的时候从芯片的背面露出埋入导体层的尖端部。接着，处理如此露出的端子表面，从而形成被接合到上层侧的第二半导体芯片的外部连接端子。
在第二半导体芯片被安装在第一半导体芯片上之后进行抛光除去支撑基板。此种情况下，当利用密封树脂层预先密封第二半导体芯片时，可以在抛光时稳定支撑以假拟晶片形式制备的第一和第二半导体芯片的叠层。另外，除去支撑基板时露出的接合凸点可以原样用作外部端子。
于是，按照根据本发明一个实施例的基板处理方法，可以适当进行被处理基板被支撑基板的支撑和支撑基板从被处理基板的除去，不使用必须具有良好临时固定性能和良好剥离性(可去除性)的粘结剂。
另外，按照根据本发明另一实施例的半导体装置的制造方法，可以高精度且高可靠地制造其中用于层间连接的通路(贯通电极)可被制造的芯片上芯片结构的半导体装置。
附图说明
图1A和1B是步骤剖面视图，示出了按照本发明第一实施例的半导体装置的制造方法；
图1C和1D是步骤剖面视图，示出了按照本发明第一实施例的半导体装置的制造方法；
图1E和1F是步骤剖面视图，示出了按照本发明第一实施例的半导体装置的制造方法；
图1G和1H是步骤剖面视图，示出了按照本发明第一实施例的半导体装置的制造方法；
图1I和1J是步骤剖面视图，示出了按照本发明第一实施例的半导体装置的制造方法；
图1K和1L是步骤剖面视图，示出了按照本发明第一实施例的半导体装置的制造方法；
图2A和2B是步骤剖面视图，示出了按照本发明第二实施例的半导体装置的制造方法；
图2C和2D是步骤剖面视图，示出了按照本发明第二实施例的半导体装置的制造方法；
图2E和2F是步骤剖面视图，示出了按照本发明第二实施例的半导体装置的制造方法；
图2G和2H是步骤剖面视图，示出了按照本发明第二实施例的半导体装置的制造方法；
图2I和2J是步骤剖面视图，示出了按照本发明第二实施例的半导体装置的制造方法；
图2K和2L是步骤剖面视图，示出了按照本发明第二实施例的半导体装置的制造方法；
图3是剖面图，示意性示出了芯片上芯片结构的半导体装置的构成例子；
图4是剖面图，示意性示出了芯片上芯片结构的半导体装置的另一构成例子；
图5A至5D是步骤剖面视图，示出了按照第一现有技术例子的半导体装置的制造方法；
图5E至5G是步骤剖面视图，示出了按照第一现有技术例子的半导体装置的制造方法；
图5H至5J是步骤剖面视图，示出了按照第一现有技术例子的半导体装置的制造方法；
图6A至6D是步骤剖面视图，示出了按照第二现有技术例子的半导体装置的制造方法；
图6E至6G是步骤剖面视图，示出了按照第二现有技术例子的半导体装置的制造方法；以及
图6H和6I是步骤剖面视图，示出了按照第二现有技术例子的半导体装置的制造方法。
具体实施方式
现在，下面参考附图说明本发明的一些实施例。在下面每一实施例中，说明本发明应用于芯片上芯片结构的半导体装置的制造的例子。
<第一实施例>
图1A至1L是步骤剖面视图，示出了按照本发明第一实施例的芯片上芯片结构的半导体装置的制造方法。
首先如图1A所示，准备晶片W1，其中包括例如晶体管的半导体器件、布线23、绝缘层24等的器件层22形成在硅构成的基板体(半导体基板)21的表面侧上。晶片W1相应于本发明实施例中的“被处理基板”。
电连接到部分布线23的多个电极衬垫25被设置在器件层22的表面侧上，凸点27形成在电极衬垫25上。凸点27可以由例如焊料凸点构成，并用作接合到下面将描述的支撑基板29的本发明实施例中的“接合凸点”。
在器件层22内初始提供了由例如铜形成的埋入导体层26P。埋入导体层26P形成为具有预定深度(例如200μm或以下)从而不穿透基板体21，并经由部分布线23电连接到电极衬垫25(并因此到达凸点27)。顺便提及，埋入导体层26P的周围被例如SiO2形成的绝缘膜覆盖，从而与基板体21电绝缘。
接着，如图1B所示，以芯片为单位划片晶片W1，以产生图中所示的多个半导体芯片20A。半导体芯片20A对应本发明实施例中的“第一半导体芯片”。
接下来，如图1C所示，如上产生的多个半导体芯片20A经由凸点27接合到支撑基板29上。支撑基板29被初始提供了与半导体芯片20A上凸点27的阵列间距对应的虚设端子28，凸点27与虚设端子28熔合，从而半导体芯片20A背面朝上地一体固定到支撑基板29上。通过与一般倒装芯片结合相同的技术进行半导体芯片20A与支撑基板29的接合，从而可利用现有安装设备进行该步骤。
支撑基板29由具有可与基板体21的热膨胀系数相当的热膨胀系数的材料形成，即，由玻璃基板、硅基板等构成。支撑基板29的厚度没有具体限制。但是优选地，支撑基板29的厚度形成为确保减薄假拟晶片时足以操作其的刚性的程度，如后所述，用绝缘材料填充半导体芯片20A之间的空间(间隙)来得到假拟晶片。例如，该厚度不小于700μm。
接着，如图1D所示，倒装芯片结合后各半导体芯片20A与支撑基板29之间的间隙用底填充树脂填充，以形成底填充层30。作为底填充树脂，可以使用热塑性树脂，例如环氧树脂，其用于一般的倒装芯片结合。
接下来，如图1E所示，在接合到支撑基板29上的半导体芯片20A之间的空间(间隙)利用绝缘材料31填充，以形成上侧平坦化的假拟晶片Wp。例如，利用用于生产晶片级CSP(芯片尺寸封装)的晶片成型技术形成假拟晶片Wp。作为绝缘材料31，使用用于晶片级CSP等的晶片成型树脂。
由于如上所述组装到假拟晶片中的半导体芯片20A可以在后续加工中在晶片状态下被操作，因此可以不做变动地使用现有的加工设备。另外，当预先通过电气测量选择的合格芯片用作被接合到支撑基板29的半导体芯片20A和它们通过晶片成型技术组装到假拟晶片中时，假拟晶片作为其中布置了合格芯片的晶片可进行后续加工。这可能提高生产率和增加产量。
接着，如图1F所示，形成于支撑基板29上的假拟晶片Wp被抛光，以减薄各半导体芯片20A的基板体21，并且以便从减薄的基板体21t的背面露出通路26(埋入导体层26P)的尖端部26a。
此步骤中，例如，基板体21与绝缘材料31一起被抛光，直到通路26的尖端部26a从基板体21的背面(抛光表面)露出，此后对基板体21t的背面实施化学刻蚀以突出通路26的尖端部26a。另外，其中安装的半导体芯片20A之间的空间(间隙)被绝缘材料31填充的结构确保了抛光表面可保持平坦，并且多个半导体芯片20A的减薄可同时、适当且稳定地进行。顺便提及，作为抛光方法，任何公知抛光技术例如背面研磨(BGR)和化学机械抛光(CMP)可单独或者接合使用。
随后，如图1G所示，对各半导体芯片20A的背面实施预定绝缘处理，例如形成绝缘膜32，并且在通路26的尖端部26a上形成外部连接端子33。外部连接端子33经由通路26、布线23和电极衬垫25电连接到凸点27。可利用用于晶片级CSP的再布线技术或者半导体工艺中的布线技术进行外部连接端子33的形成。
接下来，如图1H所示，第二半导体芯片20B安装在(第一)半导体芯片20A上的外部连接端子33上。多个凸点36预先形成在各半导体芯片20B的安装表面上，和半导体芯片20B通过倒装芯片结合经由凸点36接合到外部连接端子33上。
此后，如图1I所示，底填充层34形成在彼此接合的第一半导体芯片20A和第二半导体芯片20B之间。作为构成底填充层34的树脂材料，例如可使用上文参照图1D说明的底填充层30的相同材料。
接着，如图1J所示，密封层35形成在假拟晶片Wp上，以利用构成密封层35的树脂填满被安装的第二半导体芯片20B之间的空间(间隙)，从而使假拟晶片Wp的上表面平坦。例如可通过晶片级CSP中使用的晶片成型技术形成密封层35。作为构成密封层35的树脂，例如可使用晶片级CSP所用成型树脂。另外，通过如此形成的密封层35，则可以支撑基板29上的假拟晶片的形式，得到具有第一和第二半导体芯片20A和20B的叠层结构的半导体装置。顺便提及，如果需要，密封层35可被抛光以减薄第二半导体芯片20B。
随后，如图1K所示，从假拟晶片Wp除去支撑基板29。通过利用BGR或CMP抛光支撑基板29来进行支撑基板29的去除。去除支撑基板29的步骤进行直到第一半导体芯片20A的凸点27从假拟晶片Wp的下表面露出。这种情况下，由于密封层35的存在使得假拟晶片Wp的上表面平坦化，所以可通过抛光设备中的支撑夹具稳定且适当地支撑假拟晶片Wp，从而可能适当地抛光处理支撑基板29。
凸点27后来可用作安装基板(未示出)的连接端子。此外，由于各凸点27的周围被底填充层30支撑，则可适当进行在抛光除去支撑基板29期间露出凸点27的步骤。
最后，如图1L所示，除去了支撑基板29的假拟晶片Wp以芯片为单位划片，以生产具有第一和第二半导体芯片20A和20B三维叠层结构的半导体装置20。
半导体装置20中，通过形成在第一半导体芯片20A中的通路26，实现了第二半导体芯片20B与第一半导体芯片20A之间的电连接和第二半导体芯片20B与凸点27之间的电连接。此外，半导体装置20中，用于保护第一和第二半导体芯片20A和20B的装甲封装(armor package)由覆盖第一半导体芯片20A的周围的绝缘材料31和覆盖第二半导体芯片20B的周围的密封层35两者组成。
如上所述，按照本实施例，通过熔化(熔融接合)形成在半导体芯片20A上的接合凸点27来进行半导体芯片20A与支撑基板29的接合，并且通过抛光支撑基板29来进行支撑基板29的除去。因此，可以不需要现有技术中必须的具有良好临时固定性能和良好剥离性(可除去性)的粘结剂。结果，进行半导体芯片20A的加工可不受粘结剂的耐热温度或化学稳定性的限制，这使得能够形成例如粘性优异的绝缘膜和外部连接端子33的稳定构图(图1G)。这就确保了可以高精度和高可靠地制造芯片上芯片结构的半导体装置20，在该芯片结构中用于层间连接的通路26形成在下层侧的半导体芯片20A中。
此外，按照此实施例，通过以芯片为单位划片公共半导体晶片W1生产第一半导体芯片20A，和从生产出的单个芯片中选取的合格芯片可用作被凸点接合到支撑基板29上的半导体芯片20A。因此，制造半导体装置20时可以提高产量。
<第二实施例>
现在，下文说明本发明的第二实施例。
图2A至2L是步骤剖面视图，示出了按照本发明第二实施例的芯片上芯片结构的半导体装置的制造方法。顺便提及，图中，与以上第一实施例对应的部分采用上文使用的相同标记表示，且省略这些部分的详细说明。
首先，如图2A所示，准备晶片W2，其中包括例如晶体管的半导体器件、布线23、绝缘层24等的器件层22形成在硅构成的基板体(半导体基板)21的表面侧上。电连接到部分布线23的多个电极衬垫25被设置在器件层22的表面侧上，凸点27形成在电极衬垫25上。接着，以芯片为单位划片晶片W2，以产生第一半导体芯片20C。
这里，此实施例中的晶片W2不同于上面第一实施例中的晶片W1，其中用于形成通路(贯通电极)的埋入导体层没有形成在基板的内部，和在下面描述的减薄半导体芯片20C的步骤之后单独形成通路(贯通电极)26(图2G)。
接下来，如图2C所示，如此产生的多个半导体芯片20C经由凸点27接合到支撑基板29上。支撑基板29被初始提供了与半导体芯片20C上凸点27的阵列间距对应的虚设端子28，凸点27与虚设端子28熔合(熔融接合)，从而半导体芯片20C背面朝上地一体固定到支撑基板29上。
接着，如图2D所示，被倒装芯片结合的各半导体芯片20C与支撑基板29之间的间隙用底填充树脂填充，以形成底填充层30。接下来，如图2E所示，接合到支撑基板29上的被安装半导体芯片20C之间的空间利用绝缘材料31填充，以形成上侧被平坦化(平面)的假拟晶片Wp。
对于如此得到的假拟晶片中的半导体芯片20C，它们可以在后续加工中在晶片状态下被操作，从而可以不做变动地使用现有的加工设备。另外，当预先通过电气测量选择的合格芯片用作被接合到支撑基板29的半导体芯片20C和通过晶片成型技术得到假拟晶片时，假拟晶片可作为其中布置了合格芯片的晶片进行后续加工。这可能提高生产率和增加产量。
接着，如图2F所示，形成于支撑基板29上的假拟晶片Wp被抛光，以减薄各半导体芯片20C的基板体21。随后，如图2G所示，从基板体21t的背面形成穿过减薄的基板体21t且在其端部连接到预定布线23的通路(贯通电极)26。可通过一种方法形成通路26，其中通过干法工艺例如等离子体刻蚀形成层间接触孔，此后进行孔的内壁表面的绝缘和铜等导体镀敷的形成。进一步，对半导体芯片20C的背面实施预定绝缘处理，例如形成绝缘膜32，并且在通路26的尖端部上形成外部连接端子33。外部连接端子33经由通路26、布线23和电极衬垫25电连接到凸点27。
接下来，如图2H所示，第二半导体芯片20B安装在(第一)半导体芯片20C上的外部连接端子33上。多个凸点36预先形成在各半导体芯片20B的安装表面上，半导体芯片20B通过倒装芯片结合经由凸点36接合到外部连接端子33上。此后，如图2I所示，底填充层34形成在彼此接合的第一半导体芯片20C和第二半导体芯片20B之间。
接着，如图2J所示，密封层35形成在假拟晶片Wp上，并且利用构成密封层35的树脂填充被安装的第二半导体芯片20B之间的空间(间隙)，从而使假拟晶片Wp的上表面平坦。通过如此形成的密封层35，则可以在支撑基板29上假拟晶片的形式，组装第一和第二半导体芯片20C和20B的叠层结构的半导体装置。顺便提及，如果需要，密封层35可被抛光以减薄第二半导体芯片20B。
随后，如图2K所示，从假拟晶片Wp除去支撑基板29。通过利用BGR或CMP技术抛光支撑基板29来进行支撑基板29的去除。去除支撑基板29的步骤进行直到第一半导体芯片20C的凸点27从假拟晶片Wp的下表面露出。这种情况下，由于密封层35的存在使得假拟晶片Wp的上表面平坦化，所以可通过抛光设备中的支撑夹具稳定且适当地支撑假拟晶片Wp，从而可能适当抛光支撑基板29。
凸点27后来可用作安装基板(未示出)的连接端子。此外，由于各凸点27的周围被底填充层30支撑，则可适当进行在除去支撑基板29期间露出凸点27的步骤。
最后，如图2L所示，除去了支撑基板29的假拟晶片Wp以芯片为单位划片，以生产第一和第二半导体芯片20C和20B三维叠层结构的半导体装置。半导体装置20中，通过形成在第一半导体芯片20C中的通路26，实现了第二半导体芯片20B与第一半导体芯片20C之间的电连接和第二半导体芯片20B与凸点27之间的电连接。此外，半导体装置20中，用于保护第一和第二半导体芯片20C和20B的装甲封装由覆盖第一半导体芯片20C的周围的绝缘材料31和覆盖第二半导体芯片20B的周围的密封层35两者组成。
通过按照本实施例的半导体装置20的制造方法，同样可获得以上第一实施例的相同效果。
尽管上面说明了本发明的实施例，但是发明自然不局限于实施例，基于发明技术构思的各种变形是可能的。
例如，尽管以上实施例说明了本发明应用于芯片上芯片结构的半导体装置20的制造的例子，发明不限于所述例子。发明也可应用于通过背面研磨减薄晶片级的被处理基板的步骤、将器件安装在被处理基板上的步骤及类似步骤。
此外，尽管以上实施例作为例子已经说明了第一和第二半导体芯片被堆叠的半导体装置的制造，堆叠的半导体芯片的数量可进一步增加。那种情况下，针对下层侧的半导体芯片形成的用于层间连接的通路(贯通电极)可以按照以上实施例相同的方式形成。
本领域技术人员应当理解，取决于设计要求和其他因素，可以出现各种变形、结合、子结合和改变，只要它们落入权利要求书或其等同特征的范围内。

Claims (7)

1.一种基板处理方法，包括步骤：
将被处理基板的一侧表面接合到支撑基板；
在所述被处理基板被所述支撑基板支撑的状态下处理所述被处理基板；以及
从所述被处理基板除去所述支撑基板，
其中将所述被处理基板接合到所述支撑基板的所述步骤包括熔化形成在所述被处理基板上的接合凸点以接合所述被处理基板到所述支撑基板；及
从所述被处理基板除去所述支撑基板的所述步骤包括抛光所述支撑基板以除去所述支撑基板。
2.如权利要求1所述的基板处理方法，
其中处理所述被处理基板的所述步骤包括抛光所述被处理基板的另一侧表面以减小所述被处理基板的厚度。
3.如权利要求1所述的基板处理方法，
其中处理所述被处理基板的所述步骤包括在所述被处理基板的另一侧表面上安装器件。
4.一种半导体装置的制造方法，包括步骤：
制备在其表面上每个提供有用于外部连接的凸点的多个第一半导体芯片；
经由所述凸点将所述多个第一半导体芯片与支撑基板接合；
利用绝缘材料填充所述多个第一半导体芯片之间的空间以在所述支撑基板上形成假拟晶片；
抛光所述假拟晶片以减小各所述第一半导体芯片的厚度；
在每个所述第一半导体芯片的背面上，形成电连接到所述凸点的外部连接端子；
在所述外部连接端子上安装第二半导体芯片；
通过抛光除去所述支撑基板以露出所述凸点；以及
以芯片为单位划片所述假拟晶片。
5.如权利要求4所述的半导体装置的制造方法，
其中在所述第一半导体芯片与所述支撑基板的所述接合之后，在所述支撑基板与所述第一半导体芯片之间形成底填充层。
6.如权利要求4所述的半导体装置的制造方法，
其中每个所述第一半导体芯片的内部被预先提供电连接到所述凸点的埋入导体层，并且在各所述第一半导体芯片的厚度的所述减小的同时，所述埋入导体层的尖端部从所述第一半导体芯片的背面侧露出以形成所述外部连接端子。
7.如权利要求4所述的半导体装置的制造方法，还包括步骤：
在所述第二半导体芯片的所述安装后，形成用于密封所述第二半导体芯片的密封树脂层。
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024713A (zh) * 2009-09-14 2011-04-20 台湾积体电路制造股份有限公司 半导体封装体工艺
CN102254858A (zh) * 2010-05-17 2011-11-23 St微电子(格勒诺布尔2)有限公司 用于制造半导体器件的方法和包括具有通孔的芯片的半导体器件
CN102263039A (zh) * 2010-05-24 2011-11-30 日月光半导体制造股份有限公司 晶粒总成的制造方法
CN102623403A (zh) * 2012-04-11 2012-08-01 日月光半导体制造股份有限公司 半导体元件及其制造方法
CN103063886A (zh) * 2011-10-21 2013-04-24 台湾积体电路制造股份有限公司 用于探测集成电路的探针卡
CN103904047A (zh) * 2012-12-24 2014-07-02 佳邦科技股份有限公司 多功能半导体封装结构及其制作方法
CN104364898A (zh) * 2012-05-30 2015-02-18 奥林巴斯株式会社 摄像装置的制造方法以及半导体装置的制造方法
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US9952279B2 (en) 2012-12-21 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for three dimensional integrated circuit testing
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Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10221857A1 (de) * 2002-05-16 2003-11-27 Osram Opto Semiconductors Gmbh Verfahren zum Befestigen eines Halbleiterchips in einem Kunststoffgehäusekörper, optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung
JP2009010178A (ja) * 2007-06-28 2009-01-15 Disco Abrasive Syst Ltd ウェーハの加工方法
DE102007031490B4 (de) * 2007-07-06 2017-11-16 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleitermoduls
JP5656341B2 (ja) * 2007-10-29 2015-01-21 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置およびその製造方法
US8441133B2 (en) 2009-03-31 2013-05-14 Ibiden Co., Ltd. Semiconductor device
US20100327465A1 (en) * 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure
US8503186B2 (en) * 2009-07-30 2013-08-06 Megica Corporation System-in packages
US8441123B1 (en) * 2009-08-13 2013-05-14 Amkor Technology, Inc. Semiconductor device with metal dam and fabricating method
JP5635247B2 (ja) * 2009-08-20 2014-12-03 富士通株式会社 マルチチップモジュール
US8242543B2 (en) * 2009-08-26 2012-08-14 Qualcomm Incorporated Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers
US8803332B2 (en) * 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
TWI436470B (zh) 2009-09-30 2014-05-01 Advanced Semiconductor Eng 封裝製程及封裝結構
TWI401752B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 晶片封裝結構之製造方法
US8114707B2 (en) * 2010-03-25 2012-02-14 International Business Machines Corporation Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip
US8866301B2 (en) * 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US20110300669A1 (en) * 2010-06-07 2011-12-08 Chi-Chih Shen Method for Making Die Assemblies
US8754516B2 (en) * 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
JP2012069903A (ja) * 2010-08-27 2012-04-05 Elpida Memory Inc 半導体装置及びその製造方法
WO2012108469A1 (ja) * 2011-02-08 2012-08-16 ローム株式会社 半導体装置および半導体装置の製造方法
WO2012120659A1 (ja) 2011-03-09 2012-09-13 国立大学法人東京大学 半導体装置の製造方法
US8623763B2 (en) * 2011-06-01 2014-01-07 Texas Instruments Incorporated Protective layer for protecting TSV tips during thermo-compressive bonding
KR101131782B1 (ko) 2011-07-19 2012-03-30 디지털옵틱스 코포레이션 이스트 집적 모듈용 기판
US9418876B2 (en) 2011-09-02 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of three dimensional integrated circuit assembly
US9245773B2 (en) 2011-09-02 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packaging methods and structures thereof
EP2761651B1 (en) * 2011-09-30 2019-05-29 Intel Corporation Method for handling a very thin device wafer with a solder bump using a support substrate with a planar wetting surface and a layer of thermosetting material
JP5959216B2 (ja) * 2012-02-06 2016-08-02 日東電工株式会社 基板搬送方法および基板搬送装置
KR101932495B1 (ko) * 2012-05-11 2018-12-27 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
JPWO2013179764A1 (ja) * 2012-05-30 2016-01-18 オリンパス株式会社 撮像装置の製造方法および半導体装置の製造方法
KR102001416B1 (ko) * 2012-09-24 2019-07-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
US10714378B2 (en) 2012-11-15 2020-07-14 Amkor Technology, Inc. Semiconductor device package and manufacturing method thereof
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101473093B1 (ko) * 2013-03-22 2014-12-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9184128B2 (en) 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
KR102174336B1 (ko) * 2014-07-08 2020-11-04 삼성전자주식회사 반도체 패키지 및 그 제조 방법
TWI778938B (zh) 2015-03-16 2022-10-01 美商艾馬克科技公司 半導體裝置和製造其之方法
KR101678418B1 (ko) * 2015-03-16 2016-11-23 한국생산기술연구원 3차원 레이저 스캐닝 시스템
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR20180124256A (ko) * 2017-05-11 2018-11-21 에스케이하이닉스 주식회사 몰드비아를 갖는 적층 반도체 패키지 및 그의 제조방법
KR20200143885A (ko) * 2019-06-17 2020-12-28 에스케이하이닉스 주식회사 서포팅 기판을 포함한 스택 패키지
TW202118280A (zh) * 2019-09-10 2021-05-01 日商索尼半導體解決方案公司 攝像裝置、電子機𠾖及製造方法
US11929261B2 (en) * 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
DE102020130996A1 (de) * 2020-05-01 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-package und verfahren zu dessen herstellung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437437B1 (ko) * 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
JP3186941B2 (ja) 1995-02-07 2001-07-11 シャープ株式会社 半導体チップおよびマルチチップ半導体モジュール
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device
US6821881B2 (en) * 2001-07-25 2004-11-23 Applied Materials, Inc. Method for chemical mechanical polishing of semiconductor substrates
JP2003068806A (ja) * 2001-08-29 2003-03-07 Hitachi Ltd 半導体装置及びその製造方法
US6867501B2 (en) * 2001-11-01 2005-03-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
JP2003171624A (ja) 2001-12-04 2003-06-20 Sekisui Chem Co Ltd 支持テープ
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
JP4035066B2 (ja) 2003-02-04 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2005191550A (ja) 2003-12-01 2005-07-14 Tokyo Ohka Kogyo Co Ltd 基板の貼り付け方法
US20090115042A1 (en) 2004-06-04 2009-05-07 Zycube Co., Ltd. Semiconductor device having three-dimensional stacked structure and method of fabricating the same
JP4140580B2 (ja) 2004-08-16 2008-08-27 沖電気工業株式会社 半導体装置

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN102263039A (zh) * 2010-05-24 2011-11-30 日月光半导体制造股份有限公司 晶粒总成的制造方法
CN103063886A (zh) * 2011-10-21 2013-04-24 台湾积体电路制造股份有限公司 用于探测集成电路的探针卡
CN103063886B (zh) * 2011-10-21 2017-04-12 台湾积体电路制造股份有限公司 用于探测集成电路的探针卡
CN102623403A (zh) * 2012-04-11 2012-08-01 日月光半导体制造股份有限公司 半导体元件及其制造方法
CN104380465A (zh) * 2012-05-30 2015-02-25 奥林巴斯株式会社 摄像装置的制造方法以及半导体装置的制造方法
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US9698195B2 (en) 2012-05-30 2017-07-04 Olympus Corporation Method for producing image pickup apparatus and method for producing semiconductor apparatus
CN104380465B (zh) * 2012-05-30 2018-02-09 奥林巴斯株式会社 摄像装置的制造方法以及半导体装置的制造方法
US9952279B2 (en) 2012-12-21 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for three dimensional integrated circuit testing
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