CN102024713B - 半导体封装体工艺 - Google Patents

半导体封装体工艺 Download PDF

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CN102024713B
CN102024713B CN2010102843687A CN201010284368A CN102024713B CN 102024713 B CN102024713 B CN 102024713B CN 2010102843687 A CN2010102843687 A CN 2010102843687A CN 201010284368 A CN201010284368 A CN 201010284368A CN 102024713 B CN102024713 B CN 102024713B
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wafer
thinning
packaging process
semiconductor packaging
protective layer
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CN102024713A (zh
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邱文智
吴文进
眭晓林
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体封装工艺，以粘着层在载板上贴附晶片，而在邻近晶片边缘处暴露出部分粘着层。在晶片薄化之后，提供保护层以覆盖粘着层暴露出的部分。在薄化晶片上接合数个裸片，而后以成型化合物(moldingcompound)封装薄化晶片及裸片。本发明可不露出粘着层。

Description

半导体封装体工艺
技术领域
本发明涉及半导体装置的制作，尤其涉及一种三维(3D)集成电路(ICs)的制作。
背景技术
由于各种电子元件(也即晶体管、二极管、电阻器、电容等)的积极度的持续改良，半导体工业已经历持续快速的成长。大部分而言，积极度的改良来自不断缩减最小线宽，而使既定区域中可整合更多元件。三维集成电路可以解决当装置数量增加时，装置间内连线的数量与长度的限制。形成三维集成电路的一种方法是裸片-对-晶片堆叠接合，其晶片上接合一个或多个裸片，且裸片的尺寸可小于晶片上的芯片尺寸。为了减少半导体封装体的厚度、增加芯片速率及用于高密度制造，目前正努力减少半导体晶片厚度。厚度的减少可借由晶背研磨达成，晶背研磨是施行在形成电路图案的相反面，而具有电路图案的表面通常是以粘着材料贴附至一载板用为支撑。因为薄化晶片强度不足，容易受如弯曲及/或歪曲(warp)的影响而形变，因在以切割工艺个别的芯片封装体之前，需以成型化合物(如热固环氧树脂(thermo-curing epoxyresin))封装晶片的表面。然而，在晶片边缘附近露出的粘着材料，很容易受到蚀刻攻击，在暂时性载板接合及去接合(temporary carrier bonding andde-bonding)中会造成问题。传统在粘着材料的边缘提供边缘密封层，但接下来的晶片薄化工艺将暴露出邻近晶片边缘的粘着材料的另一部分。
发明内容
为了解决现有技术的问题，本发明提供一种半导体封装工艺，包括：提供一晶片，该晶片具有相对的第一表面及第二表面；利用一粘着层将该晶片的第一表面贴附至一载板而暴露出邻近该晶片一边缘的部分该粘着层；自该第二表面薄化该晶片，以形成一薄化晶片；形成一保护层以覆盖该粘着层的该暴露部分；接合多个裸片在该薄化晶片上；以及利用一成型化合物封装该薄化晶片及所述多个裸片。如前述的半导体封装工艺，其中该晶片包括：一半导体基板，具有一正面及一背面；一穿孔，填充有一导电材料，其至少通过一部分该半导体基板；以及一集成电路，形成在该半导体基板的正面上。
一种半导体封装工艺，包括：提供一晶片，具有相对的第一表面及第二表面；利用一粘着层将该晶片的第一表面贴附至一载板而暴露出邻近该晶片一边缘的部分该粘着层；自该第二表面薄化该晶片，以形成一薄化晶片；形成一保护层以覆盖该粘着层的该暴露部分以及该晶片的该边缘；在该薄化晶片上接合一裸片；利用一成型化合物封装该薄化晶片及该裸片；以及移除该载板。如前述的半导体封装工艺，其中该晶片包括：一半导体基板，具有一正面及一背面；一穿孔，以一导电材料填入，其至少通过一部分该半导体基板；以及一集成电路，在该半导体基板的该正面上形成。
本发明可不露出粘着层。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1A～图1F为一系列剖面图，用以说明在晶片边缘形成粘着材料的保护层的一实施例。
图2A～图2C为一系列剖面图，用以说明处理包含穿孔(through vias)的晶片的方法的一实施例。
图3A～图3B为一系列剖面图，用以说明在晶片边缘形成粘着材料的保护层的另一实施例。
其中，附图标记说明如下：
10～晶片10a～晶片10的第一表面
10b～晶片10的第二表面12～载板
14～粘着层11～半导体基板
22～成型化合物40～穿孔
40a～穿孔40的一端
10”～薄化晶片11”～薄化基板
18～保护层12e～载板12的边缘
20～裸片44～导电结构
10b”～薄化晶片10”的第二表面
11b”～薄化基板的背面
10e～薄化晶片10”的边缘
14p～粘着层14的暴露部分
11a～半导体基板11的正面
11b～半导体基板11的背面
具体实施方式
在本说明书中关于“一实施例”的描述指该实施例所叙述的特定的物件、结构或特性被包含在至少一实施例中。因此，本说明书中多处的“在一实施例中”不必然为相同实施例。另外，在一或多个实施例中于适当条件下，可为特定的物件、结构或特性的组合。应注意以下附图并非依比例绘制，而仅为说明使用。
在此图1A至图1F为一系列剖面图，用以说明形成具有在晶片边缘的粘着材料的保护层的裸片-对-晶片堆叠的实施例。
图1A为借由粘着层14在载板12贴附上晶片10的一实施例的剖面图。提供具有多个半导体芯片在其上的晶片10，该晶片10包含半导体基板如硅、砷化镓、水晶晶片、石墨、玻璃、石英、陶瓷、热固材料等。晶片10具有第一表面10a及与第一表面10a相对的第二表面10b。在第一表面10a上形成包括有源及无源装置的集成电路如晶体管、电阻器、电容等，以与接合垫(bond pad)及/或其他内连线结构接触。在第一表面10a上形成粘着层14，而后将载板12接合至粘着层14上以便在后续工艺处理晶片10时可更佳容易。在此同时，载板12可替代地或额外地配置上对应的粘着表面。载板12是以可移除或可溶材料构成如玻璃、金属、陶瓷、聚合物、硅等。
在一实施例中，晶片10包括多个用于三维应用的硅通孔(through siliconvias，TSVs)。如图2A所示，晶片10包含具有正面11a及背面11b的半导体基板11，其中在正面11a上形成集成电路及内连线结构，而多个穿孔(throughvias)40至少部分穿过半导体基板11。穿孔40由正面11a延伸至背面11b且具有所需深度的金属填充插塞。穿孔40可与在内连结构上形成的接合垫电性连接。穿孔40的制作是在“第一阶内连线(first-level interconnection)”之前进行，其指在接触结构(contact structure)及晶体管上的金属间介电层(inter-metal dielectrics layer，IMD layer)中图案化的最底层金属。此外也可在制造内连线结构之后执行金属填入孔洞的工艺(metal-filled via process)。
图1B为进行晶片薄化工艺(wafer thinning process)的晶片剖面图。在接上载板12后，依半导体封装体的使用目的可在晶片10无结构(structure-free)区域(第二表面10b)中加工以得到所需的最后厚度，其可借磨光(grinding)、蚀刻及/或研磨(polishing)制得预定厚度的薄化晶片10”。在一实施例中，晶片10薄化至厚度约5μm至50μm。在另一实施例中，晶片10薄化至厚度约25μm至250μm。在提供包含穿孔40的晶片10的实施例中，经过如图2B所示的晶片薄化工艺后，穿孔40的一端40a自薄化基板11”的背面11b”露出及/或突出。
为了避免在后续蚀刻工艺中破坏薄化晶片10”的边缘10e及粘着层14的暴露部分14p，形成保护层18以至少覆盖边缘10e及暴露部分14p。保护层18也可延伸覆盖部分的载板12如载板12的边缘12e。因此在后续蚀刻工艺中可借由保护层18保护其下的粘着层14。如图1C所示在一实施例中，提供保护层18以覆盖薄化晶片10”的第二表面10b”及粘着层14的暴露部分14p，且其可延伸覆盖住载板12的边缘12e。保护层18的材料可为介电材料如氧化膜、氮化膜、碳化膜、以聚合物为主的材料、聚酰亚胺、环氧树脂、旋涂式玻璃(SOG)、旋涂(spin-on)材料或前述的组合，利用化学气相沉积(CVD)、物理气相沉积(PVD)、旋转式涂布法(spin-on coating)、射出、印刷或其他未来发展的沉积工艺形成。在提供穿孔40的晶片10的实施例中，保护层18是形成在薄化基板11”的背面11b”，如图2B所示，其可在后续工艺中部分移除。图2B为示出在背面11b”的保护层18，而在形成保护层18之前，可在背面11b”上执行任何其他的工艺。
图1D及图1E为在薄化晶片10”上接合多个裸片20而形成裸片-对-晶片堆叠的剖面图。在薄化晶片10”的表面10b”上，形成包括电性连接(electricalconnections)及/或其他结构(所指为导电结构44)的背侧金属化层，而后在薄化晶片10”上接合裸片20，其中其连接方法包括一般常用的方法如氧化物-对-氧化物接合、氧化物-对-硅接合、铜-对-铜接合、粘着接合或其他金属如焊锡接合等。在背侧金属化工艺中可移除部分保护层18以暴露出用于外部接点(external contact)的导电区域。裸片20可包含存储器芯片、无线电射频(RF)芯片、逻辑芯片等。各裸片含有第一表面及第二表面，而在第一表面上形成集成电路。在一实施例中，在裸片20的第一表面接合上薄化晶片10”。在一实施例中，在裸片20的第二表面接合上薄化晶片10”。在提供包含穿孔40的晶片10的实施例中，如图2C所示，在穿孔40的一端40a上形成导电结构44如焊料凸块或铜凸块以接合裸片20的第二表面或第一表面。导电结构44也包括重分布层(redistribution layers，RDLs)及接合垫，在形成焊料凸块或铜凸块之前，可在薄化晶片10的表面10b”上形成接合垫。在背面金属化工艺中，可部分移除保护层18，例如由穿孔40的一端40a移除。在一实施例中，保护层18仍在薄化基板11”的背面11b”上。
图1F为在裸片-到-晶片堆叠上进行成型工艺的剖面图。在裸片-到-晶片堆叠上覆盖成型化合物22并填入相邻裸片20间的剩余空间，但可不覆盖薄化晶片10”的边缘区域。成型化合物22可为可固化材料如聚合物为主的材料、树脂为主的材料、聚酰亚胺、氧化硅、环氧树脂、苯并环丁烯(benzocyclobutenes，BCB)、SilkTM(Dow Chemical)或前述的组合。成型工艺包括射出成型、压缩成型、模板印刷(stencil printing)、旋涂覆盖或其他未来发展的沉积工艺。在覆盖成型化合物22之后，进行固化或烘烤步骤固化保护材料。
一般在晶片级(wafer-level)测试完成后，会在成型化合物顶部叠上胶带，而后将裸片-到-晶片堆叠从载板12分离以暴露薄化晶片10”的第一表面10a。分离工艺是借由如利用溶剂、利用紫外光照射或剥除(pulled off)。另外，在薄化晶片10”的第一表面10a上，形成各半导体芯片的外部接触(也即焊料凸块、包含铜的凸块或其组合)以与电性终端接合，接着按一般方式沿着分割线切割封装后的裸片-到-晶片堆叠以形成个别的半导体封装体。在切割之后，通过如各向异性导电膜(anisotropically conductive connection film)在IC卡上安装堆叠的一或多个芯片。
图3A至图3B的剖面图说明在裸片-到-晶片堆叠形成粘着材料的保护层的实施例。与在图1A至图1F及图2A至图2C相同或类似的叙述在此省略。借粘着层14在载板12上贴附上晶片10，而后晶片10进行薄化工艺至所需的最终厚度。为了避免在后续蚀刻工艺中破坏粘着层14的暴露部分14p，如图3B所示，在晶片薄化工艺后，形成保护层18以覆盖邻近晶片边缘10e的粘着层14的暴露部分14p。保护层18也可延伸覆盖薄化晶片10”的边缘10e，但没有覆盖整个暴露表面10b”。保护层18可更进一步的延伸覆盖载板12的边缘12e。在后续蚀刻工艺中可借由保护层18保护暴露部分14p，而不露出粘着层14。而后，在薄化晶片10”的表面10b”上，形成包含电性连接及/或其他结构的背侧金属化层，而后在薄化晶片10”接合上裸片20。接下来，如图3B所示，在裸片-到-晶片堆叠上覆盖成型化合物22且填入相邻裸片20间的剩余空间。
虽然本发明已以数个优选实施例揭示于上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (9)

1.一种半导体封装工艺，包括：
提供一晶片，该晶片具有相对的第一表面及第二表面；
利用一粘着层将该晶片的第一表面贴附至一载板而暴露出邻近该晶片一边缘的部分该粘着层；
自该第二表面薄化该晶片，以形成一薄化后的晶片；
形成一保护层以覆盖该粘着层的该暴露部分及该晶片边缘的部分载板；
在该薄化后的晶片的该第二表面上形成包括电性连接和/或导电结构的背侧金属化层，而后接合多个裸片在该薄化后的晶片上；以及
利用一成型化合物封装该薄化后的晶片及所述多个裸片。
2.如权利要求1所述的半导体封装工艺，其中该保护层覆盖该晶片边缘。
3.如权利要求1所述的半导体封装工艺，其中该保护层覆盖至少一部分该晶片的第二表面。
4.如权利要求1所述的半导体封装工艺，其中该保护层包括氧化膜、氮化膜、碳化膜、干膜、旋涂材料膜或前述的组合。
5.如权利要求1所述的半导体封装工艺，其中该晶片包括：
一半导体基板，具有一正面及一背面；
一穿孔，填充有一导电材料，该穿孔至少通过一部分该半导体基板；以及
一集成电路，形成在该半导体基板的正面上。
6.如权利要求5所述的半导体封装工艺，其中该晶片进行薄化后，该半导体基板的背面上暴露出该穿孔的一端。
7.如权利要求5所述的半导体封装工艺，其中该晶片进行薄化后，在该半导体基板的背面上形成该保护层。
8.如权利要求6所述的半导体封装工艺，还包括在该薄化后的晶片上接合所述多个裸片之前，在该半导体基板的背面上所暴露出该穿孔的该端形成该导电结构。
9.如权利要求8所述的半导体封装工艺，其中该导电结构包括一重分布层。
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8691690B2 (en) * 2010-09-13 2014-04-08 International Business Machines Corporation Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects
JP2013030537A (ja) * 2011-07-27 2013-02-07 Elpida Memory Inc 半導体装置の製造方法
JP5406257B2 (ja) * 2011-09-07 2014-02-05 東京エレクトロン株式会社 接合方法、プログラム、コンピュータ記憶媒体及び接合システム
US8765578B2 (en) * 2012-06-06 2014-07-01 International Business Machines Corporation Edge protection of bonded wafers during wafer thinning
US9882007B2 (en) * 2012-07-03 2018-01-30 Rfhic Corporation Handle for semiconductor-on-diamond wafers and method of manufacture
US8928120B1 (en) * 2013-06-28 2015-01-06 Taiwan Semiconductor Manufacturing Company Limited Wafer edge protection structure
KR102259959B1 (ko) 2013-12-05 2021-06-04 삼성전자주식회사 캐리어 및 이를 이용하는 반도체 장치의 제조 방법
KR102165266B1 (ko) 2014-04-03 2020-10-13 삼성전자 주식회사 반도체 소자 및 반도체 패키지
US9184104B1 (en) * 2014-05-28 2015-11-10 Stats Chippac, Ltd. Semiconductor device and method of forming adhesive layer over insulating layer for bonding carrier to mixed surfaces of semiconductor die and encapsulant
KR102261814B1 (ko) 2014-06-16 2021-06-07 삼성전자주식회사 반도체 패키지의 제조 방법
US9337064B2 (en) 2014-09-15 2016-05-10 Micron Technology, Inc. Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems
US9449877B2 (en) * 2014-09-17 2016-09-20 Asm Technology Singapore Pte Ltd Method of protecting a mounting tape during laser singulation of a wafer
US9922944B2 (en) 2015-02-12 2018-03-20 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
KR102295029B1 (ko) 2015-03-31 2021-08-27 삼성전자주식회사 반도체 소자의 제조방법
DE102015210384A1 (de) * 2015-06-05 2016-12-08 Soitec Verfahren zur mechanischen Trennung für eine Doppelschichtübertragung
CN107710514A (zh) * 2015-06-12 2018-02-16 斯瑞博有限公司 使用陶瓷的插头连接器及插座连接器及其制造方法
DE102017208405B4 (de) * 2017-05-18 2024-05-02 Disco Corporation Verfahren zum Bearbeiten eines Wafers und Schutzfolie
US10535591B2 (en) 2017-08-10 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
KR102296530B1 (ko) * 2017-10-31 2021-09-02 다이킨 고교 가부시키가이샤 적층체
US10522440B2 (en) * 2017-11-07 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
DE102018202254A1 (de) 2018-02-14 2019-08-14 Disco Corporation Verfahren zum Bearbeiten eines Wafers
CN108899272A (zh) * 2018-07-06 2018-11-27 德淮半导体有限公司 用于制造半导体装置的方法
CN110875257B (zh) 2018-09-03 2021-09-28 联华电子股份有限公司 射频装置以及其制作方法
CN110943066A (zh) * 2018-09-21 2020-03-31 联华电子股份有限公司 具有高电阻晶片的半导体结构及高电阻晶片的接合方法
TWI743704B (zh) * 2019-03-18 2021-10-21 日商芝浦機械電子裝置股份有限公司 基板處理裝置及基板處理方法
TWI753304B (zh) * 2019-03-26 2022-01-21 新加坡商Ｐｅｐ創新私人有限公司 封裝方法及面板組件
IT201900006740A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
KR20210009762A (ko) * 2019-07-18 2021-01-27 삼성전자주식회사 팬-아웃 웨이퍼 레벨 패키지 제조 방법
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
WO2022040052A1 (en) * 2020-08-18 2022-02-24 Lam Research Corporation Wafer edge deposition for wafer level packaging
CN115881541A (zh) * 2021-09-28 2023-03-31 聚力成半导体(上海)有限公司 半导体装置的制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002367942A (ja) * 1999-06-07 2002-12-20 Rohm Co Ltd 半導体装置およびその製造方法
CN101017786A (zh) * 2006-02-08 2007-08-15 冲电气工业株式会社 半导体封装的制造方法
CN101079372A (zh) * 2006-05-25 2007-11-28 索尼株式会社 基板处理方法和半导体装置的制造方法
JP2008130704A (ja) * 2006-11-20 2008-06-05 Sony Corp 半導体装置の製造方法
CN101331585A (zh) * 2005-12-16 2008-12-24 信越半导体株式会社 贴合基板的制造方法

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
KR100304197B1 (ko) * 1998-03-30 2001-11-30 윤종용 소이제조방법
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
KR100364635B1 (ko) * 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
EP1472730A4 (en) 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
JP2004079951A (ja) * 2002-08-22 2004-03-11 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7960830B2 (en) * 2003-11-14 2011-06-14 Industrial Technology Research Institute Electronic assembly having a multilayer adhesive structure
US7697673B2 (en) * 2003-11-17 2010-04-13 Apptera Inc. System for advertisement selection, placement and delivery within a multiple-tenant voice interaction service system
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US8124455B2 (en) * 2005-04-02 2012-02-28 Stats Chippac Ltd. Wafer strength reinforcement system for ultra thin wafer thinning
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7863188B2 (en) * 2005-07-29 2011-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8138502B2 (en) * 2005-08-05 2012-03-20 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and manufacturing method thereof
US7811904B2 (en) * 2007-01-31 2010-10-12 Alpha And Omega Semiconductor Incorporated Method of fabricating a semiconductor device employing electroless plating
US20080237828A1 (en) 2007-03-30 2008-10-02 Advanced Chip Engineering Technology Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same
US8119500B2 (en) * 2007-04-25 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding
TW200943583A (en) 2008-04-03 2009-10-16 Foxconn Tech Co Ltd LED assembly

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002367942A (ja) * 1999-06-07 2002-12-20 Rohm Co Ltd 半導体装置およびその製造方法
CN101331585A (zh) * 2005-12-16 2008-12-24 信越半导体株式会社 贴合基板的制造方法
CN101017786A (zh) * 2006-02-08 2007-08-15 冲电气工业株式会社 半导体封装的制造方法
CN101079372A (zh) * 2006-05-25 2007-11-28 索尼株式会社 基板处理方法和半导体装置的制造方法
JP2008130704A (ja) * 2006-11-20 2008-06-05 Sony Corp 半導体装置の製造方法

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US8252665B2 (en) 2012-08-28
CN102024713A (zh) 2011-04-20
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