WO2023076066A1 - Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same - Google Patents
Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same Download PDFInfo
- Publication number
- WO2023076066A1 WO2023076066A1 PCT/US2022/046915 US2022046915W WO2023076066A1 WO 2023076066 A1 WO2023076066 A1 WO 2023076066A1 US 2022046915 W US2022046915 W US 2022046915W WO 2023076066 A1 WO2023076066 A1 WO 2023076066A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- monolithic silicon
- silicon structure
- cavity
- assembly
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 196
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title description 39
- 230000000712 assembly Effects 0.000 title description 18
- 238000000429 assembly Methods 0.000 title description 18
- 241000724291 Tobacco streak virus Species 0.000 claims abstract 13
- 239000000463 material Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 22
- 239000010410 layer Substances 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 239000000758 substrate Substances 0.000 description 12
- 238000000605 extraction Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000008393 encapsulating agent Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000000227 grinding Methods 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013626 chemical specie Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3738—Semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Definitions
- the present disclosure generally relates to semiconductor device assemblies, and more particularly relates to semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same.
- Microelectronic devices generally have a die (/.e., a chip) that includes integrated circuitry with a high density of very small components.
- dies include an array of very small bond pads electrically coupled to the integrated circuitry.
- the bond pads are external electrical contacts through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry.
- dies are "packaged" to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines.
- Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).
- environmental factors e.g., moisture, particulates, static electricity, and physical impact.
- Figure 1 is a simplified schematic cross-sectional view of a monolithic silicon structure for thermal dissipation in accordance with one embodiment of the present disclosure.
- Figures 2 through 10 are simplified schematic cross-sectional views of semiconductor device assemblies at various stages in a process of fabrication in accordance with embodiments of the present disclosure.
- Figures 1 1 through 14 are simplified schematic cross-sectional views of monolithic silicon structures for thermal dissipation at various stages in a process of fabrication in accordance with embodiments of the present disclosure.
- Figures 15 through 20 are simplified schematic cross-sectional views of semiconductor device assemblies at various stages in a process of fabrication in accordance with embodiments of the present disclosure.
- Figures 21 through 25 are simplified schematic cross-sectional views of monolithic silicon structures for thermal dissipation at various stages in a process of fabrication in accordance with embodiments of the present disclosure.
- Figure 26 is a simplified schematic cross-sectional view of a semiconductor device assembly in accordance with one embodiment of the present disclosure.
- Figure 27 is a schematic view showing a system that includes a semiconductor device assembly configured in accordance with an embodiment of the present disclosure.
- substrate can refer to a wafer-level substrate or to a singulated, die-level substrate.
- structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
- Some semiconductor device assemblies include structures configured to assist in the extraction of heat from one or more semiconductor devices in the assembly. These structures are frequently formed from metals with high thermal conductivity, such as copper, silver, aluminum, or alloys thereof. Because the coefficient of thermal expansion (CTE) of these metals may vary greatly from the CTE of the semiconductor devices in the assembly, delamination, cracking, or other types of mechanical damage due to thermal cycling can pose a challenge to these assemblies. Moreover, the fabrication techniques used to form structures from these metals, and to shape them to accommodate additional devices in the assembly, require different tooling than is used for most other assembly processes and can greatly increase the expense of the assemblies in which they are integrated.
- CTE coefficient of thermal expansion
- various embodiments of the present application provide semiconductor device assemblies in which a monolithic silicon structure is provided for thermal dissipation between the surface of a lower die in a multi-die structure and an outer (e.g., upper) surface of the assembly.
- the monolithic silicon structure can include cavities extending partially or completely therethrough, in which additional semiconductor devices (e.g., dies, die stacks, packages, assemblies, etc.) can be provided.
- the additional semiconductor devices can be electrically coupled to the same surface of the lower die to which the monolithic silicon structure is attached (e.g., by oxide-oxide bonding, hybrid bonding, adhesive, interconnects, or the like).
- the monolithic silicon structure by virtue of its high thermal conductivity and the close match of its coefficient of thermal expansion to that of the lower die, provides improved thermal management without the risks of damage associated with other thermal management structures.
- FIG. 1 is a simplified schematic partial cross-sectional view of a monolithic silicon structure 100 in accordance with an embodiment of the present disclosure.
- Monolithic silicon structure 100 includes one or more cavities (two are illustrated) extending at least part way through the thickness (e.g., into the body) of the monolithic silicon structure 100.
- the structure 100 can be formed, e.g., from a blank silicon wafer, in which cavities have been formed (e.g., by masking and directionally etching, laser ablating, etc.).
- the structure 100 can be kept at a wafer-level for subsequent wafer-level processing steps, or can optionally be singulated prior to subsequent processing steps.
- monolithic silicon structure 100 can be pre-populated with semiconductor devices in the cavities thereof prior to integration into a larger semiconductor device assembly.
- Figure 2 is a simplified schematic cross-sectional view of a monolithic silicon structure 100 in which several semiconductor devices have been disposed in accordance with one embodiment of the present disclosure.
- semiconductor devices 102 e.g., individual dies, vertical stacks of interconnected dice, device packages, device assemblies, etc.
- Each semiconductor device 102 may be secured in the corresponding cavities by an adhesive (e.g., a thermal interface material) between the back surface of the semiconductor device and the facing interior surface of the cavity.
- the cavities may be sized such that small gaps 103 (e.g., optionally filled with an adhesive, an underfill, an encapsulant, or the like) remain surrounding the semiconductor devices 102 to ease the process of disposing them in the cavities.
- gaps 103 may be minimized or even eliminated through careful matching of the exterior dimensions of the semiconductor devices 102 and the cavities.
- a redistribution layer 104 including one or more thermal pads 105 (e.g., comprising copper, silver, aluminum, or other metals compatible with a metal-metal bonding operation) aligned with the monolithic silicon structure 100 and one or more interconnects 106 (e.g., pads, pillars, UBMs, pins, solder balls, etc.) operatively coupled to the semiconductor devices 102 can be formed.
- thermal pads 105 e.g., comprising copper, silver, aluminum, or other metals compatible with a metal-metal bonding operation
- interconnects 106 e.g., pads, pillars, UBMs, pins, solder balls, etc.
- the redistribution layer can be omitted and semiconductor devices 102 can be provided with interconnects prior to population into the monolithic silicon structure 100 (e.g., coplanar with the bonding surface of the monolithic silicon structure 100).
- the populated monolithic silicon structure 100 is illustrated being aligned in preparation for bonding to another semiconductor device (e.g., the aforementioned lower semiconductor device in the assembly), in accordance with one embodiment of the present disclosure.
- the lower semiconductor device 1 10 includes a dielectric layer 109 in which are disposed electrical contacts 107 and thermal contacts 108.
- the populated monolithic silicon structure 100 can be bonded to the lower semiconductor device 1 10 such that the thermal pads 105 are coupled to the thermal contacts 107 and the interconnects 106 are coupled to the electrical contacts 108 to form semiconductor device assembly 400, as illustrated in accordance with one embodiment of the disclosure in Figure 4.
- the bonding operation can be a hybrid bonding operation, in which a dielectric-dielectric bond (e.g., an oxide-oxide bond) is formed between the dielectric of redistribution layer 104 and the dielectric layer 109 formed over the lower semiconductor device 1 10 and metal-metal bonds are formed between corresponding ones of the thermal pads 105 and the thermal contacts 107, and between corresponding ones of the interconnects 106 and the electrical contacts 108.
- a dielectric-dielectric bond e.g., an oxide-oxide bond
- semiconductor device assembly 400 has been illustrated as formed through a hybrid bonding operation, in other embodiments the bond between a populated monolithic silicon structure and a lower semiconductor device can be achieved with adhesive layers (e.g., thermal interface material (TIM)), solder interconnects with or without underfill, or any other bonding method well known to those skilled in the art.
- adhesive layers e.g., thermal interface material (TIM)
- solder interconnects with or without underfill, or any other bonding method well known to those skilled in the art.
- semiconductor device assembly 400 can optionally be subject to further processing to remove the portions of the monolithic silicon structure 100 overlying the cavities in which semiconductor devices 102 have been disposed, in order to reduce a height of the assembly and/or to provide additional connectivity options.
- Figure 5 is a simplified schematic cross-sectional view of a semiconductor device assembly 500, in which an assembly like that illustrated in Figure 4 has been subjected to a backside thinning operation (e.g., by chemical-mechanical polishing (CMP), grinding, etc.) to remove portions of material from the monolithic silicon structure 100 in order to expose the back surfaces of semiconductor devices 102 and to reduce the overall height of the assembly 500.
- CMP chemical-mechanical polishing
- FIG. 6 is illustrated a simplified schematic cross- sectional view of a semiconductor device assembly 600.
- additional semiconductor devices 11 1 e.g., individual dies, vertical stacks of interconnected dice, device packages, device assemblies, etc.
- the additional semiconductor devices 1 1 1 can then be encapsulated by a layer of mold material 1 12 to provide mechanical protection thereto.
- one or more additional pre-populated monolithic silicon structures can be bonded to the semiconductor assembly 500 illustrated in Figure 5 to provide an assembly with a high density of devices while retaining good thermal performance.
- Figure 7 is illustrated a simplified schematic cross-sectional view of a semiconductor device assembly 700, in which an assembly like that illustrated in Figure 5 has had an additional monolithic silicon structure 1 13 populated with semiconductor devices bonded to thereto.
- the material of a monolithic silicon structure covering the back surfaces of the semiconductor devices populated in cavities thereof can merely be thinned sufficiently to permit the formation of vias (e.g., through-silicon vias (TSVs)) through the thinned material to connect to the backside contacts of the semiconductor devices.
- vias e.g., through-silicon vias (TSVs)
- FIG. 8 is shown an assembly like that of Figure 4 that has been subjected to a backside thinning operation which removed a portion of the material covering the back surfaces of the semiconductor devices in the cavities, and has been further subjected to a TSV formation operation (e.g., forming openings through the silicon material, passivating the openings, removing the passivation from the bottom of the openings to expose backside contacts, plating a conductor into the openings, etc.) providing TSVs 1 14 extending through the thinned material to contact backside contacts of the semiconductor devices to facilitate further connectivity.
- a TSV formation operation e.g., forming openings through the silicon material, passivating the openings, removing the passivation from the bottom of the openings to expose backside contacts, plating a conductor into the openings, etc.
- FIG. 9 a simplified schematic cross-sectional view of a semiconductor device assembly 900 is illustrated, in which an assembly like that shown in Figure 8 has had additional semiconductor devices 1 1 1 (e.g., individual dies, vertical stacks of interconnected dice, device packages, device assemblies, etc.) connected to the TSVs 1 14 extending through the monolithic silicon structure 100 to semiconductor devices 102 (e.g., through traditional flip-chip interconnections, solder ball arrays, hybrid bonding, etc. .
- the additional semiconductor devices 1 11 can then be encapsulated by a layer of mold material 1 12 to provide mechanical protection thereto, as described in greater detail above with reference to Figure 6.
- one or more additional pre-populated monolithic silicon structures can be bonded to the semiconductor assembly illustrated in Figure 8 to provide an assembly with a high density of devices while retaining good thermal performance.
- Figure 10 One such assembly is shown in Figure 10, in which is illustrated a simplified schematic cross- sectional view of a semiconductor device assembly 100, in which an assembly like that illustrated in Figure 8 has had an additional monolithic silicon structure 1 13 populated with semiconductor devices bonded to thereto.
- a monolithic silicon structure can be fabricated from a blank silicon wafer via traditional etching techniques for forming openings or cavities in silicon.
- methods for fabricating monolithic silicon structures can include highly-controllable and high-speed etching processes as set forth in greater detail below, in accordance with various embodiments of the present disclosure.
- FIG. 1 1 a precursor structure from which a monolithic silicon structure will be formed is shown in a simplified partial cross-sectional view at a step in the formation process in accordance with one embodiment of the present disclosure.
- the precursor structure includes a silicon wafer 1 100 on which has been formed passivation layer 1 101 (e.g., a dielectric material) in which are formed one or more thermal pads 1 102.
- a mask layer 1 103 is formed over the passivation layer 1 101 , with a pattern corresponding to the cavities to be formed in the silicon wafer 1 100.
- the mask layer 1103 includes a pattern of small openings (e.g., corresponding to narrow columnar or fin-like structures) that overlie a region in the silicon wafer 1 100 where the cavities are to be formed.
- the small openings 1 104 can be etched at least partially into a thickness of the silicon wafer 1100 to remove some of the material from where the cavities are to be formed.
- a subsequent isotropic (e.g., wet) etch operation can be performed to remove the remaining material from the silicon wafer 1 100 where the cavities are to be formed.
- the result of such an operation is illustrated in Figure 13, which shows cavities 1 105 having been formed by this two- step anisotropic and isotropic etching process in accordance with one embodiment of the present disclosure.
- some embodiments of the disclosure can involve attaching a monolithic silicon structure to a semiconductor device, backside thinning the monolithic silicon structure to reveal the cavities therein, and subsequently disposing semiconductor devices inside the cavities.
- One such approach to forming a semiconductor device assembly is shown at various stages in the process in Figures 15 to 20, according to various embodiments of the present disclosure.
- the monolithic silicon structure 1400 of Figure 14 is shown after having been bonded to a lower semiconductor device 1401 in accordance with one aspect of the disclosure.
- monolithic silicon structure 1400 is bonded to the lower semiconductor device 1401 such that the thermal pads 1 102 are coupled to thermal contacts 1402 of the lower semiconductor device 1401 .
- the bonding operation can be a hybrid bonding operation, in which a dielectric-dielectric bond (e.g., an oxide-oxide bond) is formed between the dielectric 1 101 of the monolithic silicon structure and a dielectric layer 1403 formed over the lower semiconductor device 1401 and metal-metal bonds are formed between corresponding ones of the thermal pads 1 102 and the thermal contacts 1402.
- a dielectric-dielectric bond e.g., an oxide-oxide bond
- the monolithic silicon structure 1400 can, after bonding to the lower semiconductor device 1401 , be subjected to a backside thinning operation (e.g., by chemical-mechanical polishing (CMP), grinding, etc.) to remove portions of material from the monolithic silicon structure 1400 in order to expose the cavities 1 105, as illustrated in Figure 16.
- CMP chemical-mechanical polishing
- semiconductor devices e.g., individual dies, vertical stacks of interconnected dice, device packages, device assemblies, etc.
- an encapsulant e.g., mold material
- Subsequent processing steps e.g., singulating the assembly 1700 from wafer- or panel-level, thinning and providing external connections to the lower semiconductor device 1401 , etc. can be performed at this point (and are not illustrated to preserve the clarity of the disclosure).
- the semiconductor device assembly 1700 can be subjected to additional processing operations to remove the overlying portions of the encapsulant material 1702 and expose the back surfaces of the semiconductor devices 1701 , analogously to the processes described above with reference to Figures 4 and 5, in order to thin the assembly 1700 and/or prepare the assembly for additional connectivity.
- Figure 18 is a simplified schematic cross-sectional view of a semiconductor device assembly 1800, in which an assembly like that illustrated in Figure 17 has been subjected to a backside thinning operation (e.g., by chemical-mechanical polishing (CMP), grinding, etc.) to remove overlying portions of the encapsulant 1702 in order to expose (and optionally to planarize) the back surfaces of semiconductor devices 1701 and to reduce the overall height of the assembly 1800.
- CMP chemical-mechanical polishing
- semiconductor devices 1701 include backside contacts for further connectivity
- removing the portions of material from the encapsulant 1702 covering the back surfaces of semiconductor devices 1701 can permit additional devices to be integrated into the semiconductor device assembly, as described in greater detail above with respect to Figures 6 and 7.
- additional semiconductor devices can be directly attached to the exposed backside contacts of semiconductor devices 1701 and then encapsulated by a layer of mold material (e.g., analogously to the arrangement illustrated in Figure 6).
- one or more additional pre-populated monolithic silicon structures can be bonded to the semiconductor assembly 1800 illustrated in Figure 18 to provide an assembly with a high density of devices while retaining good thermal performance.
- the processes illustrated in Figures through 18 can be iteratively performed on the assembly 1800 of Figure 18 (e.g., disposing another monolithic silicon structure 1400 over the assembly 1800, thinning the monolithic silicon structure 1400 to open the cavities 1 105 therein, disposing additional semiconductor devices in the exposed cavities, encapsulating with a mold material, and optionally thinning the overlying mold material), to provide an assembly with a high density of devices while retaining good thermal performance.
- the foregoing processes can be mixed, matched, and iteratively repeated, such that additional tiers of semiconductor devices can be provided until a desired device density has been achieved.
- FIG. 19 illustrates a process by which the lower semiconductor device 1401 can be thinned and provided with TSVs and backside contacts in accordance with one aspect of the present disclosure.
- semiconductor device assembly 1800 has been bonded to a temporary carrier wafer 1901 by a layer of adhesive 1902 disposed over the monolithic silicon structure 1400 and the exposed back surfaces of semiconductor devices 1701 .
- the back surface of lower semiconductor device 1401 can be thinned (e.g., by CMP, grinding, etc.) to reduce a total height of the assembly and to permit the formation of TSVs 1903 through a remaining thickness of lower semiconductor device 1401.
- Backside contacts e.g., pads, pillars, under-bump metallization (UBM), etc.
- UBM under-bump metallization
- buried TSVs already formed in lower semiconductor device 1401 at an earlier stage of processing may merely be exposed by the thinning operation illustrated in Figure 19.
- temporary carrier wafer 1901 and adhesive 1902 can be removed, resulting in completed semiconductor device assembly 2000, as illustrated in Figure 20.
- FIG. 21 illustrates the fabrication and integration of one embodiment of a monolithic silicon structure which includes metallic heat extraction structures.
- the precursor structure includes a silicon wafer 2100 on which has been formed passivation layer 2101 (e.g., a dielectric material) in which can optionally be formed one or more thermal pads (not illustrated).
- passivation layer 2101 e.g., a dielectric material
- a mask layer 2102 is formed over the passivation layer 2101 , with a pattern corresponding both to the cavities and the metallic heat extraction structures to be formed in the silicon wafer 2100.
- the mask layer 2102 includes a pattern of small openings (e.g., corresponding to narrow columnar or fin-like structures) that overlie both regions in the silicon wafer 2100 where the cavities are to be formed and regions in the silicon wafer 2100 where the metallic heat extraction structures are to be formed.
- a pattern of small openings e.g., corresponding to narrow columnar or fin-like structures
- the small openings 2103 can be etched at least partially into a thickness of the silicon wafer 2100 to remove some of the material from where the cavities are to be formed and to create openings in which metallic heat extraction structures can be plated. Having anisotropically etched these “slivers” of material out of the silicon wafer 2100, a plating operation can then be formed to fill the small openings 2103 with metallic structures, both in the regions where cavities are to be formed and in the regions where the metallic heat extraction structures 2105 are to remain.
- the excess metal material can be removed (e.g., by a CMP operation, a grinding operation, a wet etch operation, etc.), and another mask structure 2106 can be disposed over the silicon wafer 2100, with openings exposing the metal material in the regions where the cavities are to be formed, but not exposing the metallic heat extraction structures 2105.
- a subsequent isotropic (e.g., wet) etch operation can be performed to remove the metal structures and the remaining silicon material from the silicon wafer 2100 where the cavities are to be formed.
- the result of such an operation is illustrated in Figure 25, which shows cavities 2107 and metallic heat extraction structures 2105 having been formed by this process in accordance with one embodiment of the present disclosure.
- monolithic silicon structure 2500, with included metallic heat extraction structures 2105 and cavities 2107 is ready for the processes previously described in greater detail above with reference to Figures 2 through 10 and/or 15 through 20.
- Figure 26 illustrates a simplified schematic cross-sectional view of a semiconductor device assembly 2600 in accordance with one embodiment of the present disclosure.
- Assembly 2600 includes a monolithic silicon structure 2500 in which are disposed metallic heat extraction structures 2105 for extracting heat from a lower semiconductor device 2602 (e.g., through contact with thermal contacts in the lower semiconductor device 2602).
- the assembly 2600 further includes one or more semiconductor devices (two are illustrated) in cavities of the monolithic silicon structure, coupled to the lower semiconductor device 2602.
- embodiments of the present disclosure contemplate wafer-level processing in which an un-singulated wafer comprising a plurality of lower semiconductor devices is bonded to a wafer-level monolithic silicon structure to provide a wafer-level intermediate structure from which individual assemblies can be singulated.
- singulated monolithic silicon structures can be individually bonded to an un-singulated wafer comprising a plurality of lower semiconductor devices.
- singulated monolithic silicon structures can be individually bonded to singulated lower semiconductor devices.
- monolithic silicon structures have been illustrated and described as including thermal pads or metallic heat extraction structures in contact with corresponding thermal contacts on a lower semiconductor device, in other embodiments these features can be omitted and a monolithic silicon structure can be bonded to a surface of a lower semiconductor device without any intermediating metal structures.
- monolithic silicon structures have been illustrated and described as including two cavities of the same depth and plan area with similarly-sized semiconductor devices therein, those of skill in the art will readily appreciate that the number of cavities is not so limited, and monolithic silicon structures in other embodiments may have more or fewer cavities, cavities of different plan areas and/or depths to accommodate semiconductor devices (or other electrical components, including passive circuit components) of different sizes and shapes.
- monolithic silicon structures have been illustrated and described as disposed over a lower semiconductor die having a same plan area as the monolithic silicon structure, those of skill in the art will readily appreciate that monolithic silicon structures can be employed in other arrangements (e.g., bonded to more than one lower die, bonded to a device substrate, etc.) and need not have a same plan area as the device on which they are carried.
- the semiconductor device assemblies illustrated and described above could include memory dies, such as dynamic random access memory (DRAM) dies, NOT-AND (NAND) memory dies, MOTOR (NOR) memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like.
- memory dies such as dynamic random access memory (DRAM) dies, NOT-AND (NAND) memory dies, MOTOR (NOR) memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like.
- the semiconductor devices could be memory dies of a same kind (e.g., both NAND, both DRAM, etc.) or memory dies of different kinds (e.g., one DRAM and one NAND, etc. .
- the semiconductor dies of the assemblies illustrated and described above could include logic dies (e.g., controller dies, processor dies, etc.), or a mix of logic and memory dies (e.g., a memory controller die and a memory die controlled thereby).
- logic dies e.g., controller dies, processor dies, etc.
- a mix of logic and memory dies e.g., a memory controller die and a memory die controlled thereby.
- any one of the semiconductor devices and semiconductor device assemblies described above can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 2700 shown schematically in Figure 27.
- the system 2700 can include a semiconductor device assembly (e.g., or a discrete semiconductor device) 2702, a power source 2704, a driver 2706, a processor 2708, and/or other subsystems or components 2710.
- the semiconductor device assembly 2702 can include features generally similar to those of the semiconductor devices described above.
- the resulting system 2700 can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions.
- representative systems 2700 can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, appliances and other products.
- Components of the system 2700 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network).
- the components of the system 2700 can also include remote devices and any of a wide variety of computer readable media.
- the devices discussed herein, including a memory device may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.
- the substrate is a semiconductor wafer.
- the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate.
- SOI silicon-on-insulator
- SOG silicon-on-glass
- SOP silicon-on-sapphire
- the conductivity of the substrate, or sub-regions of the substrate may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ionimplantation, or by any other doping means.
- the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation. [0048] It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020247017335A KR20240090930A (en) | 2021-11-01 | 2022-10-17 | Semiconductor device assemblies including monolithic silicon structures for heat dissipation and methods of manufacturing the same |
CN202280077152.4A CN118285163A (en) | 2021-11-01 | 2022-10-17 | Semiconductor device assembly including monolithic silicon structure for heat dissipation and method of manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163274427P | 2021-11-01 | 2021-11-01 | |
US63/274,427 | 2021-11-01 | ||
US17/719,241 | 2022-04-12 | ||
US17/719,241 US20230139175A1 (en) | 2021-11-01 | 2022-04-12 | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2023076066A1 true WO2023076066A1 (en) | 2023-05-04 |
Family
ID=86147327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2022/046915 WO2023076066A1 (en) | 2021-11-01 | 2022-10-17 | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US20230139175A1 (en) |
KR (1) | KR20240090930A (en) |
CN (1) | CN118285163A (en) |
TW (1) | TWI830470B (en) |
WO (1) | WO2023076066A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230136202A1 (en) * | 2021-11-01 | 2023-05-04 | Micron Technology, Inc. | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110215470A1 (en) * | 2010-03-04 | 2011-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Wafers in 3DIC Package Assemblies |
US20120146209A1 (en) * | 2010-12-14 | 2012-06-14 | Unimicron Technology Corporation | Packaging substrate having through-holed interposer embedded therein and fabrication method thereof |
CN110246802A (en) * | 2018-03-09 | 2019-09-17 | 株式会社迪思科 | The processing method of package substrate |
US20200273773A1 (en) * | 2019-02-25 | 2020-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20200402877A1 (en) * | 2016-11-14 | 2020-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package Structures and Methods of Forming the Same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006062473A1 (en) * | 2006-12-28 | 2008-07-03 | Qimonda Ag | Semiconductor device for use in semiconductor component, has chip with active and rear sides, where chip is arranged over one side of substrate, and completely encapsulated with only one material |
TWI573201B (en) * | 2008-07-18 | 2017-03-01 | 聯測總部私人有限公司 | Packaging structural member |
TWI405361B (en) * | 2008-12-31 | 2013-08-11 | Ind Tech Res Inst | Thermoelectric device and process thereof and stacked structure of chips and chip package structure |
US8518746B2 (en) * | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
KR101145041B1 (en) * | 2010-10-19 | 2012-05-11 | 주식회사 네패스 | Semiconductor chip package, semiconductor module and fabrication method thereof |
US10008395B2 (en) * | 2016-10-19 | 2018-06-26 | Micron Technology, Inc. | Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill |
KR20200044497A (en) * | 2018-10-19 | 2020-04-29 | 삼성전기주식회사 | Fan-out semiconductor package |
CN111554639A (en) * | 2020-04-02 | 2020-08-18 | 珠海越亚半导体股份有限公司 | Embedded chip package and method of manufacturing the same |
-
2022
- 2022-04-12 US US17/719,241 patent/US20230139175A1/en active Pending
- 2022-10-17 CN CN202280077152.4A patent/CN118285163A/en active Pending
- 2022-10-17 KR KR1020247017335A patent/KR20240090930A/en unknown
- 2022-10-17 WO PCT/US2022/046915 patent/WO2023076066A1/en active Application Filing
- 2022-10-31 TW TW111141290A patent/TWI830470B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110215470A1 (en) * | 2010-03-04 | 2011-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Wafers in 3DIC Package Assemblies |
US20120146209A1 (en) * | 2010-12-14 | 2012-06-14 | Unimicron Technology Corporation | Packaging substrate having through-holed interposer embedded therein and fabrication method thereof |
US20200402877A1 (en) * | 2016-11-14 | 2020-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package Structures and Methods of Forming the Same |
CN110246802A (en) * | 2018-03-09 | 2019-09-17 | 株式会社迪思科 | The processing method of package substrate |
US20200273773A1 (en) * | 2019-02-25 | 2020-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
TW202329355A (en) | 2023-07-16 |
TWI830470B (en) | 2024-01-21 |
CN118285163A (en) | 2024-07-02 |
KR20240090930A (en) | 2024-06-21 |
US20230139175A1 (en) | 2023-05-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11961811B2 (en) | Semiconductor structures and method of manufacturing the same | |
TWI780293B (en) | Semiconductor device and manufacutring method thereof | |
US11699694B2 (en) | Method of manufacturing semiconductor package structure | |
US11658069B2 (en) | Method for manufacturing a semiconductor device having an interconnect structure over a substrate | |
US11855067B2 (en) | Integrated circuit package and method | |
US20220375793A1 (en) | Semiconductor Device and Method | |
US20230139175A1 (en) | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same | |
US20230139914A1 (en) | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same | |
CN113838822A (en) | Substrate-less semiconductor device assembly having a plurality of semiconductor devices and method of manufacturing the same | |
EP4135020A2 (en) | Bond pads for semiconductor die assemblies and associated methods and systems | |
US20230260941A1 (en) | Semiconductor Device and Method | |
US20230136202A1 (en) | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same | |
TWI846093B (en) | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same | |
US20230245947A1 (en) | Integrated circuit package and method | |
US11664315B2 (en) | Structure with interconnection die and method of making same | |
US11715646B2 (en) | Semiconductor structure and method for forming the same | |
US20230335534A1 (en) | Integrated Circuit Packages and Methods of Forming the Same | |
CN118299276A (en) | Method for forming integrated circuit package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 22887944 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 20247017335 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2022887944 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2022887944 Country of ref document: EP Effective date: 20240603 |