CN102254858A - 用于制造半导体器件的方法和包括具有通孔的芯片的半导体器件 - Google Patents

用于制造半导体器件的方法和包括具有通孔的芯片的半导体器件 Download PDF

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CN102254858A
CN102254858A CN2011101308247A CN201110130824A CN102254858A CN 102254858 A CN102254858 A CN 102254858A CN 2011101308247 A CN2011101308247 A CN 2011101308247A CN 201110130824 A CN201110130824 A CN 201110130824A CN 102254858 A CN102254858 A CN 102254858A
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chip
wafer
electric connection
electrically connected
layer
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CN102254858B (zh
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埃里克·索吉尔
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STMicroelectronics Grenoble 2 SAS
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STMicroelectronics Grenoble 2 SAS
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Abstract

一种用于制造半导体器件的方法和包括具有通孔的芯片的半导体器件，其中：第一晶圆(32)，包括至少一个第一集成电路芯片(2)和围绕该第一芯片的支撑层(7)，第一晶圆(32)的前面包括第一支撑层的前面和第一芯片的有源侧；第一电连接层(33)，被放置在所述第一晶圆的前面，并且包括第一电连接网络(12)；第二晶圆(34)，被放置在第一电连接层的前面，并且包括至少一个第二集成电路芯片(14a)和围绕该第二芯片的支撑层(21a)，所述第二芯片具有位于第一电连接层侧的有源侧以及填充有导体以形成电连接通孔(25)的透孔(24)；以及第二电连接层(35)，被放置在所述第二晶圆上，并且包括第二电连接网络(27)。

Description

用于制造半导体器件的方法和包括具有通孔的芯片的半导体器件
技术领域
本发明涉及半导体器件领域。
背景技术
越来越常见的是，使用具有透孔的集成电路芯片来制作从一侧到另一侧的电连接，并将这种芯片集成在叠生芯片的复杂组件中。为此，已提出：在包括多个芯片的晶圆之芯片的有源侧上制作填充有导体的盲孔；通过紧靠厚的支撑晶圆放置芯片的有源侧，将该承载芯片的晶圆安装在该支撑晶圆上；使承载芯片的晶圆变薄直到暴露出之后形成电连接通孔的导体；可选地借助于层集成电连接网络并通过封装其它芯片，将这些其它芯片装配在变薄的承载芯片的晶圆的背面上；移除支撑晶圆；在承载芯片的晶圆的前面制作电连接层；并且，最后切割最终晶圆，以分离半导体器件。
可以立即注意到，这一过程需要很多操作，并且需要使用支撑晶圆作为制造半导体器件的工具。
提议简化组件的制造，尤其是简化包括至少一个具有电连接通孔的芯片的集成电路芯片的组件制造。
发明内容
根据一种实施方式，一种用于制造半导体器件的方法包括以下步骤。
在特定位置中制作第一晶圆，所述第一晶圆包括第一集成电路芯片和围绕这些第一芯片的第一支撑层，所述第一晶圆的前面包括所述第一支撑层的前面和所述第一芯片的有源侧。
在所述第一晶圆的前面上制作第一电连接层，所述第一电连接层在所述位置上包括第一电连接网络。
在所述位置上安装第二集成电路芯片，并且形成围绕这些芯片的第二支撑层，以便形成中间晶圆，这些第二芯片具有位于所述第一电连接层侧的有源侧以及在所述第一电连接层侧开口并且填充有导体以形成电连接通孔的盲孔。
减小中间晶圆的厚度以便构建第二晶圆，所述第二晶圆包括变薄的第二芯片和变薄的第二支撑层，在所述变薄的第二支撑层中，所述变薄的第二芯片的通孔暴露出前部。
在所述第二晶圆上制作第二电连接层，所述第二电连接层在所述位置上包括第二电连接网络。
因此，在最终结构的每个位置处获得可能即将被分离的半导体器件。
此外，可以在所述位置上在所述第二变薄的支撑层中制作透孔，并使用导体填充这些孔，以便形成电连接通孔。
还可以在所述位置上将分立的外部电连接装置放置在所述第二电连接层上。
还可以切割最终晶圆以便分离所获得的每个半导体器件。
还提出一种半导体器件，包括：第一晶圆，包括至少一个第一集成电路芯片和围绕该第一芯片的支撑层，所述第一晶圆的前面包括所述第一支撑层的前面和所述第一芯片的有源侧；第一电连接层，被放置在所述第一晶圆的前面，并且包括第一电连接网络；第二晶圆，被放置在所述第一电连接层的前面，并且包括至少一个第二集成电路芯片和围绕该第二芯片的支撑层，所述第二芯片具有位于所述第一电连接层侧的有源侧以及填充有导体以形成电连接通孔的透孔；以及第二电连接层，被放置在所述第二晶圆上，并且包括第二电连接网络。
所述第一芯片和所述第二芯片可以借助于所述第一电连接网络进行连接。
所述第一芯片可以借助于所述第一电连接网络、穿过所述第二芯片的至少一些通孔以及所述第二电连接网络连接至前面的电连接装置。
所述第二芯片借助于穿过所述第二芯片的至少一些电连接通孔以及所述第二电连接网络连接至前面的电连接装置。
此外，可以提供穿过所述第二晶圆的支撑层的电连接通孔，这些通孔可能连接至所述第一电连接网络和所述第二电连接网络。
所述第一支撑层、所述电连接层、所述支撑层和所述电连接层可以由相同的基材制成。
附图说明
现在将借助于利用附图示出的非限制性示例来描述用于制造半导体器件的方法和最终的半导体器件，附图中：
图1示出根据集成第一集成电路芯片的一个制造步骤的半导体结构的截面图；
图2示出从图1得到的半导体结构的截面图；
图3示出根据集成第一电连接网络的后续制造步骤的半导体结构的截面图；
图4示出根据用于放置配备有通孔的第二集成电路芯片的后续制造步骤的半导体结构的截面图；
图5示出根据用于放置填充物的后续制造步骤的半导体结构的截面图；
图6示出根据集成第二集成电路芯片的后续制造步骤的半导体结构的截面图；
图7示出根据示出厚度减小的后续制造步骤的半导体结构的截面图；
图8示出根据集成补充通孔的后续制造步骤的半导体结构的截面图；
图9示出根据集成第二电连接网络的后续制造步骤的半导体结构的截面图；
图10示出根据集成外部电连接装置的后续制造步骤的半导体结构的截面图；
图11示出所获得的半导体器件的截面图；以及
图12示出所获得的半导体器件的变体实施例的截面图。
具体实施方式
参见图1至图10，现在将首先描述用于制造诸如图11所示的半导体器件1的多个步骤。
如图1所示，预先制作厚的承载第一芯片2的晶圆，第一芯片2在有源侧3上具有集成电路4，该晶圆被切割以便分离第一芯片2。
接下来，将这些分离后的第一芯片2的有源侧3放置在架构晶圆5上，第一芯片2被隔开，并且被布置在限定相邻位置6的方形矩阵中。第一芯片2可以由临时性的粘结装置保持在适当的位置。然后，将第一支撑层7沉积在多个第一芯片2的周围，该支撑层7例如是厚度例如等于第一芯片2的厚度的固化树脂。
在第一支撑层7已固化并且架构晶圆5已分隔之后，得到如图2所示的具有前面9的第一晶圆8，前面9包括第一支撑层7的前面10和第一芯片2的有源侧3。
有利的是，第一晶圆8形成用于在其上实施现在将描述的操作的支撑，并且会是将要获得的半导体器件的部件。
如图3所示，在第一晶圆8的前面9上制作分别被放置在位置6中的第一电连接层11，该层包括或集成有用于从一侧到另一侧进行电连接的网络12，该第一电连接层11具有前面13。电连接网络12可以具有一个或多个电连接平面。
如图4所示，预先制作厚的承载第二芯片14的晶圆，第二芯片14在有源侧15上具有集成电路16，并且具有从该有源侧15延伸的、填充有电导体的、旨在形成电连接通孔18的盲孔17，该晶圆被切割以便分离第二芯片14。
接下来，通过将第二芯片14的有源侧15放置在第一电连接层11侧，并通过插入用于进行电连接的小突起19，分别在位置6中将第二芯片14安装在第一电连接层11的前面13。
接下来，如图5所示，在电连接层11的前面13与第二芯片14的有源侧15之间的空间中注入填充物20，例如流动性极高的树脂，该树脂围绕突起19扩散。
接着，如图6所示，在多个第二芯片14周围和可选的在多个第二芯片14上沉积第二支撑层21，该支撑层7例如是固化树脂。
在第二支撑层21已固化之后，获得具有前面23的中间晶圆22。
此后，例如通过对中间晶圆22的前面23进行机械抛光，来减小中间晶圆22的厚度，直到获得如图7所示的包括多个变薄的第二芯片14a和变薄的第二支撑层21a的第二晶圆22a，第二晶圆22a具有前面23a。从而暴露第二芯片14的电连接通孔18的前面部分，用于从一侧到另一侧进行电连接。
如图8所示，然后可以可选地在位置6处在位于围绕变薄的第二芯片14a的位置中的变薄的第二支撑层21a中制作透孔24，然后使用电导体填充这些孔24以便形成电连接通孔25。
接下来，如图9所示，在第二晶圆22a的前面23a上制作分别被放置在位置6中的第二电连接层26，该层包括或集成有用于从一侧到另一侧进行电连接的网络27，该第二电连接层26具有前面28。电连接网络27可以具有一个或多个电连接平面。
接下来，如图10所示，可以在第二电连接层26的前面28上沉积电连接突起29。
从而获得在位置6处具有相邻的半导体器件1的最终结构30。
最后，例如使用锯在位置6之间或沿位置6切割最终晶圆30，以便分离如位置6一样多的半导体器件1。
如图11所示，每个半导体器件1包括堆叠：与第一晶圆8的部分相对应并且配备有被支撑层7围绕的第一芯片2的第一晶圆32；与第一电连接层11的部分相对应并且配备有第一电连接网络12的第一电连接层33；与第二晶圆8的部分相对应并且配备有变薄的第二芯片14a和变薄的支撑层21a的第二晶圆34；与第二电连接层26的部分相对应并且配备有第二电连接网络27的第二电连接层35；以及用于进行外部电连接的多个突起29。
通过在如上所述的半导体器件的制造期间分配电连接网络12和27、穿过变薄的第二芯片14a的电连接通孔18和穿过变薄的支撑层22a的补充电连接通孔25，可以在第一芯片2的集成电路4与第二芯片14a的集成电路16以及外部电连接突起29之间选择性地任意建立电连接。
穿过变薄的第二芯片14a的电连接通孔18可以选择性地横向连接至集成电路16或借助于电连接网络12连接至集成电路16，或者在电连接网络12和27之间直接建立链接。
互连层11和26的电连接网络12和27以及可选的电连接通孔25可以允许集成电路芯片2和14(14a)的有源侧3和15没有电连接引线。
有利的是，可以针对第一支撑层7、电连接层11、支撑层21和电连接层26使用相同的基材，例如树脂。
如图12所示，由以上所述的方法获得的半导体器件36可以包括：位于晶圆32中的多个可选的不同的第一芯片2n，以及具有与电连接层11相邻并连接至第一电连接网络12的侧的可选的一个或多个其它分立部件2m。初始的第一晶圆8的厚度可以适合于最厚的第一芯片或分立部件。
同样地，可以在第二晶圆33中提供至少具有电连接通孔18的若干个第二芯片14a。
另外，在图9所示的步骤之后并且在将突起电连接29放置于适当的位置之前，可以通过在电连接层的前面28上一次或多次重复参照图6至图8描述的操作来继续(未示出)半导体器件的架构，以便联接可选地提供有电连接通孔的至少一个新的第二集成电路芯片。
当然，可以采用在微电子领域通用的装置来实施以上所述的各种制造操作。
本发明不限于以上所述的示例。可以在不超出所附权利要求所限定的范围的情况下进行多种其它改变。

Claims (10)

1.一种用于制造半导体器件的方法，包括：
在特定位置(6)中制作第一晶圆(8)，所述第一晶圆(8)包括第一集成电路芯片(2)和围绕这些第一芯片的第一支撑层(7)，所述第一晶圆(8)的前面包括所述第一支撑层的前面和所述第一芯片的有源侧；
在所述第一晶圆(8)的前面上制作第一电连接层(11)，所述第一电连接层(11)在所述位置(6)上包括第一电连接网络(12)；
在所述位置(6)上安装第二集成电路芯片(14)，并且形成围绕这些第二芯片的第二支撑层(21)，以便形成中间晶圆(22)，这些第二芯片具有位于所述第一电连接层侧的有源侧以及在所述第一电连接层侧开口并且填充有导体以形成电连接通孔(18)的盲孔(17)；
减小所述中间晶圆(22)的厚度以便构建第二晶圆(22a)，所述第二晶圆(22a)包括变薄的第二芯片(14a)和变薄的第二支撑层(21a)，在所述变薄的第二支撑层(21a)中，所述变薄的第二芯片的通孔(18)暴露出前部；并且
在所述第二晶圆(22a)上制作第二电连接层(26)，所述第二电连接层(26)在所述位置(6)上包括第二电连接网络(27)，
使得在最终结构的每个位置处获得半导体器件。
2.根据权利要求1所述的方法，在构建所述第二电连接层之前包括：在所述位置(6)上在所述第二变薄的支撑层(22a)中制作透孔(24)，并使用导体填充这些孔，以便形成电连接通孔(25)。
3.根据权利要求1和2中任一项所述的方法，包括：在所述位置(6)上将分立的外部电连接装置(29)放置在所述第二电连接层(26)上。
4.根据前述权利要求中任一项所述的方法，包括：切割最终晶圆以便分离所获得的每个半导体器件(1)。
5.一种半导体器件，包括：
第一晶圆(32)，包括至少一个第一集成电路芯片(2)和围绕该第一芯片的支撑层(7)，所述第一晶圆(32)的前面包括所述第一支撑层的前面和所述第一芯片的有源侧；
第一电连接层(33)，被放置在所述第一晶圆的前面，并且包括第一电连接网络(12)；
第二晶圆(34)，被放置在所述第一电连接层的前面，并且包括至少一个第二集成电路芯片(14a)和围绕该第二芯片的支撑层(21a)，所述第二芯片具有位于所述第一电连接层侧的有源侧以及填充有导体以形成电连接通孔(25)的透孔(24)；以及
第二电连接层(35)，被放置在所述第二晶圆上，并且包括第二电连接网络(27)。
6.根据权利要求5所述的半导体器件，其中所述第一芯片(2)和所述第二芯片(14a)借助于所述第一电连接网络(12)进行连接。
7.根据权利要求5和6中任一项所述的半导体器件，其中所述第一芯片(2)借助于所述第一电连接网络(12)、穿过所述第二芯片的至少一些通孔(18)以及所述第二电连接网络(27)连接至前面的电连接装置(29)。
8.根据权利要求5至7中任一项所述的半导体器件，其中所述第二芯片(14a)借助于穿过所述第二芯片的至少一些通孔(18)以及所述第二电连接网络(27)连接至前面的电连接装置。
9.根据权利要求5至8中任一项所述的半导体器件，包括穿过所述第二晶圆的所述支撑层(21a)的电连接通孔(25)，这些通孔连接至所述第一电连接网络(12)和所述第二电连接网络(27)。
10.根据权利要求5至9中任一项所述的半导体器件，其中所述第一支撑层(7)、所述电连接层(11)、所述支撑层(21)和所述电连接层(26)由相同的基材制成。
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