TWI445144B - 堆疊晶圓級封裝與相關製造方法 - Google Patents

堆疊晶圓級封裝與相關製造方法 Download PDF

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TWI445144B
TWI445144B TW100134177A TW100134177A TWI445144B TW I445144 B TWI445144 B TW I445144B TW 100134177 A TW100134177 A TW 100134177A TW 100134177 A TW100134177 A TW 100134177A TW I445144 B TWI445144 B TW I445144B
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package structure
layer
encapsulant
semiconductor device
device package
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TW100134177A
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TW201308538A (zh
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Karl Appelt Bernd
Kay Essig
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Advanced Semiconductor Eng
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description

堆疊晶圓級封裝與相關製造方法
本發明是有關於一種半導體，且特別是有關於一種半導體組裝與封裝製程。
目前所普遍採用的晶圓級封裝方式(Wafer level packaging；WLP)可大大地改善封裝效率並降低半導體封裝之尺寸。傳統扇入(Fan-in)晶圓級封裝製程是在未切割之晶圓上進行，而使最終封裝產品尺寸約與晶粒大小差不多。而扇出(Fan-out)晶圓級封裝製程則是利用重建晶圓(Reconstitution wafer)，亦即乃將各獨立晶粒重新排列成為人造模鑄晶圓，因此可減少使用昂貴覆晶基底之需求，以封裝膠體擴大封裝尺寸，以供更高輸出/輸入(Input/Output；I/O)端應用。
而立體晶圓級封裝方式(3-D WLP)中堆疊的元件之間相當需要有效率並可靠電性連結。
本發明之一實施例提出一種半導體元件封裝結構。該封裝結構包含具有主動表面的一晶片。該封裝結構更包含部份包覆該晶片且具有上表面的一封裝膠體。該封裝結構更包含一重佈線路層，包括至少一導電層與至少一介電層。該重佈線路層部份形成於該主動表面與部份形成於該封裝膠體的下表面。該封裝結構更包含複數個導電柱位於該封裝膠體內並電性連接至該重佈線路層。該封裝結構更包含位於該封裝膠體上表面的複數個凹陷。該些凹陷之位置對應於該些導電柱之位置。該封裝結構更包含複數個內連線圖案電性連接至該些導電柱。該些內連線圖案中之至少一個延伸至該些凹陷中之至少一個。
本發明之另一實施例提出一種半導體元件封裝結構。該封裝結構包含具有主動表面的一晶片。該封裝結構更包含部份包覆該晶片且具有上表面的一封裝膠體。該封裝結構更包含一重佈線路層，包括至少一導電層與至少一介電層。該重佈線路層部份形成於該主動表面與部份形成於該封裝膠體的下表面。該封裝結構更包含複數個導電柱位於該封裝膠體內並電性連接至該重佈線路層。該封裝結構更包含位於該封裝膠體上表面的複數個凹陷。該些凹陷之位置對應於該些導電柱之位置，且暴露出至少該些導電柱之上表面的至少一部份。該封裝膠體疊蓋住該些導電柱之上表面的邊緣。
本發明之另一實施例提出一種半導體元件封裝結構製造方法。該方法包含形成複數個導電柱位於一犧牲層上。該方法更包括安置至少一晶片於該犧牲層上。。該方法更包括形成一封裝膠體於該犧牲層上，包覆該至少晶片並至少部份包覆該些導電柱。。該方法更包括形成複數個凹陷於該封裝膠體中鄰近該些導電柱之上表面。。該方法更包括形成複數個內連線圖案於該封裝膠體與該些導電柱上，該些內連線圖案至少部份填入該封裝膠體內的該些凹陷。。該方法更包括移除該犧牲層。該方法更包括形成一重佈線路層於該晶片、該些導電柱與該封裝膠體上。該重佈線路層包括至少一導電層與至少一介電層。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1乃是描述依照本發明之一實施例的一種晶圓級封裝結構(WLP) 10。封裝結構10至少包括晶片(亦稱晶粒)110、一封裝膠體130包覆晶片110、多個插柱106埋於封裝膠體130內、內連線圖案(interconnect pattern) 112a連接至該些柱106與導線圖案(trace pattern) 112b以及重佈線路層(redistribution layer；RDL) 116。重佈線路層116包括一第一介電層113、一導電層114與一第二介電層115。其他實施例中，重佈線路層116可為單層結構(僅包括導電層114)。
晶圓級封裝結構10可包括在內連線圖案112a與封裝膠體130間、內連線圖案112a與該些柱106之間以及導線圖案112b與封裝膠體130間形成種層111。透過內連線圖案112a，其上可堆疊其他半導體封裝或堆疊不同電子元件於晶圓級封裝結構10之上，如後續所述。
此外，晶圓級封裝結構10可更包括位於重佈線路層116之導電層114上的電性接點(electrical contacts) 140。電性接點140可為例如銲球來連接晶圓級封裝結構10至外接端如系統級電路板(未圖示)。導電層114電性連接晶片110之接觸墊109與電性接點140或電性連接該些柱106之一至電性接點140之一。在底面之導電層114圖案化成為連接至該些柱106之底內連線圖案114a與底導線圖案114b。晶片110可為積體電路或任意半導體晶片如微電機系統(MEMS)。圖1所示晶圓級封裝結構10僅包含兩晶片，但亦可理解本案之封裝結構端視所需可包括任意數目(單一、二個、或多個)晶片。
實施例中所述的該些插柱106為圓柱狀的，但是其他實施例中該些插柱106也可為其他形狀例如圓錐體狀的。該些柱106可以任意導電材質如銅而製成。舉例而言，相較於電鍍插塞，實心銅柱可提供較優異之導電性。後續會被封裝膠體130包覆且連接至內連線圖案112a的該些插柱106之優點之一即是其深寬比(aspect ratio)變小，亦即插柱對應孔深/孔洞直徑比變小。較低的深寬比可提高插柱無空洞或異變之可能性，也就是改善內連線之可靠度。
圖2A是依照本發明之一實施例的一種堆疊封裝結構剖面示意圖。圖2A所示之堆疊封裝結構22包括多個電子元件20a、20b、20c，堆疊在晶圓級封裝結構10之上。電子元件20a、20b、20c可為晶粒、封裝或其他元件如被動元件等，透過如覆晶技術、表面黏著式(SMT)或其他連結方式，堆疊在晶圓級封裝結構10之上。
圖2B是依照本發明之另一實施例的一種堆疊封裝結構剖面示意圖。圖2B所示之堆疊封裝結構24包括一封裝結構26堆疊在晶圓級封裝結構10之上。封裝結構26與封裝結構10透過多個接點240而電性相連。此實施例中封裝結構26可以是另一個晶圓級封裝結構而在底面具有扇出之重佈線路層(未顯示)，而電性連結至封裝結構10之上表面。
圖3A-3H是依照本發明之一實施例的一種晶圓級封裝結構製造方法的剖面示意圖。如圖3A，先提供一犧牲層100，犧牲層100上表面上具有膠帶102而膠帶102上又覆蓋光阻層104。犧牲層100、膠帶102及光阻層104之下具有硬質載體100C用以支持其上各層。膠帶102及光阻層104中形成有多個開口S。開口S可利用如：紫外光雷射鑽孔、二氧化碳雷射鑽孔或其他技術所形成。犧牲層100可為金屬例如銅箔或其他金屬箔。膠帶102可為例如晶粒黏接膠帶。光阻層104可為如乾膜式光阻層或其他光阻層。
如圖3B，於多個開口S中形成多個插柱106。該些插柱106可以電鍍方式或其他方式形成。實施例中，該些插柱106可以例如圖案電鍍法所形成的金屬例如銅所製得。實施例中，犧牲層100可作為陰極，以便於電鍍形成插柱106於開口S中。
如圖3C，移除光阻層104後，至少一晶片(或晶粒)110面朝下黏附至膠帶102。晶片110包括至少一個接觸墊109位於其朝下面(主動面)118上。此處晶片110乃指重建晶圓之單一晶片或晶粒，而晶片為從晶圓中挑出並測試確定為好的晶片(Known good die；KGD)。晶粒可能限於I/O墊數目而需要扇出以容納較大的外界連接結構如錫球。或者，若完成應用端需要是立體封裝則晶片110可不限於I/O墊數目。晶粒不會置於已經發現插柱電鍍缺陷的位置，因電鍍缺陷會導致次佳電性連接。光學檢查可檢出插柱106電鍍之缺失、不完全或瑕疵。將好的晶片置於好的插柱即可增加封裝良率。
如圖3D，模封犧牲層、膠帶102與其上之晶片110而形成一封裝膠體130覆蓋住晶片110、該些插柱106、膠帶102與犧牲層100。模封可包括壓合模塑製程(compression molding process)，可以減低或避免封裝膠體130內含空隙之產生。
於封裝膠體130中形成多個凹陷S1 ，透過移除一部份之封裝膠體130直至該些插柱106之表面106a露出而得到凹陷S1 。移除過程可以鑽孔步驟例如是紫外光雷射鑽孔或二氧化碳雷射鑽孔來進行。實施例中，凹陷S1 之形狀為傾斜漸縮的或錐狀的，而上開口孔徑121大於底開口孔徑123。其他實施例中，凹陷S1 之形狀可為非傾斜漸縮的與/或孔徑略小於該些柱106之直徑以避免插柱106與封裝膠體130之間有空隙。
接著，如圖3D，封裝膠體130覆蓋該些插柱106上表面106a之邊緣。該些凹陷S1 之形狀為錐狀的，而上開口較大孔徑距離插柱106上表面106a較遠，較小底開口孔徑距離插柱106上表面106a較近。利用例如鑽孔(drilling)步驟形成該些凹陷S1 可導致此開口形狀與封裝膠體130覆蓋該些插柱106之邊緣。若雷射沒有對準插柱106，可能會不當地移除插柱106旁之封裝膠體130，但以實施例之形狀來形成凹陷S1 可降低不當操作可能性。或者，亦可研磨封裝膠體130直至露出插柱上表面106a。
如圖3E，形成一種層111於封裝膠體上表面上與凹陷S1 中並覆蓋插柱上表面106a。種層111可以濺鍍或其他製程製得，種層111之材質可為任意材質，也可為多層結構。例如：種層111為覆蓋銅、鎳或鉻之鎢層。接著，於種層111上形成一導電層112並電性連接至該些柱106。導電層112可為金屬如銅或銅合金，或其他金屬。導電層112可以例如電鍍或其他製程製得。
一般而言，視凹陷S1 之深寬比而定，導電層112可完全填滿或部份填入凹陷S1 。較佳而言，導電層112至少電鍍覆蓋凹陷S1 之側壁並電性連接至該些插柱106。位於凹陷S1 內之導電層112作為插塞將封裝結構底面之訊號傳至封裝結構上面。
如圖3F，圖案化導電層112而於封裝膠體130上表面上形成佈線層或導線圖案112b以及電性連接至金屬柱106的內連線圖案112a。該些圖案可利用例如扣減式蝕刻(subtractive etching)或其他製程形成。圖案化導電層11之後，移除載體100C(圖3E所示)。接著，移除在底面之犧牲層100與一部份之該些插柱106，直到該些插柱底面106b實質上與晶片底面110b齊平。移除過程可包括如蝕刻或其他步驟。或者，金屬插塞106之底面106b可略略突出或凹陷於封裝膠體130之下表面130b。接著，移除膠帶102而暴露出該些插柱106與晶片底面110b，晶片110之接觸墊109也暴露出來。
另一實施例中，可選擇性地移除犧牲層100，移除鄰近該些插柱106之犧牲層100，直到該些插柱底面106b實質上齊平於或略略突出或凹陷於封裝膠體130之下表面130b。然後，勝於之犧牲層100與膠帶102一起移除，而暴露出該些插柱106與晶片底面110b。
如圖3G，形成一底導電層114覆蓋住該些插柱106與晶片底面110b，其後可能需以清潔步驟清理。底導電層114材質可為金屬如銅或銅合金，亦或其他材質。此實施例中，晶片110之接觸墊109可為銅墊，其厚度需足夠進行清潔與金屬化步驟。
如圖3H，圖案化底導電層114而形成電性連接至該些柱106的底內連線圖案114a以及底導線圖案114b。上下表面上的導電層112、114可以利用雙面製程同時圖案化，或依序分兩次進行。導線圖案112b與底導線圖案114b可以相同或不同，端視產品設計。而內連線圖案112a與底內連線圖案114a之位置乃對應於該些柱106之位置。不過，視所搭配之晶片或元件，該些圖案之設計或排列均可調整。
之後，在前述上下金屬圖案112/114上，可形成抗鏽層或表面加工層，例如是鎳/金疊層、有機保焊劑(organic solderability preservatives,OSP)，或者材質可為化學鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)或化學鎳金(electroless nickel immersion gold,ENIG)，以幫助增加連結。亦可選擇性地形成保護層如防焊層以保護前述上下金屬圖案，而僅有預定的接觸墊露出以承載錫球。
雖然根據前述實施例描述，該些柱可於單一步驟中圖案電鍍於銅箔上。薄箔可以是面板(四方)矩陣格式。一實施例中，可一次電鍍兩三片晶圓再轉至適當載體。顯示面板乃數倍大於印刷電路板，該些板材可承載晶圓，顯著增加插柱電鍍效率。若以面板格式電鍍，單一載體可承載兩薄箔而同時電鍍兩薄箔，改善製造效能。
在上述依序形成該些插柱106與導電層112之過程中，該些插柱之高度乃依設計需求為適當合理高度，不暴露出晶片110或封裝膠體130，特別是電鍍過程中不將該些元件暴露於電鍍化學反應中以避免該些元件被攻擊。
圖4A-4G是依照本發明之另一實施例的一種晶圓級封裝結構製造方法的剖面示意圖。如圖4A，先提供一犧牲層100，犧牲層100上表面上具有膠帶102而膠帶102上又具有至少一晶片110。形成光阻層104於該晶片110與膠帶102上之後，在膠帶102及光阻層104中形成多個開口S。開口S可利用前述實施例之技術所形成。一般而言，犧牲層100如前述實施例貼附至硬質載體100C上，但圖示中為描述方便忽略未繪示出硬質載體100C。
如圖4B，於多個開口S中形成多個插柱106並位於犧牲層100上。雖然圖示中該些插柱頂面106a實質上與晶片上表面110a齊平，但實際上該些插柱106可略高於或矮於晶片110。然後，移除光阻層104。
如圖4C，模封犧牲層100、膠帶102與其上之晶片110而形成一封裝膠體130覆蓋住晶片110、該些插柱106、膠帶102與犧牲層100。接著，於封裝膠體130中形成多個凹陷S1 ，透過移除一部份之封裝膠體130直至該些插柱106之上表面106a露出而得到凹陷S1 。移除過程可以包括進行前述實施例所述之技術。凹陷S1 可為具有單一一致直徑的開口，也可如圖所示開口形狀為錐狀的。
接著，如圖4D，形成一種層111於封裝膠體上表面上與凹陷S1 中並覆蓋插柱上表面106a。種層111可以濺鍍或其他製程製得，接著，於種層111上形成一導電層112並電性連接至該些柱106。導電層112共形覆蓋封裝膠體130，但導電層112完全填滿或部份填入凹陷S1 。既然凹陷S1 之深寬比較小，導電層112可完全填滿凹陷S1 。導電層112覆蓋凹陷S1 之側壁並電性連接至該些插柱106。
如圖4E，。蝕刻移除在底面之犧牲層100與一部份之該些插柱106，直到該些插柱底面106b實質上與晶片底面110b齊平。接著，移除膠帶102而暴露出該些插柱106與晶片110之接觸墊109。
如圖4F，形成一重佈線路層116覆蓋住該些插柱106底面106b與晶片底面110b。此處所述重佈線路層116乃為多層，包括一第一介電層113、一導電層114與一第二介電層115。導電層114夾在第一介電層113與第二介電層115之間。重佈線路層可幫助扇出晶片墊，以容納具微細墊間間距(fine pad pitch)之晶片，也可內連至某些插柱106。重佈線路層116之形成與標準晶圓級封裝製程或製程相關材料乃是相容的，而例示步驟描述於後。
一實施例中，於重組晶圓底面形成第一介電層113之後，於其中形成接觸窗圖案(via pattern)以連接插柱與晶片接觸墊，接著固化第一介電層113。介電層113可以旋塗或其他製程所形成。於介電層113上形成導電層114，圖案化底導電層114而形成底內連線圖案114a以及底導線圖案114b。底內連線圖案114a以及底導線圖案114b扇出晶片接觸墊109並且設計為內連接插柱106與晶片接觸墊109。
舉例而言，至少介電層113或115之一者材質可以是聚乙醯胺(polyimide)、聚苯並噁唑(polybenzoxazole)、苯並環丁烯(benzocyclobutene)、其組合或其他材質。介電層113或115可以相同或不同介電材料所形成。一實施例中，底導線圖案114b連接晶片接觸墊109。底內連線圖案114a可電性連接晶片接觸墊109與插柱106或僅連接插柱106。底內連線圖案114a可用以扇出晶片接觸墊109或用以幫助連接外部連結。
如圖4G，於第二介電層115之開口S2中形成電性接點(electrical contacts) 140，電性接點140電性連結至底內連線圖案114a。電性接點140可為例如錫球、金扣柱(gold stud)或銅柱或其他適當電性接點。此外，第二介電層115更可具有凸塊下金屬化層(under-bump metallization,UBM)以強化與電性接點之黏著。導電層112圖案化為連接至插柱106的內連線圖案112a與導線圖案112b。
圖5A-5G是依照本發明之另一實施例的一種晶圓級封裝結構製造方法的剖面示意圖。如圖5A，先提供一犧牲層100，犧牲層100上具有膠帶102而膠帶102上又具有至少一晶片110。一般而言，犧牲層100如前述實施例貼附至硬質載體100C上，但圖示中為描述方便忽略未繪示出硬質載體100C。
如圖5B，模封犧牲層100、膠帶102與其上之晶片110而形成一封裝膠體130覆蓋住晶片110、膠帶102與犧牲層100。
如圖5C，接著，於封裝膠體130中形成多個開口S，移除過程可以包括進行前述實施例所述之技術。開口S可為具有單一一致直徑的開口、漸縮形狀的開口或兩者組合。若開口S以雷射鑽孔形成，因封裝膠體130顆粒會阻礙雷射會使其表面132粗糙。粗糙表面比平滑表面難以電鍍。因此，較佳是先形成插柱106再形成封裝膠體130圍繞插柱106，如圖3A-3H與圖4A-4G所示。
如圖5D，形成一種層111於封裝膠體130上表面上與開口S中並覆蓋開口內表面。種層111可以前述實施例中任意相關製程製得，接著，於種層111上形成一導電層112。導電層112覆蓋封裝膠體130，但導電層112完全填滿或部份填入開口S。既然開口S之深寬比較小，導電層112可完全填滿開口S。導電層112填充於開口S內之部份可視為插柱部份T12c。導電層112較佳是完全覆蓋開口S之側壁與底部。此實施例中，單一形成導電層112之步驟取代了前述實施例中分開形成插柱106與導電層之步驟。
如圖5E，移除在底面之犧牲層100與一部份之插柱部份112c，直到插柱部份112c的底面113實質上與晶片底面110b齊平。該移除步驟可以前述實施例之技術進行。接著，移除膠帶102而暴露出插柱部份112c與晶片110之底面110b。
如圖5F，形成一底導電層114覆蓋住插柱部份112c與晶片110之底面110b。導電層112或底導電層114材質可包括前述實施例之金屬或其他材質。
如圖5G，圖案化導電層112為佈線或導線圖案112b與內連線圖案112a(包括插柱部份112c)。圖案化底導電層114而形成電性連接至插柱部份112c的底內連線圖案114a以及底導線圖案114b。
圖6A-6F是依照本發明之另一實施例的一種晶圓級封裝結構製造方法的剖面示意圖。如圖6A，先提供一犧牲層100，犧牲層100上具有多個插柱106，而犧牲層100透過膠帶102貼附至硬質載體100C上。部份移除犧牲層100而定義出一晶片安置區A，至少一晶片位於膠帶102上並位於晶片安置區A內。晶片安置區可利用選擇性蝕刻或其他製程製得。
如圖6B，模封犧牲層100與其上之晶片110而形成一封裝膠體130覆蓋住晶片110、該些插柱106與犧牲層100，並位於膠帶102之上。接著，於封裝膠體130中形成多個凹陷S1 ，透過移除一部份之封裝膠體130直至該些插柱106露出而得到凹陷S1 。凹陷S1 可為具有單一一致直徑的開口，也可如圖所示開口形狀為錐狀的。
接著，如圖6C，形成一種層111於封裝膠體上表面上與凹陷S1 中並覆蓋插柱上表面106a。接著，於種層111上形成一導電層112並電性連接至該些柱106。導電層112共形覆蓋封裝膠體130，但導電層112完全填滿或部份填入凹陷S1 。既然凹陷S1 之深寬比較小，導電層112可完全填滿凹陷S1 。導電層112覆蓋凹陷S1 之側壁並電性連接至該些插柱106。
如圖6D，移除硬質載體100C與膠帶102。移除在底面之犧牲層100與一部份之該些插柱106。移除步驟可以前述技術進行。因犧牲層100相當薄，可忽視晶片底面110b與封裝膠體130底面之高度差不計。晶片底面110b與封裝膠體130底面之高度差異繪示與實際比例不同。
如圖6E，形成一底導電層114覆蓋住插柱106與晶片110之底面110b。
如圖6F，圖案化導電層112為佈線或導線圖案112b與連接插柱106的內連線圖案112a。圖案化底導電層114而形成電性連接至插柱106的底內連線圖案114a以及底導線圖案114b。
圖7A-7F是依照本發明之另一實施例的一種晶圓級封裝結構製造方法的剖面示意圖。如圖7A，先提供一犧牲層100，犧牲層100上具有多個插柱106，而犧牲層100與該些插柱106位於膠帶102上。部份移除犧牲層100而定義出一晶片安置區A，至少一晶片位於膠帶102上並位於晶片安置區A內。晶片安置區可利用選擇性蝕刻或其他製程製得。該些插柱106之頂面106a高於晶片110之頂面110a。一般而言，犧牲層100貼附於硬質載體100C，但圖示描述中省略。
如圖7B，模封犧牲層100與其上之晶片110而形成一封裝膠體130覆蓋住晶片110、該些插柱106與犧牲層100，並位於膠帶102之上。
如圖7C，接著，從上面移除封裝膠體130之部份薄化封裝膠體130，直至該些插柱106之表面106a露出。該移除步驟可包括研磨或其他步驟。此實施例中之插柱106可視為貫穿封裝膠體之插塞。薄化之封裝膠體130a之厚度乃厚於晶片，方能提供晶粒與後續形成導線圖案間之背面絕緣。
如圖7D，移除膠帶102而露出犧牲層100。移除在底面之犧牲層100，移除步驟可以前述技術進行。分別形成導電層112、114覆蓋薄化之封裝膠體130a的頂面、底面。
如圖7E，圖案化導電層112為佈線或導線圖案112b與連接插柱106的內連線圖案112a。圖案化底導電層114而形成電性連接至插柱106的底內連線圖案114a以及底導線圖案114b。。
之後，在前述上下金屬圖案112/114上，可形成抗鏽層或表面加工層，例如是鎳/金疊層、有機保焊劑(OSP)，或者材質可為化學鎳鈀浸金(ENEPIG)或化學鎳金(ENIG)，以幫助增加連結。亦可選擇性地形成防焊層以保護前述上下金屬圖案。
另一實施例中，類似圖7C中薄化封裝膠體130之步驟可持續進行直到晶片110背面與插柱106上部從薄化的封裝膠體130a暴露出來。可額外形成一介電覆蓋層(未繪示)於封裝膠體130a上與晶片110背面上，但不覆蓋插柱106，然後再形成導電層112於介電覆蓋層與該些插柱106上。
其他實施例中，可使用多層重佈線路層來取代前述實施例之底面金屬圖案，以便將小間距晶片墊扇出或重佈高密度導線線路。
由前述實施例可知，晶圓級封裝結構可提供安裝於其上的元件或下一級基板直接電性連結。亦即，本發明的晶圓級封裝結構可直接電性連結安裝於其兩面之元件。因此，本案之晶圓級封裝結構適合用於立體晶圓級封裝，而堆疊封裝尺寸頗小。本發明的晶圓級封裝結構可在雙面設置重佈線路圖案，以堆疊不同種類或尺寸封裝結構，提供產品設計彈性。
本案實施例中電鍍該些插柱106之電鍍製程可有效調整最佳化電鍍化學反應與配方程式，以電鍍形成該些柱106而不電鍍封裝膠體130上表面/種層111。另一方面，貫穿膠體之接觸窗電鍍較為複雜，因電鍍多會發生於接觸窗孔，但少數電鍍仍會發生於封裝膠體130上表面/種層111。因此，此種電鍍所應用之電鍍化學反應與配方程式亦不相同。電鍍表面可能需要平坦化以便移除過度電鍍區域，亦即不均勻處。此一步驟可能會導致插柱106缺陷，例如電鍍包含物或空隙之產生。
前述實施例中重佈線路層僅設置於封裝結構底側(晶片側)，但重佈線路層可以設置於封裝結構兩面以達到最高導線密度解析度。此外，雖然只顯示單一層之重佈線路層，但不同實施例中可視設計使用多層重佈線路層。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、22、24、26．．．封裝結構
20a、20b、20c．．．電子元件
100．．．犧牲層
102．．．膠帶
106．．．插柱
109．．．接觸墊
110．．．晶片
112a．．．內連線圖案
112b．．．導線圖案
113、115．．．介電層
112、114．．．導電層
114a‧‧‧底內連線圖案
114b‧‧‧底導線圖案
116‧‧‧重佈線路層
130、130a‧‧‧封裝膠體
106a、110a‧‧‧上表面
106b、110b、130b‧‧‧下表面
140‧‧‧電性接點
240‧‧‧接點
S‧‧‧開口
S1 ‧‧‧凹陷
A‧‧‧晶片設置區
圖1是依照本發明之一實施例的一種晶圓級封裝結構剖面示意圖。
圖2A是依照本發明之一實施例的一種堆疊封裝結構剖面示意圖。
圖2B是依照本發明之另一實施例的一種堆疊封裝結構剖面示意圖。
圖3A-3H是依照本發明之一實施例的一種堆疊晶圓級封裝結構製造方法的剖面示意圖。
圖4A-4G是依照本發明之另一實施例的一種堆疊晶圓級封裝結構製造方法的剖面示意圖。
圖5A-5G是依照本發明之另一實施例的一種堆疊晶圓級封裝結構製造方法的剖面示意圖。
圖6A-6F是依照本發明之又一實施例的一種堆疊晶圓級封裝結構製造方法的剖面示意圖。
圖7A-7E是依照本發明之又一實施例的一種堆疊晶圓級封裝結構製造方法的剖面示意圖。
10．．．封裝結構
106．．．插柱
109．．．接觸墊
110．．．晶片
111．．．種層
112a．．．內連線圖案
112b．．．導線圖案
113、115．．．介電層
114．．．金屬層
114a．．．底內連線圖案
114b．．．底導線圖案
116．．．重佈線路層
130．．．封裝膠體
140．．．電性接點

Claims (19)

  1. 一種半導體元件封裝結構，包含：一晶片，其具有一主動表面；一封裝膠體，部份包覆該晶片且具有一上表面；一重佈線路層，包括至少一導電層與至少一介電層，其中該重佈線路層部份形成於該主動表面與部份形成於該封裝膠體的一下表面；複數個導電柱位於該封裝膠體內並電性連接至該重佈線路層；複數個凹陷，位於該封裝膠體的該上表面，其中該些凹陷之位置對應於該些導電柱之位置，該封裝膠體疊蓋住該些導電柱之上表面的邊緣；以及複數個內連線圖案，電性連接至該些導電柱，而該些內連線圖案中之至少一個延伸至該些凹陷中之至少一個。
  2. 如申請專利範圍第1項所述之半導體元件封裝結構，更包括一種層位於該封裝膠體與該些內連線圖案之間。
  3. 如申請專利範圍第1項所述之半導體元件封裝結構，其中該些凹陷為錐狀。
  4. 如申請專利範圍第3項所述之半導體元件封裝結構，其中該些凹陷在遠離該些導電柱之位置之直徑大於鄰近該些導電柱之位置之直徑。
  5. 如申請專利範圍第1項所述之半導體元件封裝結構，其中該重佈線路層包括一導電層介於一上介電層與一下介電層之間。
  6. 如申請專利範圍第1項所述之半導體元件封裝結構，其中該半導體元件封裝結構為一第一半導體元件封裝結構，更包括一第二半導體元件封裝結構堆疊於該第一半導體元件封裝結構上。
  7. 一種半導體元件封裝結構，包含：一晶片，其具有一主動表面；一封裝膠體，部份包覆該晶片且具有一上表面；一重佈線路層，包括至少一導電層與至少一介電層，其中該重佈線路層部份形成於該主動表面與部份形成於該封裝膠體的一下表面；複數個導電柱位於該封裝膠體內並電性連接至該重佈線路層；以及複數個凹陷，位於該封裝膠體的該上表面，其中該些凹陷之位置對應於該些導電柱之位置，且暴露出至少該些導電柱之上表面的至少一部份，其中該封裝膠體疊蓋住該些導電柱之上表面的邊緣。
  8. 如申請專利範圍第7項所述之半導體元件封裝結構，更包括複數個內連線圖案位於該封裝膠體與該些導電柱上，該些內連線圖案至少部份填入該封裝膠體之該些凹陷。
  9. 如申請專利範圍第8項所述之半導體元件封裝結構，更包括一種層位於該封裝膠體與該些內連線圖案之間。
  10. 如申請專利範圍第7項所述之半導體元件封裝結構，其中該些凹陷為錐狀。
  11. 如申請專利範圍第10項所述之半導體元件封裝結構，其中該些凹陷在遠離該些導電柱之位置之直徑大於鄰近該些導電柱之位置之直徑。
  12. 如申請專利範圍第7項所述之半導體元件封裝結構，其中該重佈線路層包括一導電層介於一上介電層與一下介電層之間。
  13. 如申請專利範圍第7項所述之半導體元件封裝結構，其中該半導體元件封裝結構為一第一半導體元件封裝結構，更包括一第二半導體元件封裝結構堆疊於該第一半導體元件封裝結構上。
  14. 一種半導體元件封裝結構製造方法，包含：形成複數個導電柱位於一犧牲層上；安置至少一晶片於該犧牲層上；形成一封裝膠體於該犧牲層上，包覆該至少晶片並至少部份包覆該些導電柱；形成複數個凹陷於該封裝膠體中鄰近該些導電柱之上表面，其中該些凹陷暴露出至少該些導電柱之上表面的至少一部份，該封裝膠體疊蓋住該些導電柱之上表面的邊緣；形成複數個內連線圖案於該封裝膠體與該些導電柱上，該些內連線圖案至少部份填入該封裝膠體內的該些凹陷；移除該犧牲層；以及形成一重佈線路層於該晶片、該些導電柱與該封裝膠 體上，該重佈線路層包括至少一導電層與至少一介電層。
  15. 如申請專利範圍第14項所述之半導體元件封裝結構製造方法，其中形成該些凹陷之步驟更包括進行一雷射鑽孔製程。
  16. 如申請專利範圍第14項所述之半導體元件封裝結構製造方法，更包括形成一種層於該封裝膠體之上，位於該封裝膠體與該些內連線圖案之間並至少部份填入於該些凹陷且覆蓋該些導電柱的該上表面。
  17. 如申請專利範圍第14項所述之半導體元件封裝結構製造方法，其中該些凹陷為錐狀。
  18. 如申請專利範圍第17項所述之半導體元件封裝結構製造方法，其中該些凹陷在遠離該些導電柱之位置之直徑大於鄰近該些導電柱之位置之直徑。
  19. 如申請專利範圍第14項所述之半導體元件封裝結構製造方法，其中該重佈線路層包括一導電層夾於一上介電層與一下介電層之間。
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