CN103187379B - 半导体堆栈结构及其制法 - Google Patents

半导体堆栈结构及其制法 Download PDF

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CN103187379B
CN103187379B CN201210589731.5A CN201210589731A CN103187379B CN 103187379 B CN103187379 B CN 103187379B CN 201210589731 A CN201210589731 A CN 201210589731A CN 103187379 B CN103187379 B CN 103187379B
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chip
wafer
making
semiconductor stack
bearing part
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CN103187379A (zh
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何彦仕
关欣
尤龙生
刘沧宇
郑家明
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XinTec Inc
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XinTec Inc
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Abstract

一种半导体堆栈结构及其制法，该半导体堆栈结构的制法通过将一规格的晶圆进行切割以形成多个芯片，再将各该芯片重新排设呈现另一规格的晶圆样式，以通过坝块堆栈于所需的基板上，再于芯片上进行线路重布层的制程，最后，进行切割以形成多个该半导体堆栈结构。

Description

半导体堆栈结构及其制法
技术领域
本发明涉及一种半导体堆栈结构及其制法，尤指一种将不同规格的晶圆相堆栈的半导体堆栈结构及其制法。
背景技术
随着电子产业的蓬勃发展，半导体平面封装相关技术到达极限，可通过集成化满足微小化的需求。堆栈晶圆的技术为新发展的领域，对未来科技有很大的助力，目前，是朝将多个同质或异质的晶圆堆栈作发展，以达多功能的目的。
一般晶圆封装厂的设备中，一套制程设备仅限于加工一种规格的晶圆，若要加工其它规格的晶圆，则需重新增设另一套制程设备。例如：8寸晶圆厂的设备用于加工8寸晶圆，12寸晶圆厂的设备用于加工12寸晶圆。而随着科技发展迅速，新发展的电子产品需要新设计的芯片，所以芯片加工厂需新盖厂房或新增设备，以因应新电子产品的需求。
然而，以目前电子产品的竞争现况，芯片加工厂新盖厂房或新增设备的速度无法配合电子产品的汰换速度，也就是说芯片加工厂难以实时供应所需的芯片封装件。
因此，如何满足晶圆加工对电子产品的需求量，实已成目前亟欲解决的课题。
发明内容
为克服上述现有技术的问题，本发明的主要目的在于提供一种半导体堆栈结构及其制法，可实时供应所需的芯片封装件，以配合电子产品的汰换速度。 
本发明的半导体堆栈结构的制法，先将晶圆进行切割以形成多个芯片，再将各该芯片重新排设以配合所需的基板规格；接着，提供表面具有多个坝块的一基板，以通过各该坝块，使各该芯片结合于该基板上；再于芯片上进行线路重布层(Redistribution Layer,RDL)的制程；最后，进行切割以形成多个该半导体堆栈结构。
前述的制法中，可于承载件上进行重新排设，且该承载件上设有多个定位部，可令所述定位部对应位于各该芯片之间，使各该芯片之间具有间距。
前述的制法中，可于切割该晶圆前，先研磨该晶圆。
本发明还提供一种半导体堆栈结构，包括：芯片、以及通过坝块可对应结合该芯片的基板。该芯片的表面具有线路重布层，且该芯片的侧面上具有隔离层，又该芯片的表面与该线路重布层上形成有保护层。
前述的结构中，该隔离层还可形成于该芯片与该线路重布层之间。
前述的结构及其制法中，该基板可为硅基板或玻璃板。
由上可知，本发明的半导体堆栈结构及其制法，主要通过现有设备将一新规格的晶圆切割为多个芯片，再将各该芯片经重新排设成现有规格的晶圆样式，以堆栈于现有规格的基板，所以可使用现有设备进行后续制程。因此，对于新规格的晶圆，本发明的制法使用现有设备加工，而无需新盖厂房或新增设备，所以可实时供应所需的芯片封装件，以配合电子产品的汰换速度。 
附图说明
图1A至图1G为本发明半导体堆栈结构的制法的剖面示意 图；以及
图2A至图2G为本发明半导体堆栈结构的制法的剖面示意图。
附图中符号的简单说明如下：
1、2：半导体堆栈结构；1a、2a：晶圆；10、20：芯片；10a、20a：第一表面；10b、20b：第二表面；10c、20c：侧面；100、200：电性接触垫；101、201：盲孔；11、21：基板；110、210：坝块；12、22：隔离层；13、23：线路重布层；130、230：导电盲孔；14、24：保护层；3：第一承载件；30：粘着层；4：第二承载件；40、40’：定位部；D：间距。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容能涵盖的范围内。同时，本说明书中所引用的如“一”、“上”、“侧”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
在本发明中，晶圆经堆栈、封装、切单后所形成的半导体封装件可应用于，例如各种微机电系统(Micro Electro  Mechanical System;MEMS)，尤其是或利用电性或电容变化来测量的影像传感器。特别是可选择使用晶圆级封装(wafer scale package;WSP)制程对影像感测组件、射频组件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)或压力传感器(process sensors)等半导体封装件。
请参阅图1A至图1G，为本发明的半导体堆栈结构1的制法的第一实施例。
如图1A所示，提供一具有相对的第一表面10a与第二表面10b的晶圆1a，该晶圆1a的第一表面10a具有多个电性接触垫100。于本实施例中，该晶圆1a为12寸。
接着，将该晶圆1a的第一表面10a设置于一第一承载件3上。于本实施例中，该第一承载件3为玻璃板，且该第一承载件3通过粘着层30结合于该晶圆1a的第一表面10a上。
如图1B所示，研磨该晶圆1a的第二表面10b，以减小该晶圆1a的厚度，而达到薄化的需求。
如图1C所示，形成多个盲孔101于该晶圆1a的第二表面10b上，以令所述电性接触垫100对应外露于各该盲孔101。
如图1D所示，于该晶圆1a的第二表面10b上进行切割，以形成多个芯片10，且该芯片10具有相邻该第一表面10a与第二表面10b的侧面10c。
如图1E所示，将各该芯片10由该第一承载件3移至一具有多个定位部40的第二承载件4上，且该芯片10的第二表面10b设置于该第二承载件4上，以外露该芯片10的第一表面10a，并令所述定位部40对应位于各该芯片10之间，使各该芯片10之间具有间距D。
于本实施例中，该第二承载件4为散热胶带、硅板或玻璃板，且该定位部40为该第二承载件4上的凸状；详细地，该定位部40 与该第二承载件4为一体、或接置于该第二承载件4上。
通过所述定位部40，使12寸晶圆1a所切割出的芯片10重新排设为对应8寸晶圆的样式，即各该芯片10之间的间距D等同于8寸晶圆切割后各芯片间的间距。
如图1F所示，提供表面具有多个坝块110的一基板11，以将各该电性接触垫100对应各该坝块110，使各该芯片10的第一表面10a结合于该基板11上。于本实施例中，该基板11为硅基板或玻璃板。再者，该坝块110依制程或结构的需求，可部分结合该电性接触垫100、完全不接触该电性接触垫100、或完全接触该电性接触垫100。
接着，移除该第二承载件4及所述定位部40，再形成隔离层12于各该芯片10的第二表面10b、盲孔101的孔壁与各该芯片10的侧面10c上，且该电性接触垫100外露出该盲孔101。
接着，形成线路重布层13于各该芯片10的第二表面10b上的部分隔离层12上，且形成导电盲孔130于该盲孔101中，以借该导电盲孔130电性连接该线路重布层13与该电性接触垫100。
接着，形成保护层14于各该芯片10的第二表面10b上的隔离层12与该线路重布层13上。
如图1G所示，沿各该芯片10之间的间距D切割该基板11，以形成多个该半导体堆栈结构1。
于其它实施例中，依设计式样，于切割该基板11时，可一并切割该坝块110。
本发明半导体堆栈结构的制法中，可通过8寸晶圆厂的设备将12寸晶圆1a切割为多个芯片10，再将各该芯片10经该第二承载件4及所述定位部40重新排设成8寸晶圆的样式，以堆栈于8寸晶圆所对应的基板11上，所以对于12寸晶圆1a而言，本发明的制法可使用现有8寸晶圆厂的设备进行加工，而无需新盖厂房 或新增设备。
请参阅图2A至图2G，为本发明的半导体堆栈结构2的制法的第二实施例。本实施例与第一实施例的差异在于形成盲孔的步骤顺序，其它相关制程均大致相同，所以相同的处不加以详述。
如图2A所示，提供一具有相对的第一表面20a与第二表面20b的晶圆2a，该晶圆2a的第一表面20a具有多个电性接触垫200。
接着，经研磨该晶圆2a的第二表面20b，再将该晶圆2a切割成多个芯片20，且该芯片具有相邻该第一表面20a与第二表面20b的侧面20c。
如图2B所示，将各该芯片20设置于一具有多个定位部40’的第二承载件4上，且该芯片20的第二表面20b设置于该第二承载件4上，以外露该芯片20的第一表面20a，并令所述定位部40’对应位于各该芯片20之间，使各该芯片20之间具有间距D。
于本实施例中，该第二承载件4为散热胶带，该定位部40’为叠于该散热胶带上的网版，以将各该芯片20置于该网版的开口中。
如图2C所示，提供表面具有多个坝块210的一基板21，以将各该电性接触垫200结合于各该坝块210，使各该芯片20的第一表面20a结合于该基板21上。
如图2D所示，移除该第二承载件4及所述定位部40’。接着，形成多个盲孔201于各该芯片20的第二表面20b上，以令所述电性接触垫200对应外露出各该盲孔201。
如图2E所示，形成隔离层22于各该芯片20的第二表面20b、盲孔201的孔壁与各该芯片20的侧面20c上，且该电性接触垫200外露出该盲孔201。
如图2F所示，形成线路重布层23于各该芯片20的第二表面20b上的部分隔离层22上，且形成导电盲孔230于该盲孔201中，以借该导电盲孔230电性连接该线路重布层23与该电性接触垫200。
如图2F所示，形成保护层24于各该芯片20的第二表面20b上的隔离层22与该线路重布层23上。
如图2G所示，沿各该芯片20之间的间距D切割该基板21与该坝块210，以形成多个该半导体堆栈结构2。
本发明还提供一种半导体堆栈结构1,2，包括：具有相对的第一表面10a,20a、第二表面10b,20b及相邻该第一表面10a,20a与第二表面10b,20b的侧面10c,20c的芯片10,20、形成于该芯片10,20的第二表面10b,20b上的保护层14,24、以及结合于该芯片10,20的第一表面10a,20a上的基板11,21。
所述的芯片10,20的第一表面10a,20a具有多个电性接触垫100,200，且其第二表面10b,20b上具有线路重布层13,23，而其侧面10c,20c上具有隔离层12,22以防止该芯片10,20受损，又该芯片10,20中具有导电盲孔130,230以电性连接该线路重布层13,23与该电性接触垫100,200。另外，该隔离层12,22还形成于该芯片10,20的第二表面10b,20b与该线路重布层13,23之间、及该导电盲孔130,230的孔壁上。 
所述的保护层14,24还形成于该线路重布层13,23上。
所述的基板11,21为硅基板或玻璃板，其表面具有多个坝块110,210以结合该电性接触垫100,200，使该芯片10,20的第一表面10a,20a结合于该基板11,21上。
综上所述，本发明的半导体堆栈结构及其制法，通过现有设备加工新规格的晶圆，因而针对新规格的晶圆无需新盖厂房或新增设备，不仅降低成本，且可实时供应所需的芯片封装件， 以达到提升生产力的目的。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (16)

1.一种半导体堆栈结构的制法，其特征在于，包括：
提供一具有相对的第一表面与第二表面的晶圆，该晶圆的第一表面具有多个电性接触垫；
将该晶圆通过该晶圆的第一表面设置于一第一承载件上；
形成多个盲孔于该晶圆的第二表面上，以令所述电性接触垫对应外露出各该盲孔；
由该晶圆的第二表面切割该晶圆，以形成多个芯片；
将各该芯片由该第一承载件移至一设有多个定位部的第二承载件上，且该芯片的第二表面设置于该第二承载件上，以外露该芯片的第一表面，并令所述定位部对应位于各该芯片之间，使各该芯片之间具有间距；
提供表面具有多个坝块的基板，以将各该芯片第一表面上的电性接触垫对应各该坝块，使各该芯片的第一表面结合于该基板上；
移除该第二承载件及所述定位部；
形成隔离层于各该芯片的第二表面、盲孔的孔壁与各该芯片的侧面上，且该电性接触垫外露出该盲孔；
形成线路重布层于各该芯片的第二表面上的部分隔离层上，且形成导电盲孔于该盲孔中，以通过该导电盲孔电性连接该线路重布层与该电性接触垫；
形成保护层于各该芯片的第二表面上的隔离层与该线路重布层上；以及
沿各该芯片之间的间距切割该基板，以形成多个该半导体堆栈结构。
2.根据权利要求1所述的半导体堆栈结构的制法，其特征在于，该第一承载件为玻璃板。
3.根据权利要求1所述的半导体堆栈结构的制法，其特征在于中，该第一承载件通过粘着层结合于该晶圆的第一表面上。
4.根据权利要求1所述的半导体堆栈结构的制法，其特征在于，该第二承载件为散热胶带、硅板或玻璃板。
5.根据权利要求1所述的半导体堆栈结构的制法，其特征在于，该定位部为网版或该第二承载件上的凸状。
6.根据权利要求1所述的半导体堆栈结构的制法，其特征在于，该基板为硅基板或玻璃板。
7.根据权利要求1所述的半导体堆栈结构的制法，其特征在于，该制法还包括形成该盲孔之前，研磨该晶圆的第二表面。
8.根据权利要求1所述的半导体堆栈结构的制法，其特征在于，该制法还包括切割该基板时，一并切割该坝块。
9.一种半导体堆栈结构的制法，其特征在于，包括：
提供一具有相对的第一表面与第二表面的晶圆，该晶圆的第一表面具有多个电性接触垫；
将该晶圆通过该晶圆的第一表面设置于一第一承载件上；
由该晶圆的第二表面切割该晶圆，以形成多个芯片；
将各该芯片由该第一承载件移至一设有多个定位部的第二承载件上，且该芯片的第二表面设置于该第二承载件上，以外露该芯片的第一表面，并令所述定位部对应位于各该芯片之间，使各该芯片之间具有间距；
提供表面具有多个坝块的基板，以将各该芯片第一表面上的电性接触垫对应各该坝块，使各该芯片的第一表面结合于该基板上；
移除该第二承载件及所述定位部；
形成多个盲孔于各该芯片的第二表面上，以令所述电性接触垫对应外露出各该盲孔；
形成隔离层于各该芯片的第二表面、盲孔的孔壁与各该芯片的侧面上，且该电性接触垫外露出该盲孔；
形成线路重布层于各该芯片的第二表面上的部分隔离层上，且形成导电盲孔于该盲孔中，以通过该导电盲孔电性连接该线路重布层与该电性接触垫；
形成保护层于各该芯片的第二表面上的隔离层与该线路重布层上；以及
沿各该芯片之间的间距切割该基板，以形成多个该半导体堆栈结构。
10.根据权利要求9所述的半导体堆栈结构的制法，其特征在于，该第一承载件为玻璃板。
11.根据权利要求9所述的半导体堆栈结构的制法，其特征在于，该第一承载件通过粘着层结合于该晶圆的第一表面上。
12.根据权利要求9所述的半导体堆栈结构的制法，其特征在于，该第二承载件为散热胶带、硅板或玻璃板。
13.根据权利要求9所述的半导体堆栈结构的制法，其特征在于，该定位部为网版或该第二承载件上的凸状。
14.根据权利要求9所述的半导体堆栈结构的制法，其特征在于，该基板为硅基板或玻璃板。
15.根据权利要求9所述的半导体堆栈结构的制法，其特征在于，该制法还包括于将该晶圆设置于该第一承载件上之前，研磨该晶圆的第二表面。
16.根据权利要求9所述的半导体堆栈结构的制法，其特征在于，该制法还包括切割该基板时，一并切割该坝块。
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