CN1095197C - 半导体晶片 - Google Patents
半导体晶片 Download PDFInfo
- Publication number
- CN1095197C CN1095197C CN96121405A CN96121405A CN1095197C CN 1095197 C CN1095197 C CN 1095197C CN 96121405 A CN96121405 A CN 96121405A CN 96121405 A CN96121405 A CN 96121405A CN 1095197 C CN1095197 C CN 1095197C
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- semiconductor integrated
- solder joint
- semiconductor
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Dicing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
可防止半导体集成电路中焊点腐蚀的半导体晶片。沿切割线将带有半导体集成电路和从半导体集成电路上的引线焊点延伸到切割线的互连的半导体晶片切割成芯片。部分互连以测片焊点残留部分的形式留在芯片上,并用绝缘膜覆盖测片焊点残留部分的表面。这就防止了水之类从测片焊点残留部分侵入,从而防止了半导体集成电路中引线焊点的腐蚀,进而提高了半导体器件产品的可靠性和寿命。
Description
本发明涉及到半导体晶片,确切地说是涉及到带有从半导体器件焊点伸延到切割线的互连的半导体晶片。
图16顶视图示出了一个常规半导体晶片。采用加于半导体集成电路1a中引线焊点2上的晶片测试探针4来进行晶片的测试。图17是图16所示半导体晶片1的剖面图。参照图18,在完成晶片测试之后,沿切割线6将晶片切割,使半导体集成电路1a分割成芯片。图19和20分别对应于图17和图18,示出了使用绝缘膜9来保护半导体集成电路1a上的有源区。在将半导体集成电路1a分割成芯片之后,制作了连接于半导体集成电路1a的引线焊点2的引线(未示出)。
当晶片测试探针4同引线焊点2相接触时,使引线焊点2出现损伤5。为了减小半导体集成电路1a的尺寸并提高半导体集成电路1a中有源区的比率,最近已使引线焊点2越来越小型化。因此,由于半导体集成电路1a的小型化,引线就有可能连接到引线焊点2的损伤5处,这就会引起引线焊点2和引线之间的不良连接。
图21示出了用来防止劣质连接的常规半导体晶片1的剖面。晶片的测试采用只加到切割线6中的晶片测试焊点3上的晶片测试探针4来进行。参照图22,在完成晶片测试之后,沿切割线6来切割晶片,从而将半导体集成电路1a分割成芯片。图23和24分别对应于图21和22,示出了使用绝缘膜9来保护半导体集成电路1a上的有源区。
但是,如图22所示,晶片测试焊点残留部分3a的表面和切割区被暴露出来。这就引起诸如水、钾、镁之类对铝(Al)有腐蚀作用的物质从晶片测试焊点残留部分3a侵入引线焊点2而引起引线焊点2的铝腐蚀的问题。
本发明的目的就是提供一种可防止半导体集成电路中焊点腐蚀的半导体晶片,进而提高了半导体器件产品的可靠性和寿命。
根据本发明的第一种情况,一种具有集成电路的半导体晶片,它包含:半导体晶片;半导体晶片上的至少一个半导体集成电路制作区,包括带有第一焊点的半导体集成电路;半导体晶片上的切割区,包围所述至少一个半导体集成电路制作区,用来将半导体晶片切割成具有半导体集成电路的芯片;位于半导体晶片上的切割区中的第二焊点;以及半导体晶片上的至少一个铝互连,电连接第一焊点和第二焊点并具有弯曲的形状以防止第一焊点的腐蚀,互连在半导体集成电路形成区中具有多个U形弯曲,各U形弯曲连接铝互连中两个通常平行的部分。
根据本发明的第二种情况,第二焊点的面积最好大于第一焊点的面积。
根据本发明的第三种情况,半导体晶片最好具有多个包围至少一个半导体集成电路形成区的第二焊点,使得相邻第二焊点之间的区域小于第二焊点,从而至少一个半导体集成电路制作区附近的切割区中无法设置额外的第二焊点。
根据本发明的第四种情况,至少一个半导体集成电路制作区包含第一和第二半导体集成电路制作区,且至少一个铝互连包括第一和第二铝互连。
根据本发明的第一种情况,当半导体集成电路分割成芯片时,弯曲防止了水之类从互连的侵入,从而防止了第一焊点的腐蚀,改善了半导体器件产品的可靠性和寿命。
根据本发明的第二种情况,大面积的第二焊点增加了晶片测试中探针与第二焊点接触时的可允许位置偏离,从而使测片工艺易于进行。
本发明的第三种情况可使半导体集成电路制作区周围的切割区得到有效利用。
本发明的第四种情况可使切割区小型化,导致半导体器件成品率的提高。
本发明已被用来解决上述问题,其目标是获得可防止半导体集成电路中焊点腐蚀的半导体晶片和半导体器件以及制造半导体器件的方法。
结合附图,从本发明的下列详细描述中,本发明的这些和其它的目的、特点、情况和优点将变得更为明显。
图1顶视图示出了本发明第一最佳实施例的半导体器件的制造方法。
图2剖面图示出了本发明第一最佳实施例的半导体器件的制造方法。
图3剖面图示出了本发明第一最佳实施例的半导体器件的制造方法。
图4顶视图示出了本发明第一最佳实施例的半导体器件的制造方法。
图5剖面图示出了本发明第一最佳实施例的半导体器件的制造方法。
图6顶视图示出了本发明第一最佳实施例的半导体器件的制造方法。
图7剖面图示出了本发明第一最佳实施例的半导体器件。
图8顶视图示出了本发明第二最佳实施例的半导体晶片。
图9顶视图示出了本发明第三最佳实施例的半导体晶片。
图10顶视图示出了本发明第四最佳实施例的半导体晶片。
图11顶视图示出了本发明第四最佳实施例的半导体晶片。
图12顶视图示出了本发明第四最佳实施例的半导体晶片。
图13顶视图示出了本发明第四最佳实施例的半导体晶片。
图14顶视图示出了本发明第四最佳实施例的半导体晶片。
图15顶视图示出了本发明第四最佳实施例的半导体晶片。
图16顶视图示出了常规半导体晶片。
图17是图16的剖面图。
图18剖面图示出了常规半导体器件。
图19是常规半导体晶片的剖面图。
图20是常规半导体器件的剖面图。
图21是常规半导体晶片的剖面图。
图22是常规半导体器件的剖面图。
图23是常规半导体晶片的剖面图。
图24是常规半导体器件的剖面图。
第一最佳实施例
图1-7示出了根据本发明第一最佳实施例的半导体器件制造方法。首先参照图1,制备了半导体晶片1。半导体集成电路1a制作在半导体晶片1上的集成电路制作区上。切割线6即切割区将半导体集成电路制作区分割开来。引线焊点2制作在半导体集成电路1a上。引线焊点2延伸至切割线6上,切割线6上的引线焊点2用作测片焊点3,且引线焊点2和测片焊点3被电连接。这就是说,在切割线6上的引线焊点2用作测片焊点3,而引线焊点2中从半导体集成电路1a延伸到切割线6的部位用作电连接引线焊点2和测片焊点3的互连。图2示出了图1的剖面。
对此半导体晶片1进行了晶片测试。在晶片测试中,测片探针4同测片焊点3接触以进行导电测试。测片探针4不与半导体集成电路1a上的引线焊点2相接触。因此,对半导体集成电路1a上的引线焊点2不引起损伤。
然后照参照图3,用激光8在半导体集成电路制作区和切割线6即切割区之间的边界中制作沟槽8a(预切工序)。沟槽8a从测片焊点3的表面延伸到其背面切开作为互连的测片焊点3。这一切割不从半导体集成电路1a的表面穿透到背面(即不切入芯片)。测片焊点3的一部分以测片焊点残留部分3a的形式留在半导体集成电路制作区上。图4示出了图3的上表面。
然后参照图5,在沟槽8a中制作覆盖测片焊点3的切割部位的绝缘膜9(绝缘膜制作工序)。绝缘膜9是制作在除引线焊点2之外的半导体集成电路制作区上和切割区上的钝化膜、聚酰亚胺膜之类。图6示出了图5的上表面。
然后参照图7,沿切割线6将大量半导体集成电路1a切成芯片(最终切割工序)。此半导体集成电路1a带有覆盖测片焊点3的绝缘膜9。
在本最佳实施例中,绝缘膜9完全覆盖测片焊点残留部分3a(它是芯片分割之后留在芯片中的引线焊点2的残留部分),从而防止了潮气之类的侵入,从而防止了芯片中引线焊点2的腐蚀。这就提高了半导体器件产品的可靠性和寿命。
预切割工序、绝缘膜制作工序和最终切割工序可在制作图23所示的半导体晶片1之后进行。但此时,虽然在图23所示的半导体晶片1中制作了用来保护半导体集成电路1a上有源区的绝缘膜9,在绝缘膜制作工序中再次使用了绝缘膜9。因此,比起常规器件来,以降低生产成品率为条件,为了确保测片焊点3而要求掩膜设计和应用中有更高的精度。
同样,在图5所示的绝缘膜制作工序中,用绝缘膜9覆盖引线焊点2表面以外的半导体集成电路1a以及切割线6。另一方面,在图23中,除引线焊点2表面以外的半导体集成电路1a和部分切割线6被覆盖,而测片焊点3被暴露出来以便测片。因此,与图23相比,由于测片焊点3不暴露,图5对应用绝缘膜9的掩模设计和使用的精度要求较低。第二最佳实施例
图8示出了本发明第二最佳实施例的半导体晶片。在图8中,1表示半导体晶片,1a表示制作在半导体晶片1的半导体集成电路制作区上的半导体集成电路,2表示制作在半导体集成电路1a中的引线焊点,3表示测片焊点,4表示用于测片的测片探针,5表示测片焊点3上的损伤,6表示用来分割半导体集成电路制作区的切割线即切割区,7表示用来连接引线焊点2和测片焊点3的延伸铝互连。
半导体集成电路1a制作在半导体晶片1表面中的半导体集成电路制作区上。切割线6分割半导体集成电路制作区。大量的引线焊点2制作在半导体集成电路1a上。测片焊点3制作在切割线6上。延伸铝互连7对引线焊点2和测片焊点3进行电连接。延伸铝互连7的形状如图8所示且有呈锐角的类直线弯曲,且弯曲至少制作在半导体集成电路制作区上,在除引线焊点2以外的半导体集成电路制作区上和切割区上制作由钝化膜、聚酰亚胺膜之类组成的绝缘膜(未示出)。
对这种半导体晶片1进行测片。在测片过程中,用与测片焊点3相接触的测片探针4来进行导电测试。测片探针4不接触引线焊点2。因此在引线焊点2上不引起损伤。在测片之后,在半导体晶片1的表面上加绝缘膜9,使引线焊点2暴露出来。或者在半导体晶片1上加绝缘膜9,使引线焊点2和测片焊点3在测片之前暴露出来。随后沿切割线6切割半导体晶片1,使大量半导体集成电路1a分割成芯片。因此,水之类只从延伸铝互连7的剖面渗透。但弯曲抑制了其向延伸铝互连7的渗透,从而抑制了它向引线焊点2接近。
根据本最佳实施例,弯曲防止了水之类的侵入,从而防止了芯片中引线焊点2的腐蚀,这就提高了半导体器件产品的可靠性和寿命。
可以采用第一最佳实施例所述的预切割工序、绝缘膜制作工序和最终切割工序。此时,用绝缘膜9覆盖延伸铝互连7的剖面,进一步改善了半导体器件产品的可靠性和寿命。
延伸铝互连7的弯曲可以是U形的、L形的、之字形的,也可以是它们的组合形的。第三最佳实施例
图9示出了本发明第三最佳实施例的半导体晶片。图9中的参考号对应于图8中的参考号。如图9所示,多个相邻半导体集成电路1a上的引线焊点2和测片焊点3通过带有弯曲的延伸铝互连7而被电连接。至少在半导体集成电路制作区上制作了延伸铝互连7的弯曲。
除第三最佳实施例外,在本最佳实施例中,多个引线焊点2和同一个测片焊点3通过延伸铝互连7而被电连接,使切割线6得以小型化,导致半导体器件的产率上升。第四最佳实施例
图10-15示出了第一最佳实施例的半导体晶片的变例。首先,图10是图1的一个变例,其中用延伸铝互连7代替了使引线焊点2和测片焊点3实行电连接的互连。
其次,图11是图10的一个变例,其中测片焊点3的表面积大于引线焊点2的表面积。测片焊点3最好做大,尽可能多地使用切割线6的表面。测片焊点3的表面积的增大提高了测片探针4和测片焊点3之间的可允许位置偏离,使测片工序更易进行。
图12是图11的一个变例,其中测片焊点3也排列在靠近半导体集成电路1a的角落的切割线6上。虽然在图11中靠近半导体集成电路1a的角落的切割线6上存在至少可形成一个测片焊点3的空白区,但图12中的测片焊点3也形成在靠近半导体集成电路1a的角落的切割线6上,致使在切割线6上不存在这种空白区,从而有效地利用了切割线6。例如,延伸铝互连7为L形,以便在靠近切割线6的角落处也形成测片焊点3。
图13是图1的一个变例,其中在相邻的多个半导体集成电路1a上的引线焊点2由一个引线焊点2组成,引线焊点2的中心用作测片焊点,这可使切割线6小型化,导致半导体器件产率的提高。
图14是图13的一个变例,其中用来对引线焊点2和测片焊点3进行电连接的从半导体集成电路1a延伸到切割线6的连接,被延伸铝互连所取代。
图15示出了对图14的一个变例,其中测片焊点3的表面积大于引线焊点2的表面积。
在图10-15所示的半导体晶片1中,分隔成芯片的半导体集成电路1a用第一最佳实施例所解释的预切割工序、绝缘膜制作工序和最终切割工序加以制作。分隔的半导体集成电路1a带有覆盖测片焊点3的切割部位的绝缘膜9。
由带有弯曲的延伸铝互连取代了延伸铝互连7的那种半导体晶片1,可以用作图10、11、12、14和15所示的半导体晶片1,至少在半导体集成电路制作区中形成了弯曲。
虽然对本发明已进行了详细的描述,但上面的描述在所有情况下都是示例性的而不是限制性的。应该理解,可以作出大量的其它修改和变更而不超越本发明的范围。
Claims (4)
1.一种具有集成电路的半导体晶片,它包含:
半导体晶片;
所述半导体晶片上的至少一个半导体集成电路制作区,包括带有第一焊点的半导体集成电路;
所述半导体晶片上的切割区,包围所述至少一个半导体集成电路制作区,用来将上述半导体晶片切割成具有所述半导体集成电路的芯片;
位于所述半导体晶片上的切割区中的第二焊点;以及
所述半导体晶片上的至少一个铝互连,电连接所述第一焊点和所述第二焊点并具有弯曲的形状以防止所述第一焊点的腐蚀,所述互连在所述半导体集成电路形成区中具有多个U形弯曲,各所述U形弯曲连接所述铝互连中两个通常平行的部分。
2.根据权利要求1的半导体晶片,其中所述的第二焊点的面积大于上述第一焊点的面积。
3.根据权利要求1的半导体晶片,具有多个包围所述至少一个半导体集成电路形成区的所述第二焊点,使得相邻第二焊点之间的区域小于第二焊点,从而所述至少一个半导体集成电路制作区附近的上述切割区中无法设置额外的第二焊点。
4.根据权利要求1的半导体晶片,其中所述至少一个半导体集成电路制作区包含第一和第二半导体集成电路制作区,且所述至少一个铝互连包括第一和第二铝互连。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60794/96 | 1996-03-18 | ||
JP8060794A JPH09252034A (ja) | 1996-03-18 | 1996-03-18 | 半導体ウエハ,半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1160290A CN1160290A (zh) | 1997-09-24 |
CN1095197C true CN1095197C (zh) | 2002-11-27 |
Family
ID=13152578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96121405A Expired - Fee Related CN1095197C (zh) | 1996-03-18 | 1996-11-11 | 半导体晶片 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5982042A (zh) |
JP (1) | JPH09252034A (zh) |
KR (1) | KR100245434B1 (zh) |
CN (1) | CN1095197C (zh) |
DE (1) | DE19645568B4 (zh) |
TW (1) | TW318952B (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100295637B1 (ko) | 1997-12-29 | 2001-10-24 | 김영환 | 반도체웨이퍼의구조및반도체칩의제조방법 |
DE19839807C1 (de) * | 1998-09-01 | 1999-10-07 | Siemens Ag | Verfahren zum Betrieb einer integrierten Schaltung |
US6150669A (en) * | 1998-12-18 | 2000-11-21 | Texas Instruments Incorporated | Combination test structures for in-situ measurements during fabrication of semiconductor devices |
JP4246835B2 (ja) * | 1999-03-09 | 2009-04-02 | ローム株式会社 | 半導体集積装置 |
US6175125B1 (en) * | 1999-05-10 | 2001-01-16 | Taiwan Semiconductor Manufacturing Company | Semiconductor structure for testing vias interconnecting layers of the structure |
US6429452B1 (en) * | 1999-08-17 | 2002-08-06 | Advanced Micro Devices, Inc. | Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process |
TW478089B (en) | 1999-10-29 | 2002-03-01 | Hitachi Ltd | Semiconductor device and the manufacturing method thereof |
TW502355B (en) * | 2000-12-15 | 2002-09-11 | Ind Tech Res Inst | Bonding pad structure to avoid probing damage |
US7344899B2 (en) * | 2002-01-22 | 2008-03-18 | Micron Technology, Inc. | Die assembly and method for forming a die on a wafer |
JP2003249465A (ja) * | 2002-02-26 | 2003-09-05 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP4405719B2 (ja) | 2002-10-17 | 2010-01-27 | 株式会社ルネサステクノロジ | 半導体ウエハ |
US7808115B2 (en) * | 2004-05-03 | 2010-10-05 | Broadcom Corporation | Test circuit under pad |
JP2006140338A (ja) * | 2004-11-12 | 2006-06-01 | Matsushita Electric Ind Co Ltd | 半導体装置 |
DE102007028512A1 (de) * | 2007-06-21 | 2008-12-24 | Robert Bosch Gmbh | Elektrisches Bauteil |
JP4907678B2 (ja) * | 2009-02-20 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
WO2011021506A1 (ja) * | 2009-08-18 | 2011-02-24 | アルプス電気株式会社 | ボンディングパッドを有するシリコン構造体 |
US10553508B2 (en) * | 2014-01-13 | 2020-02-04 | Nxp Usa, Inc. | Semiconductor manufacturing using disposable test circuitry within scribe lanes |
US20150270184A1 (en) * | 2014-03-19 | 2015-09-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Location-Shifted Probe Pads For Pre-Bond Testing |
JP5976055B2 (ja) * | 2014-08-21 | 2016-08-23 | 力晶科技股▲ふん▼有限公司 | 半導体ウエハ、半導体チップ及び半導体装置とそれらの製造方法 |
US9818656B1 (en) * | 2017-05-23 | 2017-11-14 | Nxp Usa, Inc. | Devices and methods for testing integrated circuit devices |
FR3124308B1 (fr) * | 2021-06-17 | 2023-11-03 | St Microelectronics Rousset | Puce électronique |
US20230217598A1 (en) * | 2021-12-30 | 2023-07-06 | X Display Company Technology Limited | Transfer printing high-precision devices |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5952860A (ja) * | 1982-09-20 | 1984-03-27 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPH02235356A (ja) * | 1989-03-08 | 1990-09-18 | Mitsubishi Electric Corp | 半導体装置 |
JPH05299484A (ja) * | 1992-04-20 | 1993-11-12 | Sumitomo Electric Ind Ltd | 半導体ウェハ |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62106638A (ja) * | 1985-11-05 | 1987-05-18 | Toshiba Corp | 半導体ウエハ− |
JPH01304744A (ja) * | 1988-06-01 | 1989-12-08 | Mitsubishi Electric Corp | 半導体装置 |
JPH02184043A (ja) * | 1989-01-10 | 1990-07-18 | Nec Corp | 半導体装置の製造方法 |
JPH02211648A (ja) * | 1989-02-11 | 1990-08-22 | Nec Ic Microcomput Syst Ltd | 半導体装置 |
JP3093216B2 (ja) * | 1989-06-19 | 2000-10-03 | 日本電気株式会社 | 半導体装置及びその検査方法 |
US5239191A (en) * | 1990-01-19 | 1993-08-24 | Kabushiki Kaisha Toshiba | Semiconductor wafer |
JPH0758725B2 (ja) * | 1990-01-19 | 1995-06-21 | 株式会社東芝 | 半導体ウェハ |
US5059899A (en) * | 1990-08-16 | 1991-10-22 | Micron Technology, Inc. | Semiconductor dies and wafers and methods for making |
JPH05206383A (ja) * | 1992-01-24 | 1993-08-13 | Sony Corp | 半導体ウエハー及びその検査方法 |
JPH0637137A (ja) * | 1992-07-14 | 1994-02-10 | Oki Electric Ind Co Ltd | 半導体ウエハの電極構造 |
JPH0685019A (ja) * | 1992-09-07 | 1994-03-25 | Kawasaki Steel Corp | 半導体ウエハ及び半導体ウエハの検査方法 |
JPH06151535A (ja) * | 1992-11-04 | 1994-05-31 | Kawasaki Steel Corp | 半導体ウエハ及び半導体ウエハの検査方法 |
JPH07235598A (ja) * | 1994-02-23 | 1995-09-05 | Mitsubishi Electric Corp | 半導体装置、その製造方法及び製造装置 |
US5532518A (en) * | 1994-11-22 | 1996-07-02 | International Business Machines Corporation | Electrical connect and method of fabrication for semiconductor cube technology |
-
1996
- 1996-03-18 JP JP8060794A patent/JPH09252034A/ja active Pending
- 1996-09-12 TW TW085111132A patent/TW318952B/zh active
- 1996-09-13 US US08/712,611 patent/US5982042A/en not_active Expired - Fee Related
- 1996-11-05 DE DE19645568A patent/DE19645568B4/de not_active Expired - Fee Related
- 1996-11-11 CN CN96121405A patent/CN1095197C/zh not_active Expired - Fee Related
- 1996-11-16 KR KR1019960054679A patent/KR100245434B1/ko not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5952860A (ja) * | 1982-09-20 | 1984-03-27 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPH02235356A (ja) * | 1989-03-08 | 1990-09-18 | Mitsubishi Electric Corp | 半導体装置 |
JPH05299484A (ja) * | 1992-04-20 | 1993-11-12 | Sumitomo Electric Ind Ltd | 半導体ウェハ |
Also Published As
Publication number | Publication date |
---|---|
JPH09252034A (ja) | 1997-09-22 |
KR970067746A (ko) | 1997-10-13 |
US5982042A (en) | 1999-11-09 |
KR100245434B1 (ko) | 2000-03-02 |
DE19645568B4 (de) | 2005-03-03 |
TW318952B (zh) | 1997-11-01 |
CN1160290A (zh) | 1997-09-24 |
DE19645568A1 (de) | 1997-09-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1095197C (zh) | 半导体晶片 | |
CN1093318C (zh) | 半导体装置及其制造方法 | |
CN1320644C (zh) | 晶片级封装、多封装叠层、及其制造方法 | |
CN1191628C (zh) | 具有交替的长焊盘和短焊盘的半导体器件 | |
CN101060088B (zh) | 半导体封装结构及其制造方法 | |
CN1848417A (zh) | 接合垫结构及其形成方法 | |
CN1702853A (zh) | 半导体装置及其制造方法 | |
CN1753153A (zh) | 半导体装置的制造方法 | |
CN1110842C (zh) | 具有间断绝缘区的半导体ic器件及其制造方法 | |
CN1820367A (zh) | 表面安装多片器件 | |
CN1670955A (zh) | 半导体器件 | |
CN1905175A (zh) | 半导体装置及其制造方法 | |
CN1106036C (zh) | 芯片型半导体装置的制造方法 | |
CN1873962A (zh) | 半导体元件及其制造方法 | |
CN1692495A (zh) | 半导体集成装置及其制造方法 | |
CN1913140A (zh) | 半导体器件 | |
CN1282242C (zh) | 芯片比例封装及其制造方法 | |
CN1367533A (zh) | 与安装基片有可靠连接的半导体器件 | |
CN1835231A (zh) | 半导体装置及其制造方法 | |
CN1206728C (zh) | 芯片封装及其制造方法 | |
CN1725462A (zh) | 半导体器件及半导体器件的制造方法 | |
CN1808711A (zh) | 封装体及封装体模块 | |
CN1459872A (zh) | 半导体集成装置及其制造方法 | |
CN1574321A (zh) | 铜制程焊垫结构及其制造方法 | |
CN1574320A (zh) | 半导体封装元件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C19 | Lapse of patent right due to non-payment of the annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |