CN1574321A - 铜制程焊垫结构及其制造方法 - Google Patents

铜制程焊垫结构及其制造方法 Download PDF

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CN1574321A
CN1574321A CN200310120177.7A CN200310120177A CN1574321A CN 1574321 A CN1574321 A CN 1574321A CN 200310120177 A CN200310120177 A CN 200310120177A CN 1574321 A CN1574321 A CN 1574321A
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protective layer
copper
weld pad
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metal interconnect
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赖嘉宏
林俊吉
张宗生
曹敏
曾焕棋
李豫华
杨青天
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种铜制程焊垫结构及其制造方法，此铜制程焊垫结构包含第一保护层，第二保护层，以及多个焊垫。第一保护层与第二保护层，是覆盖于半导体基材的最上层铜金属内联线之上，且具有多个开口，使露出最上层铜金属内联线表面。而焊垫形成于第一保护层的开口上方，并与最上层铜金属内联线表面相互连接，且相邻的焊垫彼此之间由第二保护层所隔离。本发明的另一方面是说明形成上述的铜制程焊垫的制造方法。通过本发明的铜制程焊垫结构及其制造方法，可防止焊垫之间短路的情况，提高集成电路产品的可靠度，还可提高集成电路的焊垫密度，以有效增加集成电路产品的输出/输入接口的数量，增强集成电路产品的功能。

Description

铜制程焊垫结构及其制造方法
技术领域
本发明涉及一种铜制程(COPPER PROCESS)焊垫结构及其制造方法，特别是有关于一种集成电路制程中所使用的铜制程焊垫结构及其制造方法。
背景技术
随着集成电路的线宽尺寸的微小化趋势，特别是0.25微米，乃至于0.13微米以下，组件的运算速度明显受到金属导线所造成的电阻电容延迟时间(Resistance Capacitance Delay Time；RC Delay Time)的影响，以致于降低其运算速度。因此，面对目前集成度(Integration)更高的电路设计，除了必须采用具有更低电阻的金属材料，例如电阻值约为1.67微欧姆-公分的铜(Cu)，来取代传统所采用的电阻值约为2.66微欧姆-公分的铝，更必须搭配低介电常数的介电材料来建构多层金属内联线，以改善RC延迟的现象。
由于铜具有低电阻的特性，因此以铜为内联线的组件可承受更密集的电路排列。于是，铜金属的使用不仅可大幅缩减金属层的数目，降低生产成本，更可提升组件的运算速度。铜具有较高的抗电致迁移(Electronmigration)的能力，因此，以铜为内联线的组件尚具有更长的寿命及较佳的稳定性等优点。
以铜金属作为内联线的组件，在完成其所需的功能的电路布置后，一般采用较容易制作的铝质金属来制作组件的焊垫，例如是铝铜合金等材料所构成的焊垫。参阅图1，图1为一公知铝铜焊垫的剖面示意图。如图中所示，铜金属内联线110为最上层的金属内联线，其上方的保护层(Passivation Layer)120则藉由蚀刻等制备过程形成开口，然后再形成焊垫(Bond Pad)130。焊垫130为集成电路与外界电路相连接的接口，使用于集成电路后续的引线接合(Wire Bond)封装制程。
近年来，集成电路的设计随着功能增强、尺寸小型化以及大量的输出/输入接口的需求，以致于缩小焊垫尺寸以及其间距的设计俨然已成为集成电路发展的趋势。一般而言，在0.13微米制程中，间距140的宽度约为3微米(μm)。更由于铝铜合金的质地较软，因此，在引线接合制程中焊垫130很容易产生变形，进而导致桥接(Bridging)的情况，使组件产生短路，严重影响产品的可靠度与良率。
因此，如何能有效改善焊垫130的隔离结构，使焊垫的结构能有效的防止桥接问题的产生，不仅可以提高集成电路的线路稳定性，更可进一步提高集成电路的产品可靠度，为集成电路的使用者与制造者所殷殷企盼。
鉴于上述的发明背景中，由于焊垫之间的间距越来越小，使得在进行引线接合时，易造成相邻焊垫产生桥接的问题，不仅会造成集成电路的产品可靠度的降低，更造成集成电路焊垫的短路。因此，提高集成电路焊垫的结构可靠度，以避免短路的情况，才能进一步提高产品的可靠度。
发明内容
本发明的目的之一是提供一种铜制程焊垫结构及其制造方法，可防止焊垫之间短路的情况。
本发明的另一目的是提供一种铜制程焊垫结构及其制造方法，以提高集成电路产品的可靠度。
为达到上述目的，本发明提供了一种铜制程焊垫结构，至少包含：一第一保护层，覆盖于一半导体基材的一最上层金属内联线之上，其中该第一保护层具有数个第一开口，且所述第一开口露出该最上层金属内联线的数个区域；一第二保护层，形成于该第一保护层之上，具有数个第二开口，且分别对应于所述第一开口，以露出所述第一开口；以及数个焊垫，形成于所述第一开口之上，并位于所述第二开口之中，且所述焊垫与该最上层金属内联线所露出的所述区域电性连接。
本发明还提供了一种铜制程焊垫的制造方法，至少包含：形成一第一保护层，覆盖于一半导体基材之上，其中该半导体基材具有一最上层金属内联线；形成一第二保护层，覆盖于该第一保护层之上；图案化该第二保护层，以形成数个第一开口；图案化该第一保护层，以形成数个第二开口分别对应于所述第一开口之中，以露出该最上层金属内联线的数个区域；以及形成数个焊垫于所述第二开口之上与所述第一开口之中，其中所述焊垫与该最上层金属内联线所露出的所述区域电性连接，且所述焊垫被该第二保护层所隔离。
也就是说，本发明提供的铜制程焊垫结构包含，第一保护层，第二保护层，以及数个焊垫。其中第一保护层，是覆盖于半导体基材的最上层金属内联线之上。且第一保护层具有数个开口，使露出最上层金属内联线的数个区域。第二保护层，形成于第一保护层之上，并露出上述的开口。上述的焊垫，形成于开口之上，并与最上层金属内联线所露出的区域相互连接，且上述的焊垫经由第二保护层彼此之间相互隔离。
其中上述的最上层金属内联线为铜金属内联线。第一保护层包含二氧化硅(SiO2)所构成的保护层，其厚度约为4000埃，第二保护层则包含氮化硅(SiN)所构成的保护层，其厚度约为6000埃，且介于焊垫之间的第二保护层宽度约为3微米(μm)。而上述的焊垫，则为铝铜合金、铝硅铜合金或铝所构成的金属焊垫。
本发明的另一方面为一种铜制程焊垫的制造方法。此制造方法包含下列步骤，首先，提供半导体基材，且半导体基材具有最上层金属内联线。接着在依序形成第一保护层与第二保护层，接着依序图案化第二保护层与第一保护层，以形成数个开口，使露出最上层金属内联线的数个区域。然后，形成数个焊垫，于第一保护层的开口上方，并与最上层金属内联线所露出的区域相连接。上述的焊垫彼此之间还由第二保护层所隔离。
其中上述的最上层金属内联线为一铜金属内联线，第一保护层包含二氧化硅保护层，且其厚度约为4000埃。第二保护层包含氮化硅(SiN)保护层，且其厚度约为6000埃，而宽度则约为3微米。
本发明的铜制程焊垫结构及其制造方法，不仅可以有效改善焊垫的隔离结构，使焊垫的在引线接合制程中有效避免产生桥接的问题，一方面可以提高集成电路的电路设计的稳定性，另一方面可进一步提高集成电路的产品可靠度，同时本发明更可提高集成电路的焊垫密度，以有效增加集成电路产品的输出/输入接口的数量，使增强集成电路产品的功能。
为让本发明的上述和其它目的、特征、和优点能更明显易懂，特举较佳实施例，并配合下列附图做更详细说明。
附图说明
图1为一公知铝铜焊垫的剖面示意图；
图2为本发明的铜制程焊垫结构的示意图；以及
图3A至图3D为本发明的铜制程焊垫制造方法的流程示意图。
其中，附图标记说明如下：
110-铜金属内联线；120-保护层；130-焊垫；140-间距；
210-铜金属内联线；220-第一保护层；230-焊垫；
240-第二保护层；250-宽度；310-铜金属内联线；
320-第一保护层；330-第二保护层；332-第一开口；
340-第二开口；360-金属层；370-焊垫；380-宽度。
具体实施方式
本发明提供一种铜制程焊垫结构及其制造方法，具有改善焊垫的隔离结构，使焊垫能有效防止短路问题的发生，不仅改善集成电路的电器特性，更可进一步提高集成电路产品的可靠度。以下将以附图及详细说明清楚说明本发明的精神，如熟悉此技术的人员在了解本发明的较佳实施例后，当可由本发明所教示的技术，加以改变及修饰，其并不脱离本发明的精神与范围。
参阅图2，为本发明的铜制程焊垫结构的示意图。如图中所示，兹将本发明的铜制程焊垫结构详述如下。本发明的铜制程焊垫结构包含铜金属内联线210，第一保护层220，以及焊垫230。铜金属内联线210为此集成电路的最上层的金属内联线。第一保护层220则覆盖于铜金属内联线210之上，并露出部分铜金属内联线210。焊垫230与露出的部分铜金属内联线210电性连接。而每一相邻的焊垫230之间更具有第二保护层240，以确保在引线接合制程中，虽然焊垫230产生变形，但却能为第二保护层240所阻隔，而不会产生桥接现象，以致于有效阻止短路的情形发生。
其中，第一保护层220包含二氧化硅(SiO2)所构成的保护层，其厚度约为4000埃(Angstrom)，而第二保护层240包含由氮化硅(SiN)所构成的保护层，其厚度约为6000埃。且第二保护层240的宽度250仅需与公知的焊垫间距相当即可，例如是3微米(μm)。
因此，本发明的铜制程焊垫结构，可在无需变更任何设计条件的情况下，使用于集成电路的焊垫设计，不仅可避免焊垫桥接所产生的短路的问题，更可以有效电性隔离焊垫，以提高集成电路的产品的可靠度。其中焊垫是使用铝铜合金、铝硅铜合金或铝所构成的金属焊垫，用来与集成电路外部接脚电性耦合，以提供集成电路输出/输入的接口。
由于本发明的铜制程焊垫结构，利用第二保护层240，以有效的隔离相邻的焊垫230。因此，使用本发明的铜制程焊垫结构的集成电路，可进一步缩小焊垫之间的间距，以提高焊垫的数量，进而增加集成电路产品的输出/输入接口的数量。
本发明的铜制程焊垫结构，合适于使用在任何需要引线接合的焊垫隔离设计上。当使用于0.13微米制程中，第二保护层240的宽度250约仅为3微米，在其它更细微的制程中或需要更多的输出输入焊垫的设计中，本发明可有效改变第二保护层240的宽度250的设计，以达到上述的保护功能，均不脱离本发明的精神与范围。
参阅图3A至图3D，本发明的铜制程焊垫制造方法的流程说明如下。首先，如图3A中所示，在集成电路的最上层铜金属内联线310上，依序形成第一保护层320与第二保护层330，并图案化第二保护层330，以在预定的位置形成第一开口332。
参阅图3B，如图中所示，接下来图案化第一保护层320，以形成第二开口340于第一保护层320之中，使其露出上述的最上层铜金属内联线310的部分区域。参阅图3C，如图中所示，接着再形成金属层360于上述的第一保护层320、第二保护层330、第一开口332与第二开口340之上。例如使用金属溅镀(Sputtering)、蒸镀(Evaporation)或者是化学气相沉积(ChemicalVapor Deposition)等方法，以形成此金属层360。
如图3D中所示，进行金属层360的图案化，以形成所需的焊垫370。而在图案化金属层360之时，第一保护层320更具有提供蚀刻终止层的功能。由于相邻的焊垫370之间，均被第二保护层330所分隔，因此焊垫370被有效的加以隔离，使焊垫370在后续的引线接合制程中，可避免产生桥接的问题。
一般而言，在0.13微米制程中，第二保护层330的宽度380约仅为3微米。而上述的金属层360为一铝质金属层，例如是，铝、铝铜合金或者是铝硅铜合金等。而金属层360可使用如微影与蚀刻过程，以进行图案化。
本发明的铜制程焊垫结构及其制造方法能有效的隔离相邻的焊垫，以避免在引线接合制程中，相邻的焊垫产生桥接的问题。不仅可以提高集成电路产品的可靠度，更可以避免焊垫短路的问题，且可更进一步提高焊垫的密度，以增加输出/输入端子的数量，提高集成电路产品的功能。
如熟悉此技术的人员所了解的，以上所述仅为本发明的较佳实施例而已，并非用以限定本发明的申请专利范围。凡其它未脱离本发明所揭示的精神下所完成的等效改变或修饰，均应包含在本发明的申请专利范围内。

Claims (20)

1.一种铜制程焊垫结构，至少包含：
一第一保护层，覆盖于一半导体基材的一最上层金属内联线之上，其中该第一保护层具有数个第一开口，且所述第一开口露出该最上层金属内联线的数个区域；
一第二保护层，形成于该第一保护层之上，具有数个第二开口，且分别对应于所述第一开口，以露出所述第一开口；以及
数个焊垫，形成于所述第一开口之上，并位于所述第二开口之中，且所述焊垫与该最上层金属内联线所露出的所述区域电性连接。
2.如权利要求1所述的铜制程焊垫结构，其中上述的最上层金属内联线为一铜金属内联线。
3.如权利要求1所述的铜制程焊垫结构，其中上述的第一保护层包含一二氧化硅保护层。
4.如权利要求3所述的铜制程焊垫结构，其中上述的二氧化硅保护层的厚度约为4000埃。
5.如权利要求1所述的铜制程焊垫结构，其中上述的第二保护层包含一氮化硅保护层。
6.如权利要求5所述的铜制程焊垫结构，其中上述的氮化硅保护层的厚度约为6000埃。
7.如权利要求1所述的铜制程焊垫结构，其中上述的第二保护层介于所述焊垫之间的宽度约为3微米。
8.如权利要求1所述的铜制程焊垫结构，其中上述的焊垫为铝铜合金所构成的焊垫。
9.一种铜制程焊垫的制造方法，至少包含：
形成一第一保护层，覆盖于一半导体基材之上，其中该半导体基材具有一最上层金属内联线；
形成一第二保护层，覆盖于该第一保护层之上；
图案化该第二保护层，以形成数个第一开口；
图案化该第一保护层，以形成数个第二开口分别对应于所述第一开口之中，以露出该最上层金属内联线的数个区域；以及
形成数个焊垫于所述第二开口之上与所述第一开口之中，其中所述焊垫与该最上层金属内联线所露出的所述区域电性连接，且所述焊垫被该第二保护层所隔离。
10.如权利要求9所述的制造方法，其中上述的最上层金属内联线为一铜金属内联线。
11.如权利要求9所述的制造方法，其中上述的第一保护层包含一二氧化硅保护层。
12.如权利要求11所述的制造方法，其中上述的二氧化硅保护层的厚度约为4000埃。
13.如权利要求9所述的制造方法，其中上述的第二保护层包含一氮化硅保护层。
14.如权利要求13所述的制造方法，其中上述的氮化硅保护层的厚度约为6000埃。
15.如权利要求9所述的制造方法，其中上述的第二保护层介于所述焊垫之间的宽度约为3微米。
16.如权利要求9所述的制造方法，其中上述的焊垫为铝铜合金所构成的焊垫。
17.一种铜制程焊垫的制造方法，至少包含：
提供一半导体基材，该半导体基材具有一最上层铜金属内联线；
形成一二氧化硅保护层，覆盖于该半导体基材之上；
形成一氮化硅保护层，覆盖于该二氧化硅保护层之上；
图案化该氮化硅保护层，以形成数个第一开口；
图案化该二氧化硅保护层，以形成数个第二开口分别对应于所述第一开口，使露出该最上层铜金属内联线的数个区域；以及
形成数个铝铜合金焊垫于所述第二开口之上与所述第一开口之中，其中所述铝铜合金焊垫与该最上层铜金属内联线所露出的所述区域电性连接，且所述铝铜合金焊垫被该氮化硅保护层所隔离。
18.如权利要求17所述的制造方法，其中上述的二氧化硅保护层的厚度约为4000埃。
19.如权利要求17所述的制造方法，其中上述的氮化硅保护层的厚度约为6000埃。
20.如权利要求17所述的制造方法，其中上述的氮化硅保护层介于所述焊垫之间的宽度约为3微米。
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