CN2731711Y - 铜金属镶嵌结构 - Google Patents

铜金属镶嵌结构 Download PDF

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CN2731711Y
CN2731711Y CNU2004200667623U CN200420066762U CN2731711Y CN 2731711 Y CN2731711 Y CN 2731711Y CN U2004200667623 U CNU2004200667623 U CN U2004200667623U CN 200420066762 U CN200420066762 U CN 200420066762U CN 2731711 Y CN2731711 Y CN 2731711Y
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layer
copper metal
copper
metal
dielectric layer
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吴振诚
卢永诚
章勋明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

一种铜金属镶嵌结构,先在基材上依序形成介电层与蚀刻终止层,再于介电层与蚀刻终止层中形成金属插塞。接着,形成另一介电层于蚀刻终止层上,定义出后续形成铜金属层的开口结构。随后,形成介电阻障层于开口中,并利用回蚀刻将开口底部的部分介电阻障去除,以暴露出金属插塞。再形成铜金属层于开口中。上述制程于开口中暴露金属插塞的同时,暴露出蚀刻终止层。因此,此结构中的铜金属与金属插塞以及蚀刻终止层接触,而不会与介电层接触,所以可改善铜金属的扩散现象。

Description

铜金属镶嵌结构
技术领域
本实用新型涉及一种集成电路的铜金属镶嵌结构,特别涉及一种利用介电材料作为阻障层的铜金属镶嵌结构。
背景技术
过去数十年来,铝金属一直被用来当作芯片内部的导线材料。但是随着集成电路制程除了朝小体积的组件发展,以达到高密度及降低单位成本的目的之外,组件的最后的性能更是关键。除了晶体管组件本身的设计外,内连接金属导线乃至内连线间的介电层都是影响组件执行速度的重要因素,这是因导线的电阻值R,和上层导线与下层导线及相邻导线之间会有电容C存在,一如熟知相关技术的人士所共知,此RC值愈小代表较短的延迟时间。
纯铝的电阻系数约为2.7微欧姆-厘米,但是铜金属的电阻系数却约为1.7微欧姆-厘米左右,要远小于铝金属。所以,为有效降低阻抗率,铜材料方为最佳的选择。由于铜具有低电阻的特性,因此以铜为导线的组件可承受更密集的电路排列,如此可大大减少所需金属层的数目,进而降低生产成本且提高计算机的运算速度。此外,铜还具有较高的电子迁移阻力(Electromigration Resistance),因此以铜为导线的组件具有更高的寿命以及稳定性。
但是,铜金属的一些化学性质却限制了铜制程在集成电路上的发展。举例来说,铜原子具有快速的扩散性,在电场的加速下,铜原子能穿透介电层而快速的扩散,尤其一旦铜原子扩散至硅基材中,会引入深层能阶受体(Deep LevelAcceptor),造成组件的特性退化与失效。因此,在铜金属层形成前,需要先形成防止铜和氧化层或硅层接触的阻障层(Barrier Layer),以避免铜扩散或催化等污染。阻障层的另一项作用是用来提升金属与其它材料的附着力。一般阻障层材料可分为金属阻障材料以及介电阻障层材料等,常见的阻障层材料例如有钽(Ta)、氮化钽(TaN)、氮化钛(TiN)等等。
铜材料无法用传统的干式蚀刻技术来进行导线布植,因此目前工业界大部分采用新一代的导线制作技术镶嵌(Damascene)法来做铜导线的填充。图1至图6所绘示为现有铜金属化制程的剖面示意图。
请参照图1,首先提供基材10,并在基材10上形成介电层12。接着,利用微影蚀刻方式,在介电层12形成开口,并于开口内填满金属材料,即可形成金属插塞14。此金属插塞14用来连接不同层的组件或金属层。
接着,请参照图2,依序在介电层上形成蚀刻终止层16与另一介电层18。并随后利用微影蚀刻方式,在介电层12形成开口20,而暴露出金属插塞14,如图3所示。之后,为防止铜金属的扩散,会在形成铜金属层之前,先于开口20中形成一层阻障层22,如图4所示。随后,再于开口20中填满铜金属层24,以作为另一层金属连线结构。
由于阻障材料的导电性质不同,例如金属阻障材料与介电阻障材料,因此形成阻障层22后再填满铜金属层24的制程与结构也不尽相同。如果利用金属阻障材料来构成图4的阻障层22,由于金属阻障材料并不影响开口中铜金属与金属插塞14的导通,因此可接着在阻障层22上形成一层铜金属材料,并填满开口20。随后,再利用化学机械研磨,将介电层18上多余的铜金属材料与阻障层22去除,而形成如图5的结构。又如果利用介电阻障材料来构成图4的阻障层22,由于介电阻障材料无法导电,则必须先利用回蚀刻将开口24中覆盖在金属插塞14上的部分阻障层22去除,同时也去除了介电层18上的多余阻障层22。随后,再形成铜金属材料,并利用化学机械研磨将介电层18上的多余铜金属材料去除,而形成如图6的结构。
在上述利用介电材料构成阻障层的图6结构中,在铜金属层24两旁的阻障层22可用来阻障铜原子的扩散,但是在制程中暴露金属插塞14表面的同时,却将开口底部阻挡铜金属层与介电层12接触的部分阻障层22也同时去除。因此,如区域26所示,因为有部分的铜金属层24与介电层12接触,所以很容易发生铜原子的扩散现象。
发明内容
鉴于上述的现有技术中,利用介电材料构成铜制程的阻障层时,很容易发生铜原子的扩散现象,因此,本实用新型的目的在于提供一种铜金属镶嵌制程及其结构,先在介电层上形成蚀刻终止层,接着再形成金属插塞于介电层与蚀刻终止层中。如此,当后续暴露开口中的金属插塞结构时,所同时暴露出的即为金属插塞旁的蚀刻终止层。当铜金属与蚀刻终止层接触时,可利用蚀刻终止层的阻障特性来防止铜原子的扩散。
根据上述目的,本实用新型的铜金属镶嵌制程包括:首先于一基材上依序形成一介电层与一沉积层;接着,于沉积层与第一介电层中形成金属插塞,之后再形成另一介电层覆盖于沉积层上;随后,于第二介电层中形成开口结构,此开口结构并暴露出该沉积层中金属插塞;之后,形成阻障层覆盖于第二介电层与开口表面上,并且利用例如回蚀刻步骤,去除部分的阻障层,以暴露出第二介电层与开口中的金属插塞表面;最后,形成铜金属层以填满开口。
根据上述目的,本实用新型的铜金属镶嵌结构包括:一基材;位于基材上的一第一介电层;位于第一介电层上的一沉积层;位于沉积层与第一介电层中的金属插塞;位于沉积层上的一第二介电层;位于第二介电层中的一铜金属层,以及位于铜金属层的两侧侧壁的阻障层,铜金属层的底部与金属插塞相互接触。
本实用新型中,上述铜金属层的底部可位于沉积层的表面或位于沉积层中。并且,当铜原子与沉积层接触时,可利用沉积层的阻障特性来防止铜原子的扩散。
附图说明
图1至图6所绘示为现有铜金属镶嵌制程的剖面示意图;以及
图7至图10所绘示为依据本实用新型一较佳实施例的铜金属镶嵌制程的剖面示意图。
具体实施方式
为了使本实用新型的叙述更加详尽与完备,可参照下列描述并配合图7至图10的图标。图7至图10所绘示为依据本实用新型一较佳实施例的铜金属镶嵌制程的剖面示意图。
请参照图7,首先提供基材100,此基材100可为一般的硅基材,或者已制造有其它组件的硅基材。接着,在基材100上依序沉积厚度约介于5000埃至10000埃之间的介电层102以及厚度约为500埃的蚀刻终止层104。介电层102的目的作为金属层间的绝缘,其材料可例如磷硅玻璃(PSG)与四乙基硅酸盐(Tetra-Ethyl-Ortho-Silicate;TEOS)等等。
接着,再利用例如微影蚀刻等方式,在介电层102与蚀刻终止层104中形成开口,并于开口内填满例如钨等金属材料,即可形成具有暴露表面的金属插塞106。此金属插塞106结构当基材100上有其它组件或金属层时,为连接不同层的组件或金属层所形成。
请参照图8,接着,在蚀刻终止层104上形成由例如低介电系数材料所构成的另一介电层108,并在介电层108中利用例如微影蚀刻制程,而形成例如为沟渠(Trench)或介层窗(Via)等的开口120结构,以暴露出位于底下的金属插塞106。在图8的蚀刻步骤中,除了去除部分的介电层108以暴露出金属插塞106表面外,较佳更可再往下去除少部分的蚀刻终止层104与金属插塞106,使得开口120的底部介于蚀刻终止层104之间。
在本实用新型一较佳实施例中,上述蚀刻终止层104的厚度约为500埃,而介电层108的厚度约介于2500埃至3000埃之间,因此,较佳的开口120深度约介于2800埃至3300埃之间,如此可使得开口120的底部介于蚀刻终止层104之间。
请参照图9,接着,在介电层108上与开口120表面形成由介电材料所构成的阻障层122,此阻障层122的厚度约为300埃。随后,进行一回蚀刻步骤,将位于介电层108表面以及开口120底部的多余阻障层122去除,而暴露出金属插塞106。并且,由于位于开口120底部的部分阻障层122被去除,因此在暴露金属插塞106的同时,也暴露出两旁与金属插塞106接触的部分蚀刻终止层104。
接着,在介电层108上形成一层铜金属层124,此铜金属层124并填满开口120。随后,再利用例如化学机械研磨,将介电层108表面上的多余铜金属层124去除,而形成如图10的结构。由于铜金属层124的形成方式并非本实用新型的重点,故本实用新型并不在此赘述。
本实用新型如图10的铜金属镶嵌结构的特点在于,由于金属插塞除了位于介电层中,更位于蚀刻终止层中。因此,为暴露金属插塞而形成的开口底部会位于蚀刻终止层的表面或位于蚀刻终止层中,而暴露金属插塞的同时,有可能暴露的是金属插塞两旁的蚀刻终止层。所以形成铜金属于开口中时,铜金属层利用阻障层与蚀刻终止层与四周的介电层作隔离,并不会互相接触,而可避免现有铜原子扩散的缺点。
由于阻障层122与蚀刻终止层104需具备阻障特性,并且在回蚀刻步骤中,蚀刻终止层104与阻障层122之间必须具备较高的蚀刻选择比,才能使蚀刻制程易于进行。因此在本实用新型一较佳实施例中,利用碳氧化硅(SiOC)作为蚀刻终止层104的材料,以及利用碳化硅(SiC)作为阻障层122的材料,可具有较佳的阻障效果并使制程易于进行。但值得注意的是,上述蚀刻终止层与阻障层的材料仅为举例,可视需要而加以改变,本实用新型不限于此。并且,上述的蚀刻终止层仅为举例,具有其它功效却位于相同位置的沉积层,也可应用于本实用新型中,本实用新型也不限于此。
而本实用新型铜金属镶嵌制程的特点在于,先在介电层102上形成蚀刻终止层104后,去除部分的介电层102与蚀刻终止层104而形成金属插塞106的开口结构。因此,可使得后续形成的金属插塞106表面并不像现有结构位于蚀刻终止层104下方,而是与蚀刻终止层104具有同样水平的表面。所以,当后续阻障层122的回蚀刻制程以暴露出金属插塞106时,所同时暴露出的为蚀刻终止层104,而非介电层102。当铜金属层124与具有阻障效果的蚀刻终止层104接触时,并不会发生现有的铜原子扩散现象。
利用一般制程设备与步骤可进行本实用新型的制程与形成本实用新型的结构,无需再另外添购设备或增加不兼容的步骤。并且,利用上述本实用新型的铜金属镶嵌制程及其结构,可避免铜金属扩散到底部的介电层中,并可因此具有降低铜金属层漏电流(Leakage)、改善时间关联介电崩溃(Time DependentDielectric Breakdown;TDDB)的特性、降低RC延迟等优点。

Claims (12)

1.一种铜金属镶嵌结构,其特征在于,该结构至少包括:
一基材;
一位于该基材上的第一介电层;
一位于该第一介电层上的沉积层;
至少一位于该沉积层与该第一介电层中的金属插塞;
一位于该沉积层上的第二介电层;
至少一位于该第二介电层中的铜金属层,该铜金属层的底部与该金属插塞接触;以及
一位于该铜金属层的两侧侧壁的阻障层。
2.根据权利要求1所述的铜金属镶嵌结构,其特征在于:上述的铜金属层的底部位于该沉积层的表面。
3.根据权利要求1所述的铜金属镶嵌结构,其特征在于:上述的铜金属层的底部位于该沉积层中。
4.根据权利要求3所述的铜金属镶嵌结构,其特征在于:上述的铜金属层与该沉积层接触。
5.根据权利要求3所述的铜金属镶嵌结构,其特征在于:上述的基材具有至少一电路组件。
6.根据权利要求3所述的铜金属镶嵌结构,其特征在于:上述的第一介电层的材料选自于由磷硅玻璃与四乙基硅酸盐所组成一族群。
7.根据权利要求3所述的铜金属镶嵌结构,其特征在于:上述的沉积层为一蚀刻终止层。
8.根据权利要求3所述的铜金属镶嵌结构,其特征在于:上述的沉积层由一阻障材料所构成。
9.根据权利要求8所述的铜金属镶嵌结构,其特征在于:上述的沉积层由氧碳化硅所构成。
10.根据权利要求3所述的铜金属镶嵌结构,其特征在于:上述的阻障层由一介电阻障材料所构成。
11.根据权利要求10所述的铜金属镶嵌结构,其特征在于:上述的阻障层由碳化硅所构成。
12.根据权利要求3所述的铜金属镶嵌结构,其特征在于:上述的第二介电层由一低介电系数材料所构成。
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