SG141230A1 - Method of a non-metal barrier copper damascene integration - Google Patents

Method of a non-metal barrier copper damascene integration

Info

Publication number
SG141230A1
SG141230A1 SG200403599-4A SG2004035994A SG141230A1 SG 141230 A1 SG141230 A1 SG 141230A1 SG 2004035994 A SG2004035994 A SG 2004035994A SG 141230 A1 SG141230 A1 SG 141230A1
Authority
SG
Singapore
Prior art keywords
barrier layer
layer
copper damascene
barrier
damascene integration
Prior art date
Application number
SG200403599-4A
Other languages
English (en)
Inventor
Zhen-Cheng Wu
Yung-Chen Lu
Syun-Ming Jang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of SG141230A1 publication Critical patent/SG141230A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG200403599-4A 2003-06-11 2004-06-09 Method of a non-metal barrier copper damascene integration SG141230A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/459,222 US7151315B2 (en) 2003-06-11 2003-06-11 Method of a non-metal barrier copper damascene integration

Publications (1)

Publication Number Publication Date
SG141230A1 true SG141230A1 (en) 2008-04-28

Family

ID=33510766

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200403599-4A SG141230A1 (en) 2003-06-11 2004-06-09 Method of a non-metal barrier copper damascene integration

Country Status (4)

Country Link
US (1) US7151315B2 (zh)
CN (2) CN1326231C (zh)
SG (1) SG141230A1 (zh)
TW (1) TWI231564B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
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US7151315B2 (en) * 2003-06-11 2006-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of a non-metal barrier copper damascene integration
US20060216924A1 (en) * 2005-03-28 2006-09-28 Zhen-Cheng Wu BEOL integration scheme for etching damage free ELK
US7713865B2 (en) * 2005-06-24 2010-05-11 International Business Machines Corporation Preventing damage to metal using clustered processing and at least partially sacrificial encapsulation
KR100711912B1 (ko) * 2005-12-28 2007-04-27 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
US20080260967A1 (en) * 2007-04-17 2008-10-23 Hyungsuk Alexander Yoon Apparatus and method for integrated surface treatment and film deposition
US7645701B2 (en) * 2007-05-21 2010-01-12 International Business Machines Corporation Silicon-on-insulator structures for through via in silicon carriers
WO2009014646A1 (en) * 2007-07-20 2009-01-29 Applied Materials, Inc. Methods and apparatus to prevent contamination of a photoresist layer on a substrate
US7781332B2 (en) * 2007-09-19 2010-08-24 International Business Machines Corporation Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer
US7737052B2 (en) * 2008-03-05 2010-06-15 International Business Machines Corporation Advanced multilayer dielectric cap with improved mechanical and electrical properties
JP5654794B2 (ja) * 2010-07-15 2015-01-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8420531B2 (en) 2011-06-21 2013-04-16 International Business Machines Corporation Enhanced diffusion barrier for interconnect structures
JP6041527B2 (ja) * 2012-05-16 2016-12-07 キヤノン株式会社 液体吐出ヘッド
CN104347477B (zh) * 2013-07-24 2018-06-01 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9219033B2 (en) * 2014-03-21 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Via pre-fill on back-end-of-the-line interconnect layer
US10916503B2 (en) 2018-09-11 2021-02-09 International Business Machines Corporation Back end of line metallization structure
US11398406B2 (en) * 2018-09-28 2022-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Selective deposition of metal barrier in damascene processes
US11637036B2 (en) * 2020-01-30 2023-04-25 International Business Machines Corporation Planarization stop region for use with low pattern density interconnects

Citations (3)

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US20020130419A1 (en) * 2001-03-15 2002-09-19 Micron Technology, Inc. Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect
US6525428B1 (en) * 2002-06-28 2003-02-25 Advance Micro Devices, Inc. Graded low-k middle-etch stop layer for dual-inlaid patterning

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US6436824B1 (en) 1999-07-02 2002-08-20 Chartered Semiconductor Manufacturing Ltd. Low dielectric constant materials for copper damascene
US6284657B1 (en) * 2000-02-25 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Non-metallic barrier formation for copper damascene type interconnects
US6566258B1 (en) 2000-05-10 2003-05-20 Applied Materials, Inc. Bi-layer etch stop for inter-level via
US6261963B1 (en) * 2000-07-07 2001-07-17 Advanced Micro Devices, Inc. Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices
US6774489B2 (en) * 2000-08-29 2004-08-10 Texas Instruments Incorporated Dielectric layer liner for an integrated circuit structure
JP2002110679A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
US6380084B1 (en) * 2000-10-02 2002-04-30 Chartered Semiconductor Manufacturing Inc. Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
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JP3974023B2 (ja) * 2002-06-27 2007-09-12 富士通株式会社 半導体装置の製造方法
US6770570B2 (en) * 2002-11-15 2004-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer
US7151315B2 (en) * 2003-06-11 2006-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of a non-metal barrier copper damascene integration

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020130419A1 (en) * 2001-03-15 2002-09-19 Micron Technology, Inc. Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect
US6525428B1 (en) * 2002-06-28 2003-02-25 Advance Micro Devices, Inc. Graded low-k middle-etch stop layer for dual-inlaid patterning

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
INTEGRATION OF CU/SIOC IN DUAL DAMASCENE INTERCONNECT FOR 0,1 MICRON TECHNOLOGY USING A NEW SIC MATERIAL AS DIELECTRIC BARRIER *

Also Published As

Publication number Publication date
US20040251547A1 (en) 2004-12-16
CN2731711Y (zh) 2005-10-05
TWI231564B (en) 2005-04-21
CN1574281A (zh) 2005-02-02
TW200428576A (en) 2004-12-16
CN1326231C (zh) 2007-07-11
US7151315B2 (en) 2006-12-19

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