CN1326231C - 铜金属镶嵌工艺及其结构 - Google Patents
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims description 66
- 229910052802 copper Inorganic materials 0.000 title claims description 57
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
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Abstract
本发明提供一种铜金属镶嵌工艺及其结构，其先在基材上依序形成介电层与蚀刻终止层后，再在介电层与蚀刻终止层中形成金属插塞。接着，在蚀刻终止层上形成另一介电层并在该介电层中加工出后续用来形成铜金属层的开口结构。随后，在开口中形成介电阻障层，并利用回蚀刻将开口底部的部分介电阻障去除，以暴露出金属插塞。之后，再在开口中形成铜金属层。上述工艺中在开口中加工暴露金属插塞的同时，是暴露出蚀刻终止层而非介电层。因此，此结构中的铜金属与金属插塞以及蚀刻终止层接触，而不会与介电层接触，所以可改善铜金属的扩散现象。
Description
技术领域
本发明是关于集成电路的铜加工工艺，特别是关于利用介电材料作为阻障层的铜金属镶嵌工艺及其结构。
背景技术
过去数十年来，铝金属一直被用来当作芯片内部的导线材料。但是随着集成电路加工除了朝小体积的组件发展，以达到高密度及降低单位成本的目的外，组件的最后的性能更为关键。除了晶体管组件本身的设计外，内连接金属导线乃至内联机间的介电层都是影响组件执行速度的重要因素，这是因为导线的电阻值R，和上层导线与下层导线及相邻导线之间会有电容C存在，如本技术领域的普通技术人员所共知的，此RC值愈小代表较短的延迟时间。
纯铝的电阻系数约为2.7微欧姆-厘米，而铜金属的电阻系数却约为1.7微欧姆-厘米左右，要远小于铝金属。所以，为有效降低阻抗率，铜材料为更佳的选择。由于铜具有低电阻的特性，因此以铜为导线的组件可承受更密集的电路排列，如此可大大减少所需金属层的数目，进而降低生产成本且提高电脑的运算速度。此外，铜还具有较高的电子迁移阻力(Electromigration Resistance)，因此以铜为导线的组件具有更高的寿命以及稳定性。
但是，铜金属的一些化学性质却限制了铜加工工艺在集成电路上的发展。举例来说，铜原子具有快速的扩散性，在电场的加速下，铜原子能穿透介电层而快速的扩散，尤其是一旦铜原子扩散至硅基材中，会引发形成深层能阶受体(Deep Level Acceptor)，造成组件的特性退化与失效。因此，在铜金属层形成前，需要先形成防止铜和氧化层或硅层接触的阻障层(Barrier Layer)，以避免铜扩散或催化等污染。阻障层的另一项作用是用来提升金属与其它材质的附着力。一般阻障层材料可分为金属阻障材料以及介电阻障层材料等，常见的阻障层材料例如有钽(Ta)、氮化钽(TaN)、氮化钛(TiN)等等。
铜材料无法用传统的干式蚀刻技术来进行导线布植，因此目前工业界大部分采用新一代的导线制作技术镶嵌(Damascene)法来做铜导线的填充。图1至图6所示为现有铜金属镶嵌工艺的剖面示意图。
请参照图1，首先提供基材10，并在基材10上形成介电层12。接着，利用微影蚀刻方式，在介电层12形成开口，并在开口内填满金属材料，即可形成金属插塞14。此金属插塞14用来连接不同层的组件或金属层。
接着，请参照图2，依序在介电层上形成蚀刻终止层16与另一介电层18。并随后利用微影蚀刻方式，在介电层12形成开口20，而暴露出金属插塞14，如图3所示。之后，为防止铜金属的扩散，会在形成铜金属层之前，先在开口20中形成一层阻障层22，如图4所示。随后，再在开口20中填满铜金属层24，以作为另一层金属联机结构。
由于阻障材料的导电性质不同，例如金属阻障材料与介电阻障材料，因此形成阻障层22后再填满铜金属层24的工艺与结构也不尽相同。如果利用金属阻障材料来构成图4的阻障层22，由于金属阻障材料并不影响开口中铜金属与金属插塞14的导通，因此可接着在阻障层22上形成一层铜金属材料，并填满开口20。随后，再利用化学机械研磨，将介电层18上多余的铜金属材料与阻障层22去除，而形成如图5所示的结构。又如果利用介电阻障材料来构成图4的阻障层22，由于介电阻障材料无法导电，则必须先利用回蚀刻将开口24中覆盖在金属插塞14上的部分阻障层22去除，同时也去除了介电层18上的多余阻障层22。随后，再形成铜金属材料，并利用化学机械研磨将介电层18上的多余铜金属材料去除，而形成如图6所示的结构。
在上述利用介电材料构成阻障层的图6结构中，在铜金属层24两旁的阻障层22可用来阻障铜原子的扩散，但是在加工暴露金属插塞14表面的同时，却将开口底部阻挡铜金属层与介电层12接触的部分阻障层22也同时去除。因此，如区域26所示，因为有部分的铜金属层24与介电层12接触，所以很容易发生铜原子的扩散现象。
发明内容
鉴于上述的现有技术中，利用介电材料构成铜加工工艺中的阻障层时，很容易发生铜原子的扩散现象，因此，本发明的目的在于提供一种铜金属镶嵌工艺及其结构，其先在介电层上形成蚀刻终止层，接着再在介电层与蚀刻终止层中形成金属插塞。如此，当后续加工暴露开口中的金属插塞结构时，所同时暴露出的即为金属插塞旁的蚀刻终止层。当铜金属与蚀刻终止层接触时，可利用蚀刻终止层的阻障特性来防止铜原子的扩散。
根据上述目的，本发明的铜金属镶嵌结构包括：一基材；一位于基材上的第一介电层；一位于第一介电层上的沉积层，该沉积层由碳氧化硅构成；至少一个位于沉积层与第一介电层中的金属插塞；一位于沉积层上的第二介电层；至少一个位于第二介电层中的铜金属层以及位于铜金属层的外侧壁的阻障层，其中，铜金属层的底部位于该沉积层中以与金属插塞相互接触。
在本发明的优选实施例中，上述铜金属层的底部可位于沉积层的表面或位于沉积层中。并且，当铜原子与沉积层接触时，可利用沉积层的阻障特性来防止铜原子的扩散。
采用本发明的优点在于：
1、由于本发明的金属插塞除了位于介电层中外，还位于蚀刻终止层中。因此，为暴露金属插塞而形成的开口底部会位于蚀刻终止层的表面或位于蚀刻终止层中，而暴露金属插塞的同时，有可能暴露的是金属插塞两旁的蚀刻终止层。所以在开口中形成铜金属时，铜金属层利用阻障层与蚀刻终止层与四周的介电层作隔离，并不会互相接触，而可避免现有技术中铜原子扩散的缺点。
2、本发明先在介电层上形成蚀刻终止层后，去除部分的介电层与蚀刻终止层而形成金属插塞的开口结构。因此，可使得后续形成的金属插塞表面并不像现有的结构那样位于蚀刻终止层下方，而是与蚀刻终止层具有同样水平的表面。所以，当后续阻障层的回蚀刻加工以暴露出金属插塞时，所同时暴露出的为蚀刻终止层，而非介电层。当铜金属层与具有阻障效果的蚀刻终止层接触时，并不会发生现有技术中的铜原子扩散现象。
3、利用一般工艺设备与步骤即可进行本发明的工艺与形成本发明的结构，无需再另外添购设备或增加不兼容的步骤。并且，利用上述本发明的铜金属镶嵌工艺及其结构，可避免铜金属扩散到底部的介电层中，并可因此具有降低铜金属层漏电流(Leakage)、改善时间关联介电崩溃(Time Dependent DielectricBreakdown；TDDB)的特性、降低RC延迟等优点。
附图说明
本发明的优选实施例将在之后的说明文字中辅以下列附图做更详细的阐述，其中：
图1至图6所示为现有铜金属镶嵌工艺的剖面示意图；以及
图7至图10所示为依据本发明一优选实施例的铜金属镶嵌工艺的剖面示意图。
具体实施方式
为了使本发明的叙述更加详尽与完备，可参照下列描述并配合图7至图10的标号。图7至图10所示为依据本发明一优选实施例的铜金属镶嵌工艺的剖面示意图。
请参照图7，首先提供基材100，此基材100可为一般的硅基材，或者已制造有其它组件的硅基材。接着，在基材100上依序沉积厚度约介于5000埃至10000埃之间的介电层102以及厚度约为500埃的蚀刻终止层104。其中，介电层102的目的是作为金属层间的绝缘，其材质可例如磷硅玻璃(PSG)与四乙基硅酸盐(Tetra-Ethyl-Ortho-Silicate；TEOS)等等。
接着，再利用例如微影蚀刻等方式，在介电层102与蚀刻终止层中形成开口，并在开口内填满例如钨等金属材料，即可形成具有暴露表面的金属插塞106。当基材100上有其它组件或金属层时，此金属插塞106结构是为连接不同层的组件或金属层而形成。
请参照图8，接着，在蚀刻终止层104上形成由例如低介电系数材料所构成的另一介电层108，并在介电层108中利用例如微影蚀刻工艺，而形成例如为沟渠(Trench)或介层窗(Via)等的开口120结构，以暴露出位于底下的金属插塞106。在图8的蚀刻步骤中，除了去除部分的介电层108以暴露出金属插塞106表面外，较佳地还可再往下去除少部分的蚀刻终止层104与金属插塞106，使得开口120的底部介于蚀刻终止层104中间。
在本发明一优选实施例中，上述蚀刻终止层104的厚度约为500埃，而介电层108的厚度约介于2500埃至3000埃之间，因此，较佳的开口120深度约介于2800埃至3300埃之间，如此可使得使得开口120的底部介于蚀刻终止层104中间。
请参照图9，接着，在介电层108上与开口120表面形成由介电材料所构成的阻障层122，此阻障层122的厚度约为300埃。随后，进行一回蚀刻步骤，将位于介电层108表面以及开口120底部的多余阻障层122去除，而暴露出金属插塞106。并且，由于位于开口120底部的部分阻障层122被去除，因此在暴露金属插塞106的同时，也暴露出两旁与金属插塞106接触的部分蚀刻终止层104。
接着，在介电层108上形成一层铜金属层124，此铜金属层并填满开口120。随后，再利用例如化学机械研磨，将介电层108表面上的多余铜金属层124去除，而形成如图10所示的结构。其中，由于铜金属层124的形成方式并非本发明的重点，且为本技术领域普通技术人员所知晓，故本发明在此不再赘述。
由于阻障层122与蚀刻终止层104皆需具备阻障特性，并且在回蚀刻步骤中，蚀刻终止层104与阻障层122之间必须具备较高的蚀刻选择比，才能使蚀刻工艺易于进行。因此在本发明一优选实施例中，利用碳氧化硅(SiOC)作为蚀刻终止层104的材质，以及利用碳化硅(SiC)作为阻障层122的材质，可具有较佳的阻障效果并使加工易于进行。但值得注意的是，上述蚀刻终止层与阻障层的材质仅为举例，可视需要而加以改变，本发明并不限于此。并且，上述的蚀刻终止层仅为举例，具有其它功效却位于相同位置的沉积层，也可应用于本发明中，本发明也不限于此。
如本技术领域的普通技术人员所了解的，以上所述仅为本发明的优选实用例而已，并非用来限定本发明的权利要求范围。凡是其它未脱离本发明所揭示的构思下所完成的等效变化或修改，均应包含在所附的权利要求范围内。
Claims (4)
1、一种铜金属镶嵌结构，其特征在于，其至少包括：
一基材；
一位于该基材上的第一介电层；
一位于该第一介电层上的沉积层，该沉积层由碳氧化硅构成；
至少一个位于该沉积层与该第一介电层中的金属插塞；
一位于该沉积层上的第二介电层；
至少一个位于该第二介电层中且其底部位于该沉积层中以与该金属插塞接触的铜金属层；以及
一位于该铜金属层的外侧壁的阻障层。
2、如权利要求1所述的铜金属镶嵌结构，其特征在于：上述的阻障层由一介电阻障材料构成。
3、如权利要求1所述的铜金属镶嵌结构，其特征在于：上述的沉积层为一蚀刻终止层。
4、如权利要求1所述的铜金属镶嵌结构，其特征在于：上述的沉积层的厚度为500埃。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/459,222 US7151315B2 (en) | 2003-06-11 | 2003-06-11 | Method of a non-metal barrier copper damascene integration |
| US10/459,222 | 2003-06-11 |
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| CN1574281A CN1574281A (zh) | 2005-02-02 |
| CN1326231C true CN1326231C (zh) | 2007-07-11 |
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| CNU2004200667623U Expired - Lifetime CN2731711Y (zh) | 2003-06-11 | 2004-06-10 | 铜金属镶嵌结构 |
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| US (1) | US7151315B2 (zh) |
| CN (2) | CN1326231C (zh) |
| SG (1) | SG141230A1 (zh) |
| TW (1) | TWI231564B (zh) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7151315B2 (en) * | 2003-06-11 | 2006-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of a non-metal barrier copper damascene integration |
| US20060216924A1 (en) * | 2005-03-28 | 2006-09-28 | Zhen-Cheng Wu | BEOL integration scheme for etching damage free ELK |
| US7713865B2 (en) * | 2005-06-24 | 2010-05-11 | International Business Machines Corporation | Preventing damage to metal using clustered processing and at least partially sacrificial encapsulation |
| KR100711912B1 (ko) * | 2005-12-28 | 2007-04-27 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
| US20080260967A1 (en) * | 2007-04-17 | 2008-10-23 | Hyungsuk Alexander Yoon | Apparatus and method for integrated surface treatment and film deposition |
| US7645701B2 (en) * | 2007-05-21 | 2010-01-12 | International Business Machines Corporation | Silicon-on-insulator structures for through via in silicon carriers |
| WO2009014646A1 (en) * | 2007-07-20 | 2009-01-29 | Applied Materials, Inc. | Methods and apparatus to prevent contamination of a photoresist layer on a substrate |
| US7781332B2 (en) * | 2007-09-19 | 2010-08-24 | International Business Machines Corporation | Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer |
| US7737052B2 (en) * | 2008-03-05 | 2010-06-15 | International Business Machines Corporation | Advanced multilayer dielectric cap with improved mechanical and electrical properties |
| JP5654794B2 (ja) * | 2010-07-15 | 2015-01-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US8420531B2 (en) | 2011-06-21 | 2013-04-16 | International Business Machines Corporation | Enhanced diffusion barrier for interconnect structures |
| JP6041527B2 (ja) * | 2012-05-16 | 2016-12-07 | キヤノン株式会社 | 液体吐出ヘッド |
| CN104347477B (zh) * | 2013-07-24 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
| US9219033B2 (en) * | 2014-03-21 | 2015-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via pre-fill on back-end-of-the-line interconnect layer |
| US10916503B2 (en) | 2018-09-11 | 2021-02-09 | International Business Machines Corporation | Back end of line metallization structure |
| US11398406B2 (en) * | 2018-09-28 | 2022-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective deposition of metal barrier in damascene processes |
| US11637036B2 (en) * | 2020-01-30 | 2023-04-25 | International Business Machines Corporation | Planarization stop region for use with low pattern density interconnects |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261963B1 (en) * | 2000-07-07 | 2001-07-17 | Advanced Micro Devices, Inc. | Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices |
| US6380084B1 (en) * | 2000-10-02 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling |
| WO2002078060A2 (en) * | 2001-03-27 | 2002-10-03 | Advanced Micro Devices, Inc. | Damascene processing using dielectric barrier films |
| US6489233B2 (en) * | 2000-02-25 | 2002-12-03 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formations for copper damascene type interconnects |
| CN2731711Y (zh) * | 2003-06-11 | 2005-10-05 | 台湾积体电路制造股份有限公司 | 铜金属镶嵌结构 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4860067A (en) | 1986-06-20 | 1989-08-22 | International Business Machines Corporation | Semiconductor heterostructure adapted for low temperature operation |
| EP0560617A3 (en) | 1992-03-13 | 1993-11-24 | Kawasaki Steel Co | Method of manufacturing insulating film on semiconductor device and apparatus for carrying out the same |
| US5441765A (en) | 1993-09-22 | 1995-08-15 | Dow Corning Corporation | Method of forming Si-O containing coatings |
| GB9413141D0 (en) | 1994-06-30 | 1994-08-24 | Exploration And Production Nor | Downhole data transmission |
| US5880108A (en) | 1995-02-14 | 1999-03-09 | Bioniche, Inc. | Method for treating the internal urinary bladder and associated structures using hyaluronic acid |
| US5759906A (en) | 1997-04-11 | 1998-06-02 | Industrial Technology Research Institute | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
| US5858869A (en) | 1997-06-03 | 1999-01-12 | Industrial Technology Research Institute | Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers |
| US6124198A (en) | 1998-04-22 | 2000-09-26 | Cvc, Inc. | Ultra high-speed chip interconnect using free-space dielectrics |
| US6159871A (en) | 1998-05-29 | 2000-12-12 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
| US6333560B1 (en) | 1999-01-14 | 2001-12-25 | International Business Machines Corporation | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies |
| US6436824B1 (en) | 1999-07-02 | 2002-08-20 | Chartered Semiconductor Manufacturing Ltd. | Low dielectric constant materials for copper damascene |
| US6566258B1 (en) | 2000-05-10 | 2003-05-20 | Applied Materials, Inc. | Bi-layer etch stop for inter-level via |
| US6774489B2 (en) * | 2000-08-29 | 2004-08-10 | Texas Instruments Incorporated | Dielectric layer liner for an integrated circuit structure |
| JP2002110679A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US6696360B2 (en) * | 2001-03-15 | 2004-02-24 | Micron Technology, Inc. | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
| US6518184B1 (en) | 2002-01-18 | 2003-02-11 | Intel Corporation | Enhancement of an interconnect |
| JP4340040B2 (ja) * | 2002-03-28 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP3974023B2 (ja) * | 2002-06-27 | 2007-09-12 | 富士通株式会社 | 半導体装置の製造方法 |
| US6525428B1 (en) | 2002-06-28 | 2003-02-25 | Advance Micro Devices, Inc. | Graded low-k middle-etch stop layer for dual-inlaid patterning |
| US6770570B2 (en) * | 2002-11-15 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer |
-
2003
- 2003-06-11 US US10/459,222 patent/US7151315B2/en not_active Expired - Lifetime
- 2003-11-06 TW TW092131134A patent/TWI231564B/zh not_active IP Right Cessation
- 2003-11-11 CN CNB200310116392XA patent/CN1326231C/zh not_active Expired - Lifetime
-
2004
- 2004-06-09 SG SG200403599-4A patent/SG141230A1/en unknown
- 2004-06-10 CN CNU2004200667623U patent/CN2731711Y/zh not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489233B2 (en) * | 2000-02-25 | 2002-12-03 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formations for copper damascene type interconnects |
| US6261963B1 (en) * | 2000-07-07 | 2001-07-17 | Advanced Micro Devices, Inc. | Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices |
| US6380084B1 (en) * | 2000-10-02 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling |
| WO2002078060A2 (en) * | 2001-03-27 | 2002-10-03 | Advanced Micro Devices, Inc. | Damascene processing using dielectric barrier films |
| CN2731711Y (zh) * | 2003-06-11 | 2005-10-05 | 台湾积体电路制造股份有限公司 | 铜金属镶嵌结构 |
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| Publication number | Publication date |
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| US20040251547A1 (en) | 2004-12-16 |
| CN2731711Y (zh) | 2005-10-05 |
| TWI231564B (en) | 2005-04-21 |
| CN1574281A (zh) | 2005-02-02 |
| TW200428576A (en) | 2004-12-16 |
| SG141230A1 (en) | 2008-04-28 |
| US7151315B2 (en) | 2006-12-19 |
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