JP5305651B2 - 回路の配線構造および集積回路の配線構造の製作方法 - Google Patents
回路の配線構造および集積回路の配線構造の製作方法 Download PDFInfo
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- JP5305651B2 JP5305651B2 JP2007509628A JP2007509628A JP5305651B2 JP 5305651 B2 JP5305651 B2 JP 5305651B2 JP 2007509628 A JP2007509628 A JP 2007509628A JP 2007509628 A JP2007509628 A JP 2007509628A JP 5305651 B2 JP5305651 B2 JP 5305651B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 28
- 239000003989 dielectric material Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 68
- 239000002184 metal Substances 0.000 description 27
- 239000011229 interlayer Substances 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- BVKZGUZCCUSVTD-UHFFFAOYSA-L Carbonate Chemical compound [O-]C([O-])=O BVKZGUZCCUSVTD-UHFFFAOYSA-L 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
- H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
C=1/(1/CA1+1/CD+1/CA2)
各静電容量は、C=εA/dで表すことができ、εは材料の誘電率、Aは側面断面積、dは材料の厚さである。空気の誘電率をε=1とすると、(単位断面積当たりの)層内静電容量C/Aは次式によって与えられる。
C/A=(2dA+dD/ε)−1
ここで、dAは各空隙の厚さ、dDは部分13cの厚さ(すなわち、金属線25−1と25−2との間の層13の側方向の寸法)である。層11および13が二酸化シリコン(ε=3.85)から成り、リソグラフィのグランドルールが0.16μmであるとすると、様々な幅の空隙の静電容量は以下のようになる。
Claims (5)
- 集積回路の配線構造を製作する方法であって、
第1の誘電材料層および第2の誘電材料層と、前記第1の誘電材料層および第2の誘電材料層の間に前記第2の誘電材料層よりも誘電率の低い第1の低誘電材料層とを形成するステップと、
前記第2の誘電材料層および前記第1の低誘電材料層に、各々が側壁と底部とを有する複数のフィーチャを形成するステップと、
前記側壁にスペーサを形成するステップと、
前記スペーサによって前記側壁から分離された導体を前記フィーチャ内に形成するステップと、
前記スペーサを除去することによって、前記導体が空隙によって前記側壁から分離されるように前記側壁のところに前記空隙を形成するステップと、
前記第2の誘電材料層よりも誘電率の低い第2の低誘電材料層を、前記第2の誘電材料層および前記導体を覆うように形成するステップと
を含み、
前記フィーチャを形成するステップは、前記第1の低誘電材料層をオーバーエッチングすることにより、前記第1の誘電材料層から前記第1の低誘電材料層へ延びる導電スタッドを露出させ、
導体を前記フィーチャ内に形成するステップにより、前記導電スタッドへの電気的接続が行われる、方法。 - 前記スペーサを形成する前記ステップは、
各フィーチャの側壁および底部上にスペーサ材料の層を付着させるステップと、
方向性エッチング・プロセスを使用して前記底部から前記スペーサ材料を除去するステップとを含む請求項1に記載の方法。 - 前記導体を形成する前記ステップは、前記各スペーサの上部表面部を露出させるステップをさらに含み、
前記スペーサを除去する前記ステップは、前記第2の誘電材料層の上面部をエッチング剤に晒すステップを含む請求項1または2に記載の方法。 - 前記フィーチャは、リソグラフィ寸法を特徴とするリソグラフィ・プロセスを用いて形成され、前記スペーサは前記リソグラフィ寸法未満の水平方向の寸法で形成される請求項1〜3のいずれか1項に記載の方法。
- 前記スペーサは、各導体がその上部が底部よりも広くなるように、前記フィーチャの底部近傍が前記フィーチャの上部近傍よりも大きい水平方向の寸法で形成される請求項1〜4のいずれか1項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/709,204 | 2004-04-21 | ||
US10/709,204 US20050239284A1 (en) | 2004-04-21 | 2004-04-21 | Wiring structure for integrated circuit with reduced intralevel capacitance |
PCT/US2005/013601 WO2005104212A2 (en) | 2004-04-21 | 2005-04-21 | Wiring structure for integrated circuit with reduced intralevel capacitance |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007534178A JP2007534178A (ja) | 2007-11-22 |
JP2007534178A5 JP2007534178A5 (ja) | 2008-05-08 |
JP5305651B2 true JP5305651B2 (ja) | 2013-10-02 |
Family
ID=35137032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007509628A Expired - Fee Related JP5305651B2 (ja) | 2004-04-21 | 2005-04-21 | 回路の配線構造および集積回路の配線構造の製作方法 |
Country Status (9)
Country | Link |
---|---|
US (2) | US20050239284A1 (ja) |
EP (1) | EP1743366B1 (ja) |
JP (1) | JP5305651B2 (ja) |
KR (1) | KR20070008599A (ja) |
CN (1) | CN1943023B (ja) |
AT (1) | ATE504079T1 (ja) |
DE (1) | DE602005027195D1 (ja) |
TW (1) | TW200539281A (ja) |
WO (1) | WO2005104212A2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101471324B (zh) * | 2007-12-26 | 2010-07-07 | 和舰科技(苏州)有限公司 | 一种超低k互连结构及其制造方法 |
US8497203B2 (en) | 2010-08-13 | 2013-07-30 | International Business Machines Corporation | Semiconductor structures and methods of manufacture |
US8492270B2 (en) | 2010-09-20 | 2013-07-23 | International Business Machines Corporation | Structure for nano-scale metallization and method for fabricating same |
US8957519B2 (en) | 2010-10-22 | 2015-02-17 | International Business Machines Corporation | Structure and metallization process for advanced technology nodes |
US8735279B2 (en) | 2011-01-25 | 2014-05-27 | International Business Machines Corporation | Air-dielectric for subtractive etch line and via metallization |
CN103094183B (zh) * | 2011-10-29 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
CN103117244B (zh) * | 2011-11-16 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Ic内连线和层间介质层之间的空气间隔形成方法 |
CN102931127A (zh) * | 2012-10-10 | 2013-02-13 | 哈尔滨工程大学 | 一种抗辐射加固浅槽隔离结构形成方法 |
US9431294B2 (en) * | 2014-10-28 | 2016-08-30 | GlobalFoundries, Inc. | Methods of producing integrated circuits with an air gap |
US10770539B2 (en) * | 2018-09-25 | 2020-09-08 | Nxp B.V. | Fingered capacitor with low-K and ultra-low-K dielectric layers |
US11094632B2 (en) * | 2019-09-27 | 2021-08-17 | Nanya Technology Corporation | Semiconductor device with air gap and method for preparing the same |
Family Cites Families (21)
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US5372969A (en) * | 1991-12-31 | 1994-12-13 | Texas Instruments Incorporated | Low-RC multi-level interconnect technology for high-performance integrated circuits |
US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
US5783481A (en) * | 1996-06-05 | 1998-07-21 | Advanced Micro Devices, Inc. | Semiconductor interlevel dielectric having a polymide for producing air gaps |
US5792706A (en) * | 1996-06-05 | 1998-08-11 | Advanced Micro Devices, Inc. | Interlevel dielectric with air gaps to reduce permitivity |
US5880026A (en) * | 1996-12-23 | 1999-03-09 | Texas Instruments Incorporated | Method for air gap formation by plasma treatment of aluminum interconnects |
JP2962272B2 (ja) * | 1997-04-18 | 1999-10-12 | 日本電気株式会社 | 半導体装置の製造方法 |
US6242336B1 (en) * | 1997-11-06 | 2001-06-05 | Matsushita Electronics Corporation | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
US6211561B1 (en) * | 1998-11-16 | 2001-04-03 | Conexant Systems, Inc. | Interconnect structure and method employing air gaps between metal lines and between metal layers |
JP4134405B2 (ja) * | 1998-11-20 | 2008-08-20 | 沖電気工業株式会社 | 半導体素子の製造方法及び半導体素子 |
TW411570B (en) * | 1999-02-02 | 2000-11-11 | Nanya Technology Corp | Manufacturing method of self-aligned contact |
US6177329B1 (en) * | 1999-04-15 | 2001-01-23 | Kurt Pang | Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets |
US6342722B1 (en) * | 1999-08-05 | 2002-01-29 | International Business Machines Corporation | Integrated circuit having air gaps between dielectric and conducting lines |
GB0001179D0 (en) * | 2000-01-19 | 2000-03-08 | Trikon Holdings Ltd | Methods & apparatus for forming a film on a substrate |
TW444342B (en) * | 2000-02-17 | 2001-07-01 | United Microelectronics Corp | Manufacturing method of metal interconnect having inner gap spacer |
TW465039B (en) * | 2000-11-06 | 2001-11-21 | United Microelectronics Corp | Void-type metal interconnect and method for making the same |
US6380106B1 (en) * | 2000-11-27 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures |
US6936533B2 (en) * | 2000-12-08 | 2005-08-30 | Samsung Electronics, Co., Ltd. | Method of fabricating semiconductor devices having low dielectric interlayer insulation layer |
US6448177B1 (en) * | 2001-03-27 | 2002-09-10 | Intle Corporation | Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure |
KR100460771B1 (ko) * | 2001-06-30 | 2004-12-09 | 주식회사 하이닉스반도체 | 듀얼다마신 공정에 의한 다층 배선의 형성 방법 |
JP2003163266A (ja) * | 2001-11-28 | 2003-06-06 | Sony Corp | 半導体装置の製造方法および半導体装置 |
US6806534B2 (en) * | 2003-01-14 | 2004-10-19 | International Business Machines Corporation | Damascene method for improved MOS transistor |
-
2004
- 2004-04-21 US US10/709,204 patent/US20050239284A1/en not_active Abandoned
-
2005
- 2005-04-06 TW TW094110922A patent/TW200539281A/zh unknown
- 2005-04-21 DE DE602005027195T patent/DE602005027195D1/de active Active
- 2005-04-21 CN CN2005800110922A patent/CN1943023B/zh not_active Expired - Fee Related
- 2005-04-21 JP JP2007509628A patent/JP5305651B2/ja not_active Expired - Fee Related
- 2005-04-21 AT AT05746299T patent/ATE504079T1/de not_active IP Right Cessation
- 2005-04-21 EP EP05746299A patent/EP1743366B1/en not_active Not-in-force
- 2005-04-21 WO PCT/US2005/013601 patent/WO2005104212A2/en active Application Filing
- 2005-04-21 KR KR1020067019469A patent/KR20070008599A/ko not_active Application Discontinuation
- 2005-08-15 US US11/203,944 patent/US7329602B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1743366A4 (en) | 2009-11-11 |
CN1943023B (zh) | 2010-09-29 |
US20060035460A1 (en) | 2006-02-16 |
EP1743366A2 (en) | 2007-01-17 |
CN1943023A (zh) | 2007-04-04 |
TW200539281A (en) | 2005-12-01 |
US20050239284A1 (en) | 2005-10-27 |
US7329602B2 (en) | 2008-02-12 |
EP1743366B1 (en) | 2011-03-30 |
KR20070008599A (ko) | 2007-01-17 |
WO2005104212A3 (en) | 2006-07-20 |
ATE504079T1 (de) | 2011-04-15 |
WO2005104212A2 (en) | 2005-11-03 |
DE602005027195D1 (de) | 2011-05-12 |
JP2007534178A (ja) | 2007-11-22 |
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