CN101312161B - 电子结构及其制造方法 - Google Patents

电子结构及其制造方法 Download PDF

Info

Publication number
CN101312161B
CN101312161B CN2008100952822A CN200810095282A CN101312161B CN 101312161 B CN101312161 B CN 101312161B CN 2008100952822 A CN2008100952822 A CN 2008100952822A CN 200810095282 A CN200810095282 A CN 200810095282A CN 101312161 B CN101312161 B CN 101312161B
Authority
CN
China
Prior art keywords
layer
ground floor
insulating material
semi
conducting material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008100952822A
Other languages
English (en)
Other versions
CN101312161A (zh
Inventor
布伦特·A·安德森
埃德蒙·J·斯普罗吉斯
保罗·S·安德里
科尼莉亚·K·唐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101312161A publication Critical patent/CN101312161A/zh
Application granted granted Critical
Publication of CN101312161B publication Critical patent/CN101312161B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种电子结构及其制造方法。提供了一种用于在硅晶片载体结构中不使用背面光刻形成贯穿通路的绝缘体上硅(SOI)结构。所述SOI结构包括接合到硅衬底结构的硅晶片载体结构，掩埋氧化物层和氮化物层分离这些硅结构。通路形成于所述硅载体结构中并且贯穿所述氧化物层至所述氮化物层并且所述通路的壁被钝化。所述通路用多晶硅或导电材料的填充材料填充。所述衬底结构随后被回蚀刻至所述氮化物层并且所述氮化物层被回蚀刻至所述填充材料。在填充材料是多晶硅的情形，所述多晶硅被蚀刻掉，形成至所述载体晶片结构的顶表面的开通路。随后用导电材料回填所述通路。

Description

电子结构及其制造方法 
技术领域
本发明涉及电互连通路结构以及以材料(例如半导体材料)制造电互连通路结构的方法。更具体地，本发明涉及导电贯穿通路(through via)结构及其制造方法，在例如半导体晶片、半导体芯片、元件等电子器件结构中和这样的半导体晶片、芯片、元件的电子器件的载体中。 
背景技术
在电子器件，例如半导体芯片或晶片的封装中，器件载体可以用于互连器件。在电子器件连接至另一层的封装的情形，载体典型地需要延伸穿过载体的导电通路从而连接器件至封装的下一层。 
电子器件载体可以用各种不同的材料制造，例如玻璃、陶瓷、有机和半导体材料或这些和其它材料以单或多层的组合。 
由例如硅的半导体材料制成的电子器件载体在封装上提供了许多优点，例如便于制造以及可靠性和高连接密度。该技术的挑战之一是需要在晶片的背侧进行复杂的工艺。当在例如硅的半导体载体的背侧进行时，涉及光刻、RIE蚀刻等的传统的复杂的工艺步骤可以变得困难得多并且成本昂贵。 
一种在例如硅的半导体载体中产生导电通路的现有的方案使用可以称之为“通路优先”的方案。在这样的方案中的通常的步骤是蚀刻通路，在通路壁上形成绝缘层并且金属化。当使用“盲通路”方案时，通路不被蚀刻贯穿晶片层，使得仅在载体被恰当地减薄以暴露通路底部之后，成为“贯穿通路”。这样的方案的实例可以在美国专利No.5,998,292中看到。 
但是该类型的方案具有许多难点。例如，一个难点是控制垂直结构尺寸。另一难点是控制工艺步骤的背侧减薄深度停止和隔离。 
一些在半导体载体中产生贯穿通路的方案可能需要背侧光刻工艺和蚀刻步骤。在硅载体的背侧的这样的工艺增加了工艺的复杂性。作为实例，于2005年8月提交的并且转让给本发明的受让人的美国申请No.11/214,602，在晶片中形成贯穿通路上使用了在硅晶片的背侧上的光刻和RIE步骤。 
发明内容
本发明的目的是提供改善的电子结构及其制造方法。 
本发明的另一目的是提供改善的电子封装的导电通路结构的制造方法。 
本发明的又一目的是提供贯穿通路结构及其制造方法，该方法简化了制造并且改善了封装的电子器件的产率和可靠性。 
本发明的又一目的是提供贯穿通路结构及其制造方法，其容易地允许通路在例如芯片载体结构的单电子结构上制造为均匀深度的不同直径。 
本发明的又一目的是提供改善的贯穿通路结构及其制造方法，其从前侧线后端(BEOL)金属化工艺中分离通路金属化工艺步骤。 
本发明的又一目的是提供在使用提供了控制的深度停止和隔离的绝缘体上硅(SOI)晶片结构的硅载体中的贯穿导电通路结构的制造工艺，并且简化背侧工艺并且其中所有的结构都是自对准的并且结构的垂直尺寸受到严密的控制。 
这些，以及其它的目的，在本发明中通过使用通过至少两层绝缘层结合在一起的一对半导体结构，从而形成掩埋绝缘结构而形成导电贯穿通路。更具体地，本发明的方法包括的步骤是： 
提供半导体结构，该半导体结构包括：具有第一和第二表面的半导体材料的第一层和具有第一和第二表面的半导体材料的第二层，其通过绝缘材料的第一层和绝缘材料的第二层接合在一起，所述绝缘材料的第一层夹置于所述绝缘材料的第二层和所述半导体材料的第一层的第二表面之间，并且所述绝缘材料的第二层夹置于所述绝缘材料的第一层和所述的第二层的第二表面之间； 
在所述半导体材料的第一层中形成通路，所述通路具有从所述半导体材料的第一层的第一表面延伸贯穿所述绝缘材料的第一层至所述绝缘材料的第二层的壁表面； 
在所述通路的所述壁表面上形成绝缘材料层； 
用另一材料填充所述通路； 
回蚀刻所述半导体材料的第二层至所述绝缘材料的第二层；并且 
蚀刻所述绝缘材料的第二层从而暴露另一材料。 
如本发明进一步提供的，其中在所述通路的所述壁表面上的所述绝缘材料层由与所述绝缘材料的第一层相同的绝缘材料制成。 
如本发明进一步提供的，其中所述半导体材料的第一层和所述半导体材料的第二层都是硅。 
如本发明进一步提供的，还包括在所述另一材料上提供导电布线材料的步骤。 
如本发明进一步提供的，其中所述另一材料是导电材料。 
如本发明进一步提供的，其中所述另一材料是多晶硅。 
如本发明进一步提供的，所述方法包括的步骤是： 
提供SOI晶片结构，该结构至少包括在硅晶片和硅衬底之间形成的绝缘材料的第一层和绝缘材料的第二层，绝缘材料上的所述第一层与所述硅晶片接触； 
从所述硅晶片的顶表面蚀刻通路贯穿至所述第一绝缘层； 
蚀刻贯穿所述绝缘材料的第一层； 
在所述被蚀刻的通路的侧壁上形成由与所述绝缘材料的第一层相同的材料制成的绝缘层； 
用多晶硅材料填充所述通路并且平坦化至所述硅晶片的所述顶表面； 
在所述多晶硅材料的上方形成导电金属结构；并且随后 
通过蚀刻去除所述硅衬底；随后 
通过蚀刻去除所述绝缘材料的第二层；随后 
通过蚀刻去除所述多晶硅材料从而再次形成开口通路；并且 
在所述通路中形成导电材料从而连接至所述导电金属结构。 
如本发明还提供的，形成例如焊料凸块的电触点，与在所述通路中的所述导电材料接触。 
如本发明进一步提供的，根据描述的SOI的工艺步骤，内部布线沟道形成于导电通路之间。 
在本发明的一实施例中，提供了其上形成有氮化物层的硅衬底的SOI结构。氧化物层形成于所述氮化物层上并且硅载体晶片贴附至所述氮化物层。形成贯穿硅载体晶片和掩埋的氧化物层至氮化物层的通路的壁被氧化并且用另一材料回填。随后在所述另一材料上方形成金属结构。 
在本发明的另一实施例中，上述硅衬底被去除，剩下所述氮化物层。氮化物层随后被去除，剩下所述另一材料。所述另一材料的去除形成至所述金 属结构的开通路。回填入通路的导电材料提供至所述金属结构的电连接。焊料凸块与形成于通路内的导电材料接触，从而允许例如至衬底的连接。这样形成的晶片提供了相对厚的硅载体。 
在另一实施例中，上述回填的另一材料是导电材料，由此提供了至所述金属结构的电连接，而不需要背侧通路蚀刻和用导电材料回填。 
在本发明的又一实施例中，硅载体晶片背侧提供有背侧布线。 
在本发明的又一实施例中，通路首先在硅载体晶片中从背侧产生并且在接合到硅衬底之前填充以多晶硅。 
在本发明的另一实施例中，硅载体晶片被提供有互连导电通路的内部布线沟道。 
附图说明
图1A-1K示出了根据本发明一实施例的制造载体结构的一系列工艺步骤。 
图2A-2L示出了根据本发明另一实施例的制造载体结构的一系列工艺步骤。 
图3A-3O示出了根据本发明又一实施例的制造载体结构的一系列工艺步骤。 
图4A-4C示出了根据本发明又一实施例的制造载体结构的一系列工艺步骤。 
图5A-5B示出了根据本发明又一实施例的制造载体结构的进一步的工艺步骤。 
图6A-6C示出了根据本发明又一实施例的制造载体结构的步骤。 
具体实施方式
根据本发明，通过使用绝缘体上硅，提供了在电子器件结构(例如半导体晶片和芯片结构等)及其电器件载体中的导电贯穿通路。根据更具体的描述，可以使用绝缘体上硅(SOI)结构。多层SOI绝缘体结构被用于提供在硅晶片中形成通路和沟道的背面无光刻工艺。SOI晶片结构工艺提供在贯穿通路形成中的受控的深度停止和隔离并且简化可以例如在硅载体技术中采用的背侧工艺。 
尽管在下列描述中就电子器件硅载体结构而言描述了通路结构及其制造方法，但是应当理解通路结构及其制造方法也可以在其它电子结构中形成，例如有源器件芯片和晶片结构。例如通路结构及其制造方法可以用于器件堆叠，例如晶片对晶片堆叠和芯片对芯片堆叠。显见本发明所界定的通路结构及其制造方法可以在任何种类的电子器件结构中被采用，例如具有背侧接触要求的图像传感器。尽管提及了硅结构，但是显见也可以使用其它半导体材料的结构。 
参考图1A-1K，示出了根据本发明一实施例，描绘制造这样的载体中的导电贯穿通路结构的工艺的硅载体晶片的一部分的一系列截面图。硅载体晶片的一部分的截面图，如在图1A至1I中所示出的，展示了一贯穿通路可以如何制造的。图1J和1K示出了从硅载体晶片切割的硅裸芯中的通路的截面图。清楚的是多个这样的通路可以同时在硅晶片载体或裸芯中制造，例如，使用这样的工艺。 
在当前的优选实施例中，载体是硅晶片并且绝缘体是氧化物和氮化物。但是，也可以使用其它的绝缘体。参考图1A，示出了硅衬底3上的硅载体晶片1，掩埋氧化物层5和氮化物层7定位于其之间。典型地，氧化物层5应当为0.5至1.0μm厚并且氮化物层7应当为大约0.1μm厚。氮化物层7可以通过任何熟知的技术，例如CVD而沉积。相似地，氧化物层5可以通过任何的各种熟知的技术，例如热氧化或等离子体增强CVD而形成。在这点上，部分氧化物层5可以首先被沉积在硅晶片1的结合侧9和氮化物层7的另一部分上并且随后晶片1通过加热将氧化物层熔化在一起而接合至衬底3。显然，容易使用其它技术将结构接合在一起。 
如在图1A中所示出的形成多层SOI结构之后，通路11形成于硅晶片1中下至氧化物层5。这通过构图光致抗蚀剂层13从而形成对应于希望的通路的开口尺寸并且使用例如深反应离子蚀刻(RIE)法穿过开口至氧化物层5蚀刻硅而进行。因而，可以使用本领域中已知的通过在等离子体中产生的氟自由基的深硅蚀刻。这样的深硅结构可以使用传统的可以获得的深RIE系统(例如可以从Alcatel获得的A601E)制造。在这一点上，应当注意，根据本发明的工艺，硅载体1可以是例如50μm厚的200mm晶片。 
蚀刻通路11之后，在通路底部中的氧化物层5的被暴露的氧化物被去除，停止于氮化物层7。该氧化物可以通过例如使用HF的蚀刻而被去除。 这在图1C中被示出。 
如在图1D中所示出的，随后使用传统抗蚀剂去除技术剥离抗蚀剂层13。仍然如在图1D中所示出的，通路11的侧壁随后被钝化，从而使用热氧化形成例如1μm厚的氧化物层15。也可以是其它的氧化物厚度。这可以通过例如在管炉中在氧气或蒸气环境中在900℃和1100℃之间进行。通路11随后被填充以导电材料17。导电材料可以是例如镀的铜或钨。用导电材料填充通路之后，材料通过例如化学机械抛光(CMP)平坦化，回到硅载体1的顶表面。 
如在图1E中所示出的，下一步骤涉及线末端(BEOL)布线和接合焊盘结构19的传统硅工艺步骤。通过实例示出了两个布线层，连接至导电材料17的布线层21和连接至焊盘25的布线层23。在本领域中形成这样的布线和接合焊盘结构的技术是熟知的。在这一点上，术语“金属结构”广泛地用于覆盖导电布线和/或接合焊盘和相似于结构19的互连结构。 
为了处理上的方便，临时处理结构27可以贴附于布线和接合焊盘19，如在图1F中所示出的。该处理结构可以是，例如使用粘合剂22接合于布线和接合焊盘结构19的玻璃晶片。 
如在图1G中所示出的，下一步骤涉及从SOI结构的背侧去除硅衬底3的硅。该去除工艺可以通过例如研磨和/或用氮化物层7作为蚀刻停止的向下至氮化物层7的TMAH蚀刻而完成。 
下一步骤涉及从背侧去除掩埋的氮化物层7，如在图1H中所示出的。这可以通过例如反应离子蚀刻(RIE)而完成。也可以使用湿法蚀刻。在这一点上，与布线21接触的通路11中的导体17被暴露。 
如在图1I中所示出的，现在焊料凸块29可以沉积在与导电材料17接触的导电贯穿通路的上方。典型的沉积焊料凸块29的工艺是熟知的C4工艺。 
随后，晶片1可以被切割为单独的裸芯载体4并倒装片接合到衬底31上的触点32，如在图1J中所示出的。随后通过激光切除去除临时玻璃处理器27，如在图1K中所示出的。显然可以采用其它玻璃处理器释放系统，例如具有贯穿孔阵列的玻璃处理器，其允许化学溶剂流过孔从而去除接合粘合剂。去除玻璃处理器之后，采用清洁步骤从而去除在贯穿通路裸芯的顶表面上的残留的聚合物。 
在图1A-1K中所示出的工艺中，应当注意被蚀刻的通路11从多层SOI 绝缘体结构的前侧被填充以导体17。在图2A-2L中所示出的工艺中示出了替代的布置，其中被蚀刻的通路11从前侧被填充以非导体，例如多晶硅，多晶硅是方便的硅工艺材料。在这样的布置中，多晶硅随后从背侧从SOI结构中被去除并且打开的通路随后被填充以导电材料。因而，在该布置中导电通路的形成与BEOL金属化工艺和在晶片的前侧上的前端工艺步骤隔离并且独立。由此，使用该工艺流程的具体的优点是，可以在载体上进行附加的前端工艺步骤，例如建造晶体管器件、电阻、电容等，由于填充了多晶硅的通路仍然可以通过前端步骤而处理，而在这样的情形中填充了金属的通路则典型地不可以。 
因而，在图2A-2L的工艺布置中，图2A-2C与先前对于图1所描述的相同。在这一点上，在各图中使用了相似的参考标号以识别相似的元件。在图2D中，深通路抗蚀剂13被剥离并且侧壁被钝化，如上述对于图1D所描述的。但是，在该情形，通路11被填充以多晶硅33。这可以通过例如CVD而进行。多晶硅的CVD之后，进行多余的材料的蚀刻或CMP从而平坦化表面至硅晶片表面。 
随后进行传统硅工艺步骤从而添加前端器件和BEOL布线和接合焊盘结构，如在图2E中所示出的。在图2E-2G中所示出的结构和步骤与对于图1E-1G所示出和描述的相同。 
如在图2H中所示出的，氮化物层7再次通过RIE被剥离至掩埋的蚀刻停止氧化物层5。在这一点上，通路11中的多晶硅填充栓被暴露。随后多晶硅填充物使用例如TMAH的蚀刻剂被去除，留下打开的通路34至顶侧布线上的布线21和接合焊盘结构19。 
随后打开的通路34被填充以导电材料，例如铜，从而形成导电通路35，如在图2I中所示出的。铜例如可以被镀，并且随后通过CMP被平坦化。 
在图2J-2L中所示出的剩下的步骤与上述对于图1I-1K所示出和描述的相同。因而，图2A-2L包括，去除多晶硅填充物栓和从硅载体晶片背侧用导电材料回填的附加的步骤，如在图2H和2I中所示出的。 
在图3A-3O中所示出的工艺中添加了晶片1的背侧上的附加的布线层，也是不使用背侧光刻。在这样的布置中，在硅晶片1接合于其上之前，硅衬底3首先被构图以具有在至少一侧上的特征。在图3A-3O的布置中，在接合之前，特征首先在硅衬底3的接合侧中被构图。 
因而，如在图3A中所示出的，硅衬底3的接合侧37使用例如TMAH的RIE而被蚀刻，从而形成构图的凹入39。典型地，凹入是0.5μm左右。在图3B中，凹入区39被填充以氧化物41并且使用例如上述工艺而被平坦化。 
平坦化氧化物41之后，毯式氮化物层7和部分氧化物层5的厚度沉积在硅衬底表面和凹入的氧化物41的上方，如在图3C中所示出的。随后在其接合侧具有毯式氧化物的晶片1被接合至衬底3的接合侧37的这样形成的氧化物表面，如在图3D中所示出的，以参考图1A所述的方式。接合步骤因而形成SOI结构的掩埋氧化物层5和氮化物层7。 
在图3E-3I中示出的结构和步骤与在图1B-1F中所示出和描述的相同。但是，如在图3J中所示出的，硅衬底3的硅材料被回蚀刻从而暴露氮化物层7，留下凹入的氧化物41。因而对于布线沟道形成凹入43。为了该目的，可以使用对于硅的高度选择性的蚀刻，比如RIE、或使用熟知的气体(例如CF4、SF6、NF3等)的等离子体蚀刻。 
如在图3K中所示出的，被暴露的氮化物通过例如RIE被蚀刻，留下氧化物图案41之间的凹入区43。凹入区43因而形成可以用于布线的沟道。如在图3L中所示出的，布线沟道区43被填充以导电材料45，例如铜。铜可以例如被镀入沟道区并且随后被平坦化。 
该背侧布线可以以各种方式被使用，例如互连导电通路。在图3M中，布线45用于将导电通路17连接到焊料凸块29，从导电通路偏移。在图3N和O中所示出的结构和步骤与对以图1J和K中所描述的相同，其中硅晶片1被切割并且倒装片接合至衬底31。随后通过激光切除去除临时玻璃处理器27。 
如上所述，图4A-4C示出了使用顺序步骤的另外的实施例。在图4A中，在接合至硅载体晶片1之前，如在图3A-3O中所描述的，硅衬底3用氧化物41构图。随后构图的氧化物41之间的硅通过蚀刻而被去除并用多晶硅51回填。因而形成的硅衬底随后被接合至硅载体晶片1，如先前所描述的，并且以参考图1所描述的相同的方式形成一对通路导体47和49。导体47和49可以再次是铜或钨。尽管示出了顶氧化物53，但是可以实施该布置而没有顶氧化物53。 
在图4B中，硅衬底3首先被回蚀刻，留下氮化物层7上的氧化物41和 多晶硅层51。然后，多晶硅层51和氮化物层7被回蚀刻从而形成掩埋氧化物41中的凹入，该凹入可以用于形成布线。在图4C中，导电材料54被沉积从而形成导电通路47和49之间的布线导体。显然可以相似地形成其它的布线沟道。 
图5A-5B示出了本发明的又一实施例。在该实施例中，在硅晶片1被接合至硅衬底3之前，以相似于上面参考于从顶侧蚀刻通路所描述的方式，从载体晶片1的背侧蚀刻一对通路。随后通路被填充以多晶硅从而以上述方式形成多晶硅栓55和56，并且所得的结构被接合至具有接合的掩埋氧化物层5和氮化物层7的硅衬底3，如先前所描述的。 
随后以上述方式，衬底3的硅材料被回蚀刻至氮化物层7，并且氮化物层7又被回蚀刻从而暴露多晶硅栓55和56。硅栓55和56随后被蚀刻出通路，如在图5B中所示出的。还是如在图5B中所示出的，打开的通路可以随后被用导电材料62填充或形成衬垫并与形成贯穿顶氧化物层61的导电通路57和59对准。 
图6A-6C示出了在图4A-4C和5A-5B中示出结构的结合。图6A示出了相似于图4A的结构，除了在图4A中所示出的多晶硅51延伸进入其中示出了导体47和49的通路(相似于图5A)的事实之外，从而由此形成多晶硅区63。 
这可以通过在衬底3上形成绝缘层67，随后在绝缘层67上形成氮化物层65并且随后在氮化物层65上形成绝缘层71而完成，如在图6A中所示出的，所有都在将衬底3与载体晶片1接合之前。随后使用光刻从而构图绝缘层71中的开口并且开口被回填以多晶硅63。多晶硅还通过构图的氮化物层69被单独的回填入硅载体1中的通路，相似于在图5A-5B中所采用的工艺，从而由此形成多晶硅区55和56。随后这样形成的衬底3与这样形成的载体1接合。 
随后如先前所述进行蚀刻，从而生产对于公共沟道区71打开的通路，如在图6B中所示出的。如在图6C中所示出的，通路、沟道区和公共部73可以随后被镀以导电材料75。 
从前面的描述应当理解，在本发明的优选实施例中可以进行各种的改进和变更而不偏离其真正的精神。本说明书旨在为了说明的目的而不应理解为限制性的。本发明的范围应当仅受到所附权利要求的语言的限制。 

Claims (20)

1.一种电子结构的制造方法，包括：
提供半导体结构，该半导体结构包括通过绝缘材料的第一层和绝缘材料的第二层接合在一起的具有第一和第二表面的半导体材料的第一层和具有第一和第二表面的半导体材料的第二层，所述绝缘材料的第一层夹置于所述绝缘材料的第二层和所述半导体材料的第一层的所述第二表面之间，并且所述绝缘材料的第二层夹置于所述绝缘材料的第一层和所述半导体材料的第二层的第二表面之间；
在所述半导体材料的第一层中形成通路，所述通路具有从所述半导体材料的第一层的所述第一表面延伸穿过所述绝缘材料的第一层至所述绝缘材料的第二层的壁表面；
在所述通路的所述壁表面上形成绝缘材料层；
用另一材料填充所述通路；
回蚀刻所述半导体材料的第二层至所述绝缘材料的第二层；并且
蚀刻所述绝缘材料的第二层以便暴露所述另一材料。
2.根据权利要求1的方法，其中在所述通路的所述壁表面上的所述绝缘材料层由与所述绝缘材料的第一层相同的绝缘材料制成。
3.根据权利要求2的方法，其中所述半导体材料的第一层和所述半导体材料的第二层都是硅。
4.根据权利要求3的方法，其中导电布线材料形成于所述另一材料上。
5.根据权利要求4的方法，其中所述另一材料是与所述导电布线材料接触的导电材料。
6.根据权利要求4的方法，其中所述另一材料是多晶硅。
7.根据权利要求6的方法，其中在蚀刻所述绝缘材料的第二层的步骤之后，所述方法还包括从所述通路蚀刻所述多晶硅从而打开所述通路以便暴露所述导电布线材料的步骤。
8.根据权利要求7的方法，还包括用导电材料填充所述通路以便接触所述导电布线材料的步骤。
9.根据权利要求8的方法，其中所述绝缘材料的第一层是氧化物并且所述绝缘材料的第二层是氮化物。
10.根据权利要求9的方法，其中在所述导电材料上形成焊料凸块。
11.一种电子结构的制造方法，包括：
提供半导体结构，该半导体结构包括通过绝缘材料的第一层和绝缘材料的第二层接合在一起的具有第一和第二表面的半导体材料的第一层和具有第一和第二表面的半导体材料的第二层，所述绝缘材料的第一层夹置于所述绝缘材料的第二层和所述半导体材料的第一层的所述第二表面之间，并且所述绝缘材料的第二层夹置于所述绝缘材料的第一层和所述半导体材料的第二层的所述第二表面之间；
在所述半导体材料的第一层中形成通路，所述通路具有从所述半导体材料的第一层的所述第一表面延伸穿过所述绝缘材料的第一层至所述绝缘材料的第二层的壁表面；
在所述通路的所述壁表面上用与所述绝缘材料的第一层相同的材料形成绝缘材料层并且延伸至所述绝缘材料的第二层；
用另一材料填充所述通路；
在所述半导体材料的第一层的所述第一表面和所述另一材料上形成金属结构；
从所述半导体材料的第二层的所述第一表面开始蚀刻所述半导体材料的第二层并且回蚀刻至所述绝缘材料的第二层；
蚀刻所述绝缘材料的第二层从而暴露所述另一材料。
12.根据权利要求11的方法，其中所述另一材料是导电通路材料。
13.根据权利要求12的方法，其中所述提供半导体结构的步骤包括在所述半导体材料的第二层的所述第二表面上首先形成与所述半导体材料的第二层的所述第二表面共面的凹入的绝缘材料的图案并且随后在所述半导体材料的第二层的所述第二表面和所述凹入的绝缘材料的图案上沉积所述绝缘材料的第二层。
14.根据权利要求13的方法，其中蚀刻所述半导体材料的第二层的所述步骤包括蚀刻所述半导体材料的第二层下至所述凹入绝缘材料图案之间从而形成其间的至少一沟道并且暴露绝缘材料的第二层的一部分。
15.根据权利要求14的方法，包括蚀刻穿过所述绝缘材料的第二层的所述被暴露的部分并且用导电材料填充所述至少一沟道的步骤以形成布线，使得所述布线的第一部与所述导电通路材料接触。
16.根据权利要求11的方法，其中在所述半导体材料的第一层中形成通路的所述步骤包括从所述半导体材料的第一层的所述第二表面首先形成所述通路。
17.一种电子结构，包括：
半导体结构，该半导体结构包括通过绝缘材料的第一层和绝缘材料的第二层接合在一起的具有第一和第二表面的半导体材料的第一层和具有第一和第二表面的半导体材料的第二层，所述绝缘材料的第一层夹置于所述绝缘材料的第二层和所述半导体材料的第一层的所述第二表面之间，并且所述绝缘材料的第二层夹置于所述绝缘材料的第一层和所述半导体材料的第二层的所述第二表面之间；
在所述半导体材料的第一层中的通路，该通路具有从所述半导体材料的第一层的所述第一表面延伸穿过所述绝缘材料的第一层至所述绝缘材料的第二层的壁表面；
覆盖所述通路的所述壁表面、由与所述绝缘材料的第一层相同的材料制成的绝缘材料层，所述通路延伸至所述绝缘材料的第二层；和
填充所述通路以便与所述半导体材料的第一层的所述第一表面共面的填充材料。
18.根据权利要求17的电子结构，其中所述填充材料是导电材料。
19.根据权利要求18的电子结构，其中金属结构设置于包括所述导电材料的所述半导体材料的第一层的所述第一表面上。
20.根据权利要求19的电子结构，其中所述电子结构包括所述半导体材料的第一层，具有定位在所述半导体材料的第一层的所述第二表面暴露的所述导电材料上的焊料凸块。
CN2008100952822A 2007-05-21 2008-05-09 电子结构及其制造方法 Expired - Fee Related CN101312161B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/751,105 2007-05-21
US11/751,105 US7645701B2 (en) 2007-05-21 2007-05-21 Silicon-on-insulator structures for through via in silicon carriers

Publications (2)

Publication Number Publication Date
CN101312161A CN101312161A (zh) 2008-11-26
CN101312161B true CN101312161B (zh) 2010-12-01

Family

ID=40071653

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100952822A Expired - Fee Related CN101312161B (zh) 2007-05-21 2008-05-09 电子结构及其制造方法

Country Status (2)

Country Link
US (2) US7645701B2 (zh)
CN (1) CN101312161B (zh)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645701B2 (en) * 2007-05-21 2010-01-12 International Business Machines Corporation Silicon-on-insulator structures for through via in silicon carriers
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
US8587121B2 (en) * 2010-03-24 2013-11-19 International Business Machines Corporation Backside dummy plugs for 3D integration
US8519538B2 (en) * 2010-04-28 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Laser etch via formation
US8278132B2 (en) * 2010-05-18 2012-10-02 Himax Imaging, Inc. Image sensor and fabricating method thereof
US8316717B2 (en) 2010-06-29 2012-11-27 Rogue Valley Microdevices, Inc. Wireless self-powered monolithic integrated capacitive sensor and method of manufacture
US8492260B2 (en) 2010-08-30 2013-07-23 Semionductor Components Industries, LLC Processes of forming an electronic device including a feature in a trench
US8847380B2 (en) * 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
CN102420234B (zh) * 2010-09-28 2015-04-08 汉积科技股份有限公司 感光结构的制造方法
CN102064092B (zh) * 2010-10-26 2012-09-05 日月光半导体制造股份有限公司 用于半导体工艺的载体分离方法
FR2980917B1 (fr) * 2011-09-30 2013-09-27 St Microelectronics Crolles 2 Procede de realisation d'une liaison traversante electriquement conductrice
US9236274B1 (en) * 2011-11-01 2016-01-12 Triton Microtechnologies Filling materials and methods of filling through holes for improved adhesion and hermeticity in glass substrates and other electronic components
SE538058C2 (sv) * 2012-03-30 2016-02-23 Silex Microsystems Ab Metod att tillhandahålla ett viahål och en routing-struktur
CN103579088B (zh) * 2012-07-26 2016-09-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件硅通孔的制备方法
US9012324B2 (en) * 2012-08-24 2015-04-21 United Microelectronics Corp. Through silicon via process
US8981533B2 (en) 2012-09-13 2015-03-17 Semiconductor Components Industries, Llc Electronic device including a via and a conductive structure, a process of forming the same, and an interposer
SE538062C2 (sv) * 2012-09-27 2016-02-23 Silex Microsystems Ab Kemiskt pläterad metallvia genom kisel
NL2009757C2 (en) * 2012-11-05 2014-05-08 Micronit Microfluidics Bv Method for forming an electrically conductive via in a substrate.
US9000344B2 (en) * 2013-03-15 2015-04-07 Sensors Unlimited, Inc. Focal plane array periphery through-vias for read out integrated circuit
DE102013221788B4 (de) * 2013-10-28 2021-05-27 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines Kontaktelements und eines optoelektronischen Bauelements
US9362171B2 (en) * 2013-12-26 2016-06-07 Globalfoundries Singapore Pte. Ltd. Through via contacts with insulated substrate
US9831281B2 (en) 2015-05-01 2017-11-28 Sensors Unlimited, Inc. Electrical interconnects for photodiode arrays and readout interface circuits in focal plane array assemblies
US9812354B2 (en) 2015-05-15 2017-11-07 Semiconductor Components Industries, Llc Process of forming an electronic device including a material defining a void
US9455187B1 (en) 2015-06-18 2016-09-27 International Business Machines Corporation Backside device contact
FR3037720A1 (fr) 2015-06-19 2016-12-23 St Microelectronics Crolles 2 Sas Composant electronique et son procede de fabrication
US9514987B1 (en) 2015-06-19 2016-12-06 International Business Machines Corporation Backside contact to final substrate
US9496239B1 (en) * 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US11056382B2 (en) 2018-03-19 2021-07-06 Globalfoundries U.S. Inc. Cavity formation within and under semiconductor devices
FR3083000A1 (fr) * 2018-06-21 2019-12-27 Soitec Substrat pour capteur d'image de type face avant et procede de fabrication d'un tel substrat
KR102518803B1 (ko) * 2018-10-24 2023-04-07 삼성전자주식회사 반도체 패키지
EP3937512A1 (en) 2020-07-10 2022-01-12 Infineon Technologies AG Method and structure for sensors on glass
CN113013094B (zh) * 2021-02-24 2023-07-07 长江存储科技有限责任公司 一种半导体器件及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218213A (en) * 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
CN1519925A (zh) * 2003-02-04 2004-08-11 恩益禧电子股份有限公司 半导体器件及其制造方法
CN1591820A (zh) * 2003-09-03 2005-03-09 联华电子股份有限公司 介层洞优先双镶嵌制程
CN2731711Y (zh) * 2003-06-11 2005-10-05 台湾积体电路制造股份有限公司 铜金属镶嵌结构

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5312621A (en) * 1988-01-25 1994-05-17 Baker Cummins Dermatologicals, Inc. Method of treating fibrotic disorders
US5963838A (en) * 1993-06-22 1999-10-05 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having wiring layers within the substrate
US5682062A (en) * 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US6312621B1 (en) 1998-11-17 2001-11-06 Johnson Matthey Electronics, Inc. Via fill formulations which are electrically and/or thermally conductive, or non-conductive
EP1220312A1 (en) * 2000-12-29 2002-07-03 STMicroelectronics S.r.l. Integration process on a SOI substrate of a semiconductor device comprising at least a dielectrically isolated well
FR2834124B1 (fr) * 2001-12-20 2005-05-20 Osram Opto Semiconductors Gmbh Procede de production de couches semi-conductrices
US6835589B2 (en) * 2002-11-14 2004-12-28 International Business Machines Corporation Three-dimensional integrated CMOS-MEMS device and process for making the same
JP2004311948A (ja) * 2003-03-27 2004-11-04 Seiko Epson Corp 半導体装置、半導体デバイス、電子機器、および半導体装置の製造方法
US6888223B2 (en) * 2003-04-01 2005-05-03 International Business Machines Corporation Use of photoresist in substrate vias during backside grind
JP3646720B2 (ja) * 2003-06-19 2005-05-11 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6897125B2 (en) * 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
JP4432470B2 (ja) * 2003-11-25 2010-03-17 株式会社デンソー 半導体装置
US7276787B2 (en) * 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
CN100521229C (zh) * 2004-07-20 2009-07-29 Nxp股份有限公司 半导体装置及其制造方法
KR100641362B1 (ko) * 2005-01-13 2006-10-31 삼성전자주식회사 이중 확산방지막을 갖는 배선구조 및 그 제조방법
JP2007036060A (ja) * 2005-07-28 2007-02-08 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7465669B2 (en) * 2005-11-12 2008-12-16 Applied Materials, Inc. Method of fabricating a silicon nitride stack
US7410884B2 (en) * 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7605019B2 (en) * 2006-07-07 2009-10-20 Qimonda Ag Semiconductor device with stacked chips and method for manufacturing thereof
US7344959B1 (en) * 2006-07-25 2008-03-18 International Business Machines Corporation Metal filled through via structure for providing vertical wafer-to-wafer interconnection
US7863189B2 (en) * 2007-01-05 2011-01-04 International Business Machines Corporation Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
US7645701B2 (en) * 2007-05-21 2010-01-12 International Business Machines Corporation Silicon-on-insulator structures for through via in silicon carriers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218213A (en) * 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
CN1519925A (zh) * 2003-02-04 2004-08-11 恩益禧电子股份有限公司 半导体器件及其制造方法
CN2731711Y (zh) * 2003-06-11 2005-10-05 台湾积体电路制造股份有限公司 铜金属镶嵌结构
CN1591820A (zh) * 2003-09-03 2005-03-09 联华电子股份有限公司 介层洞优先双镶嵌制程

Also Published As

Publication number Publication date
US20090315188A1 (en) 2009-12-24
US7645701B2 (en) 2010-01-12
US20080290525A1 (en) 2008-11-27
CN101312161A (zh) 2008-11-26
US8198734B2 (en) 2012-06-12

Similar Documents

Publication Publication Date Title
CN101312161B (zh) 电子结构及其制造方法
TWI689047B (zh) 用於三維記憶體元件的貫穿陣列接觸
TWI463584B (zh) 將淺溝槽隔離及穿透基板之通孔整合至積體電路設計中
CN102446886B (zh) 3d集成电路结构及其形成方法
CN110574162B (zh) 三维存储器器件及其制造方法
US7993950B2 (en) System and method of encapsulation
EP2194574B1 (en) Method for producing interconnect structures for integrated circuits
US20220208749A1 (en) Semiconductor devices and methods of manufacture thereof
TWI479554B (zh) 晶圓穿孔及其製造方法
CN103548131B (zh) 使用多层通路的3d集成电路
US9472504B2 (en) Semiconductor having a high aspect ratio via
CN113284841B (zh) 形成三维半导体结构的方法
CN102858681B (zh) 用于微机电系统的化学机械研磨处理流程
CN110828372A (zh) 金属引线、半导体器件及其制作方法
US6087251A (en) Method of fabricating a dual damascene structure
KR100482179B1 (ko) 반도체 소자 제조방법
US7579258B2 (en) Semiconductor interconnect having adjacent reservoir for bonding and method for formation
CN113363202A (zh) 半导体结构及其形成方法
WO2009033837A2 (en) Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US20220108948A1 (en) Method for Producing an Interconnect Via
US9761481B2 (en) Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
Bauer et al. Front end of line integration of high density, electrically isolated, metallized through silicon vias
WO2022072038A1 (en) Connections from buried interconnects to device terminals in multiple stacked devices structures
Bauer et al. Front End of Line Integration of High Spatial Density Electrically Isolated Metallized Through Silicon Vias.

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171127

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171127

Address after: American New York

Patentee after: Core USA second LLC

Address before: New York grams of Armand

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20101201

Termination date: 20190509

CF01 Termination of patent right due to non-payment of annual fee