CN1879208A - 用于探针测试和布线接合的i/o位置 - Google Patents

用于探针测试和布线接合的i/o位置 Download PDF

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Publication number
CN1879208A
CN1879208A CNA2003801107044A CN200380110704A CN1879208A CN 1879208 A CN1879208 A CN 1879208A CN A2003801107044 A CNA2003801107044 A CN A2003801107044A CN 200380110704 A CN200380110704 A CN 200380110704A CN 1879208 A CN1879208 A CN 1879208A
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China
Prior art keywords
layer
groove
barrier
conductive barrier
electrically conductive
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CNA2003801107044A
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Inventor
K·S·彼得拉尔卡
T－J·程
S·H·尼克博克
R·P·沃朗
G·F·瓦尔克
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International Business Machines Corp
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International Business Machines Corp
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Publication of CN1879208A publication Critical patent/CN1879208A/zh
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Abstract

本发明公开了形成输入－输出(I/O)结构的方法，其中通过在凹槽(25)中选择性形成的第一导电阻挡层(102)覆盖具有在第一介质层(10)中的凹槽(25)的底部暴露的铜导电部分(20)的衬底。在衬底表面上形成第二介质(105)，优选有机聚合物例如聚酰亚胺，并且在第二介质(105)中形成第二凹槽(27)以使第一导电阻挡层(102)的至少一部分暴露。保形沉积第二导电阻挡层(107)，之后保形沉积籽晶层(109)，二者均在真空下沉积以确保籽晶层(109)与第二导电阻挡层(107)的附着。选择性除去凹槽(27)外部的籽晶层(107)，之后镀覆含镍金属(113)和随后镀覆贵金属(115)，其将在凹槽(27)中的籽晶层(107)的剩余部分上，而不在第二导电阻挡层(107)镀覆。通过低偏置功率RIE从暴露的场区域除去第二导电阻挡层(107)。本发明提供了形成用于探针测试和布线接合的I/O结构的低成本方法，而不损坏下面的器件和降低芯片的面积。

Description

用于探针测试和布线接合的I/O位置
技术领域
本发明一般涉及半导体制造，更具体地涉及用于制造在封装集成电路(IC)芯片时使用的输入/输出(I/O)位置的方法。
背景技术
在半导体器件的制造中，在多级结构中，尤其在制造工艺的后阶段(“后段制程”或“BEOL”)的介质层中通常镶嵌金属线。包含金属线的最后层(在现有技术中通常称为端部过孔或TV层)将具有在有时称为“远后段制程”或“远BEOL”的工艺中与金属线接触形成的金属衬垫。IC芯片主要使用铝(Al)形成互连，但是最近使用铜(Cu)。Cu具有较低电阻率的优点，但缺点是需要氧化/扩散阻挡。金属衬垫通常用作接合位置，以连接芯片和其它系统部件例如互连的另一级。常规连接包括布线接合和焊料凸起。尽管希望减小IC芯片的所有元件的尺寸，但是接合衬垫日趋难于缩减，以及在一些情况下，接合衬垫的面积增加。由于产量(即在给定晶片或衬底上好芯片与所有芯片的百分比)不利地与芯片尤其是逻辑芯片的尺寸相关，因此芯片面积越大，例如由污染颗粒的沉积引起的损坏的机会越大。
布线接合是本领域公知的并且主要使用在IC芯片中，但缺点包括互连位置的有限密度以及在接合位置对芯片的机械损坏的可能性。工业中普遍公知的大多数当前半导体制造工业利用铝衬垫用于布线接合和电路测试。金属衬垫主要包括铝(Al)，因为铝的反应，在其表面上通常将形成氧化物层。
在布线接合之前，通过在顶层上的关键导电点设置一组测试探针，进行电路测试。为了在测试探针和衬垫金属之间形成良好的接触，必须除去表面氧化物(通常通过公知为“清洁”的技术)。因此接合衬垫的表面将被划痕或损坏。在一些情况中，衬垫可以被探针刺穿。
利用本领域公知的技术，例如热超声(thermosonic)接合，将布线附装到具有氧化表面的铝衬垫，布线通常是具有痕量硅用于硬度的金(Au)。在热超声接合中，在金布线穿过毛细管突出之后，金布线的末端熔化以形成球。然后使该球向下到接合衬垫上，引起该球变形，并引入超声力以完成接合。向下力和超声力通常不足以克服由测试者引入的损坏，这将导致接合失败。因此，衬垫趋向于以更大的面积形成，以允许分离探针和在衬垫上的布线接合位置。
在金和铝之间形成布线接合的另一个问题是金与铝形成金属间化合物，其可以降低接合的可靠性。
对下面的衬底和器件的损坏仍是当前集成电路的另一个问题。尤其在利用Cu金属化的集成电路中，可采用柔软并且通过压力易于损坏的低k介质。因此，尤其在柔软的低k介质的情况下，芯片遇到潜在的机械损坏。因而，通常需要在接合衬垫下的面积没有器件，其也增加芯片的总尺寸。
已经介绍镍/金接合衬垫，因为金是贵金属，其将不容易氧化，所以与接合金和铝相比，接合金布线和金衬垫相对简单(例如，参见U.S.6,534,863，通过参考结合其整个内容)。接合力已经成功减小至30-50％之间，而没有接合故障。然而，在U.S.6,534,863中公开的工艺通常利用严格洁净需求的半导体处理设备进行，并且因此很昂贵。将有利的是提供利用不昂贵的设备和工艺，形成具有贵金属表面的I/O衬垫的方法，例如在封装工业中可获得的那些方法。
因此希望形成具有贵金属的I/O衬垫以允许对于探针测试和布线接合的低结合力，而没有损坏下面的衬底，其降低面积的需求，以及降低成本。
考虑到现有技术的问题和缺陷，因此，本发明的一个目的是提供用于铜互连的I/O位置，其具有贵金属表面，在探针测试之后可以形成可靠的布线接合，并且最小化或没有对下面的衬底的损坏。本发明的另一个目的是提供I/O位置，其具有降低的面积需求并且不需要下面的衬底没有器件。本发明再一个目的是提供形成降低制造成本的I/O位置的方法。本发明的其它目的和优点将通过本说明书部分地明显并显而易见。
发明内容
描述了形成输入-输出(I/O)结构的方法，其中通过在凹槽中选择性形成以覆盖铜表面的第一导电阻挡层例如TiW、TiN或TaN，更优选TiW，覆盖具有在第一介质层例如氧化物或氮化物中的凹槽的底部暴露的铜导电部分(例如互连)的衬底。在衬底表面上形成第二介质，优选包含有机聚合物例如聚酰亚胺，并且在第二介质中形成第二凹槽以使在凹槽底部的第一导电阻挡层的至少一部分暴露。保形沉积第二导电阻挡层例如TiW，之后保形沉积籽晶层，优选CrCu/Cu，二者均在真空下沉积以确保CrCu/Cu籽晶层与第二导电阻挡层的附着。优选第二导电阻挡层在暴露于氧源时自钝化。选择性除去第二介质(例如聚酰亚胺)中的凹槽外部的籽晶层，之后在籽晶层上选择性镀覆(例如电镀或无电镀)含镍金属，和随后在含镍层上选择性镀覆贵金属。镀覆将选择性发生，因为第二导电阻挡层的自钝化特性。贵金属优选金。通过低偏置功率RIE除去第二阻挡层的暴露的场区域。
相比于现有方法，通过上述本发明获得的优点包括成本较低，因为本发明可以利用比半导体处理工具和工艺的成本低的封装工具和工艺实现。所得的I/O结构提供了用于探针测试和布线接合的公共位置，而不损坏下面的器件和降低芯片的面积。
附图说明
现在将通过参考结合本申请的的附图更加详细地描述本发明，附图没必要按比例绘制。注意，在附图中类似的参考标号用于描述类似和相应的部分。
图1示出了本发明的初始结构的截面图，该结构包括具有在介质中形成的凹槽中暴露的铜互连的衬底。
图2示出了本发明的中间步骤的结构的截面图。
图3示出了本发明的中间步骤的结构的截面图。
图4示出了本发明的中间步骤的结构的截面图。
图5示出了本发明的中间步骤的结构的截面图。
图6示出了本发明的中间步骤的结构的截面图。
图7示出了本发明的中间步骤的结构的截面图。
图8示出了本发明的中间步骤的结构的截面图。
图9示出了本发明的中间步骤的结构的截面图。
图10示出了本发明的中间步骤的结构的截面图。
图11示出了本发明的中间步骤的结构的截面图。
图12示出了本发明的中间步骤的结构的截面图。
图13示出了根据本发明的结构的截面图，该结构包括布线结合。
图14A示出了现有技术I/O衬垫的平面图。
图14B示出了根据本发明形成的I/O衬垫的平面图。
具体实施方式
根据本发明，描述了以相对低的成本实现的具有贵金属表面的I/O位置和形成I/O位置的方法。本发明的I/O位置尤其适合用于探针测试和布线接合。在本发明的优选实施例的随后描述中，应该理解这里仅作为实例，并且本发明可以采用各种衬底和金属实践。参考附图说明根据本发明的方法，附图没必要按比例绘制。
参考图1，提供包括后段制程(BEOL)结构的衬底5，该结构包括金属导体20，例如铝(Al)、铜(Cu)等，具有在第一介质层10的凹槽25中暴露的表面。例如，该结构可以是BEOL，其中形成金属导体20作为互联结构。利用本领域公知的工艺，包括但不限于光刻和蚀刻工艺形成凹槽。凹槽在I/O衬垫期望位置形成，并且通常具有在50-140μm范围的宽度，例如，52μm乘以140μm的矩形尺寸。凹槽的深度可以在0.4至约4.0μm的范围，更优选从约0.6-0.8μm。介质层10包括多层介质材料(为了简明，没有示出)，例如二氧化硅(SiO2)、氮化硅(SiNx)、SiCOH以及其它合适的介质。介质优选低k介质，例如SiCOH、来自Dow Chemical的SiLK或其它低模量材料。
根据本发明，如图2所示，第一导电阻挡层102在衬底5的表面上保形形成。导电阻挡层102优选TiW，但也可以由作为扩散阻挡和附着促进剂的材料例如TaN、TiN或其它导电材料形成。阻挡层102的厚度优选薄，以容易制造以及与互连20的良好导电性，但是足够厚，以阻挡金属扩散进入覆层材料。阻挡层102的厚度优选至少约350，以及不大于约500。通过本领域公知的方法沉积阻挡层102，例如，化学气相沉积(CVD)、物理气相沉积(PVD)、离子化物理气相沉积(IPVD)、原子层沉积(ALD)等，优选通过CVD。
然后，基本上从凹槽25外部的衬底5的表面除去阻挡层102，从而保留阻挡层25的一部分，以覆盖在凹槽25中的金属导体20的表面，如图3所示。通过例如化学机械抛光(CMP)的技术，或通过例如湿蚀刻或干蚀刻如反应离子蚀刻的蚀刻工艺，进行从凹槽外部的表面除去阻挡层102。只要导体20的表面保持密封，在除去凹槽外部的阻挡层102之后的凹槽的拐角可以变化。在通过CMP除去的情况下，凹槽的上拐角会遇到一些损坏(没有示出)，但是凹槽25的深度必须充分深以防止从凹槽25的底部除去阻挡层102以及暴露导体20。凹槽的深度可以在0.4至约4.0μm的范围，更优选从约0.6-0.8μm。在通过蚀刻工艺除去的情况下，由于凹槽区域的掩蔽(没有示出)，阻挡层102的一小部分在凹槽外延伸。
接下来，形成第二介质层105以覆盖衬底5的表面，如图4所示。通常，覆盖介质层105将填充凹槽25。第二介质层优选旋涂介质层例如聚酰亚胺、BCB(非光敏的苯并环丁烯)等，并且更优选聚酰亚胺和优选光敏。可以采用非光敏介质，例如氧化物和氮化物，其通过例如CVD、PEVCD(等离子体增强化学气相沉积)方法和本领域公知的其它方法沉积。第二介质层105的厚度可以从4至12μm的范围，优选约5-7μm，以及最优选6μm。注意如果导电互连是铜，第一导电阻挡层102防止铜污染覆盖介质层105。
接下来，参考图5，在第二、覆盖介质层105中形成凹槽27，以使在凹槽25的底部导电阻挡层102的至少一部分直接覆盖导体20。虽然第二凹槽27优选与第一凹槽25对准，只要暴露在导体20上的第一导电阻挡层102的底表面的一部分，它可以不对准，如图5所示。对于封装IC，覆盖介质层可以作为划痕保护层。通过本领域公知的构图方法形成凹槽27，例如湿或干(如，RIE)蚀刻技术，以及光刻技术。优选，覆盖介质层105是光敏的，其允许利用光刻工艺，利用在初始结构中用于形成初始凹槽图形25的相同掩膜构图。这将节约生产额外的光刻掩膜的成本，并且将避免常规蚀刻工艺中需要的额外掩蔽材料的形成。在旋涂介质的情况下，在构图之后，需要通常根据使用的材料通过本领域公知的热处理固化材料。
现在参考图6，在衬底5的表面上保形沉积第二导电阻挡层107。第二导电阻挡层107应该具有与第二介质层105和第一阻挡层102的良好的附着。导电阻挡层107当暴露于氧时也应该自钝化，即充分反应以形成作为绝缘体的氧化物，并且将防止随后镀覆在所述表面上。适合第二导电阻挡层107的实例是TaN、TiN，并且优选TiW。第二导电阻挡层107可以在真空下通过例如CVD、PVD等方法沉积。第二导电阻挡层107的厚度应该在1500至1600(0.15-0.16μm)的范围内，并且优选约1600。
然后在第二导电阻挡层107上沉积第三导电层109，以在第三阻挡层109的上表面上提供铜。第三导电阻挡层109优选在真空下沉积，以确保附着到下面的第二导电阻挡层107(例如，防止第二层107表面的氧化)。形成第三导电阻挡层109以提供包括用于镀覆的籽晶金属的表面，优选铜。可以利用其它籽晶金属，包括Ru、Rd、In、Os等。优选，第三导电(籽晶)层109是渐变的，起始于铜和与CrCu/Cu兼容的金属的混合物，其从在与第二阻挡层107(如，TiW或TaN的)的界面处的CrCu(优选50重量％的Cr与50重量％的Cu)渐变，直到第三(籽晶)层109的表面主要为Cu。可选地，第三导电层109可以由多层形成，其中在与第二阻挡层107的界面处的层包括铜和与第二层107兼容的另一种金属的混合物，并且上层基本上包括Cu。优选，CrCu渐变层约2500至4000，并且铜籽晶层优选小于约5000，更优选约4500。本发明对于第二或第三导电层107、109的具体厚度没有限定，其可以为适应具体制造设备的能力而改变。第二和第三层107、109的沉积优选连续地进行，例如，在真空中，以在工艺的该阶段确保良好的附着和防止在第二阻挡层107上形成钝化层。
然后从凹槽27的外部区域除去作为籽晶层的第三导电层109。例如，凹槽27利用光刻工艺保护性掩蔽以形成保护抗蚀剂部分111，如图8所示，其利用构图的光刻掩膜(没有示出)形成。用于构图抗蚀剂部分111的掩膜可以与用于形成凹槽25的掩膜相同，除了通过利用相反的抗蚀剂工艺。例如，如果利用正抗蚀剂形成凹槽25，那么利用负抗蚀剂通过相同掩膜形成抗蚀剂部分111。凹槽27的底部的至少一部分必须被覆盖，其将形成至导电部分20的导电路径以允许正常的芯片工作。通过蚀刻工艺如湿蚀刻、RIE或优选电蚀刻工艺除去籽晶层109(例如CrCu/Cu)，除了被抗蚀剂部分111保护的地方。例如利用包括硫酸盐和丙三醇的水溶液进行电蚀刻工艺。
接着，通过本领域公知的技术除去抗蚀剂111。可选地，如果充分最小化表面形貌，通过抛光，如CMP，从凹槽外部的第二阻挡层107除去籽晶层109。所得的结构如图9所示，其中籽晶层109至少覆盖凹槽27的底部表面。优选籽晶层具有至少一部分沿凹槽27的外部的晶片5的最上表面延伸。这如此实现，通过利用与形成第一凹槽25相同的掩膜，例如，通过利用负抗蚀剂，并利用过剂量条件进行暴露，如本领域技术人员所公知。这提供的优点是不需要两种分离的掩膜来形成构图凹槽25和构图凹槽27。
然后，在籽晶层109上镀覆含镍层113，如图10所示。含镍层可以基本上为镍或镍合金，例如，NiP等。镀覆利用电镀工艺或无电镀工艺进行。注意，根据本发明，含镍层113将仅在籽晶层109上，而不在通过原氧化物已经钝化的第二阻挡层107上镀覆。例如，如果电蚀刻工艺在选择性除去凹槽27外部的籽晶层109时进行，蚀刻溶液中水的存在为自钝化第二阻挡层107提供氧源。对于随后的电镀第二阻挡层107也作为电极。对于电镀，施加的电压应该平衡，从而镍将在籽晶层109上而不是在当前运送层107上成核。根据使用的特定工具的需求调节其它因素，如本领域公知的例如电流、流速以及其它工具特定参数。在无电镀情况下，第二阻挡层107提供保护阻挡，防止化学药品如聚酰亚胺进入第二介质层105。
然后，现在参考图11，在含镍层113上镀覆贵金属衬垫层115。衬垫层115可以是贵金属例如金、铂、或钯，更优选金。贵金属115的镀覆通过电镀或无电镀镀覆方法进行。优选在镀覆贵金属层115之前不使含镍层113氧化，例如，通过在镍和金镀覆浴之间利用冲洗浴。镀覆电压应该平衡，以使贵金属115将在含镍层113上，而不在第二阻挡层107(例如TiW)上选择性成核。贵金属衬垫115具有的厚度优选在0.4-0.6μm的范围，对于金衬垫优选约0.5μm厚。含镍层113应该充分厚以阻止贵金属(例如金)和籽晶金属(例如铜)的混合。例如，利用从Uyemura可以获得的THRU-NIC CL电镀浴，优选厚度约1μm。
然后，从没有被衬垫115(即场区域)覆盖的区域除去第二阻挡层107如图12所示。通过蚀刻例如湿蚀刻或干蚀刻进行除去。只要介质层105没有损坏，可以利用抛光除去阻挡层107。优选进行各向异性蚀刻，例如RIE。RIE蚀刻的功率应该尽可能的低以从场区域除去阻挡层107，从而衬垫115可以作为RIE掩膜，以使贵金属将不溅射。例如，约200瓦的偏置可以充分除去TiW阻挡层而基本上没有金衬垫的溅射。用于RIE的功率将依赖于利用的设备。从场区域除去阻挡层107之后的结构在图12中示出。
接着，参考图13，布线117可以与衬垫115接合。布线117，其优选贵金属例如金，利用例如热超声接合、超声接合或热压缩接合的技术与衬垫115接合。
本发明的一个优点是衬垫115的尺寸可以设计以与衬垫上形成的球的尺寸更接近，与常规衬垫相比降低了衬垫的尺寸。例如，参考图14A，在平面图中示出的常规衬垫215，例如铝衬垫，为适合探针标记219和布线结合217，长度L1通常长于它的宽度W1。然而，根据本发明形成的衬垫115，可以适合探针标记(没有示出)和随后在探针标记上形成的布线接合117，因此与常规衬垫的长度L1相比长度L2可以充分减小。例如，如果将要接合的布线末端的球具有约45μm的直径，并且接合工具具有±2μm的位置公差，以及1μm的允许值是可以接收的，那么应该设计衬垫具有等于它长度L2的宽度W2，即具有50μm×50μm的尺寸。考虑一些常规具有52μm×145μm尺寸的衬垫，尺寸为50μm×50μm的衬垫将提供每衬垫5040μm2的节约。如果芯片具有100接合衬垫，本发明将实现至少500,000μm2的节约。
申请人已经发现根据本发明形成的衬垫导致布线接合所需的接合力30-50％的缩减量。这种低作用力有利于在有源区域或器件上设置的衬垫，其在芯片尺寸上将提供进一步的改善。
本发明在制造上也实现了成本的节约。当在半导体工艺的最后阶段期间通常生产常规I/O衬垫，本发明允许利用当前封装技术进行I/O衬垫的制造，其为在有机介质上金属的沉积提供了设备和工艺，例如在旋涂介质如聚酰亚胺上的CrCu/Cu层。在半导体制造阶段由于需要高的公差，半导体设备和工艺的使用比封装设备和工艺的使用明显更昂贵。
尽管通过具体实施例描述了本发明，明显的是，通过上述描述，许多替换、修改和变换对于本领域的技术人员来说是显而易见的。因此，本发明旨在包括落入本发明和所附权利要求的范围和金属的所有这些替换、修改和变换。
工业适用性
本发明的结构和方法有用于制造集成电路，尤其有用于为铜互连技术提供用于探针测试和布线接合的衬垫。

Claims (10)

1.一种制造输入-输出结构的方法，包括以下步骤：
提供包括介质层的衬底，所述介质层具有在其中形成的凹槽，其中所述凹槽具有包括铜的底表面；
在所述衬底上保形沉积第一导电阻挡层；
选择性除去所述凹槽外部的所述第一阻挡层，以使在所述凹槽中保留的所述第一导电阻挡层的一部分至少覆盖所述底表面；
在所述衬底的表面上沉积第二介质层；
在所述第二介质层中形成第二凹槽以暴露覆盖所述第一凹槽的底表面的所述第一导电阻挡层的至少一部分；
在具有所述第二凹槽的所述衬底上保形沉积第二导电阻挡层；
在所述第二导电阻挡层上保形沉积籽晶层；
从所述第二凹槽外部的所述第二阻挡层的表面选择性除去所述籽晶层；
在所述籽晶层的所述保留部分上选择性镀覆含镍层；以及
在所述含镍层上选择性镀覆贵金属。
2.根据权利要求1的方法，其中所述第二介质层包括有机聚合物。
3.根据权利要求2的方法，其中所述有机聚合物包括聚酰亚胺。
4.根据权利要求1-3中任何一项的方法，其中所述第二导电阻挡层包括选自TiW、TiN和TaN的一种材料。
5.根据权利要求1-4中任何一项的方法，其中所述籽晶层包括CrCu/Cu层。
6.根据权利要求1-5中任何一项的方法，其中所述贵金属选自金、铂和钯。
7.根据权利要求1-6中任何一项的方法，还包括在选择性镀覆贵金属的所述步骤之后，选择性除去所述第二阻挡层的暴露部分的步骤。
8.根据权利要求7的方法，其中选择性除去所述第二阻挡层的暴露部分的所述步骤包括在充分低的偏置功率下的反应离子蚀刻以使所述贵金属不溅射。
9.根据权利要求1-8中任何一项的方法，还包括以下步骤：在所述贵金属层上进行探针测试，以及在所述贵金属层的与所述探针测试基本上相同的位置将布线接合到所述贵金属层。
10.一种通过权利要求1-9中任何一项的方法形成的输入-输出结构。
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