KR20040018248A - 집적 회로 구조체와 그 마련 공정 - Google Patents

집적 회로 구조체와 그 마련 공정 Download PDF

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Publication number
KR20040018248A
KR20040018248A KR10-2003-7008825A KR20037008825A KR20040018248A KR 20040018248 A KR20040018248 A KR 20040018248A KR 20037008825 A KR20037008825 A KR 20037008825A KR 20040018248 A KR20040018248 A KR 20040018248A
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South Korea
Prior art keywords
copper
pad
wiring
cmp
depositing
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KR10-2003-7008825A
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English (en)
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KR100542120B1 (ko
Inventor
바쓰한스요아힘
Original Assignee
인피니언 테크놀로지스 노쓰 아메리카 코포레이션
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Publication of KR20040018248A publication Critical patent/KR20040018248A/ko
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Publication of KR100542120B1 publication Critical patent/KR100542120B1/ko

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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L2924/14—Integrated circuits

Abstract

집적 회로 구조에서, 배선 본딩된 구리 패드 구리 배선 구성요소를 포함하는 개선물에 있어서, 상기 구리 패드 구리 배선 구성요소는 셀프 패시베이션(self-passivation), 낮은 저항, 높은 본드 강도 및 산화 작용 및 부식에의 향상된 저항력을 특징으로 하고, 구리 패드 구리배선 구성요소는 금속화물 라인과, 금속화물 라인과 구리 패드를 둘러싸는 구리 합금을 분리하는 라이너와, 라이너를 둘러싸는 유전체와, 구리 합금 배선에 본딩된 구리 패드를 포함하고, 구리 배선 구성요소는 a) 구리 합금과 라이너 사이의 도펀트 다량 함유 계면과, b) 상기 구리 패드의 표면과, c) 구리 패드와 구리 합금 배선 사이의 본드의 표면과, d) 구리 합금 배선의 표면 상의 셀프 패시베이션 영역을 특징으로 한다.

Description

집적 회로 구조체와 그 마련 공정{CU-PAD/BONDED/CU-WIRE WITH SELF-PASSIVATING CU-ALLOYS}
배선 본딩의 기술에서, 현재의 최신 기술은 종래의 알루미늄 쐐기 또는 금 볼 본딩(Au-ball bonding)과 조합하여 알루미늄 패드를 사용하는 것이다. 그러나, 구리계 금속화물(Cu based metaliization)의 상부에 알루미늄 패드의 삽입은 고가이며 추가의 처리 단계들을 필요로 한다.
게다가, 구리 패드 상에 구리 배선의 동시 본딩이 사용된다면, 노출된 구리 층은 부식 및 산화에 상당히 영향을 받기 쉽다.
종래의 오버플레이팅되고 오버코팅된 구리(Cu) 패드(overplated, overcoated copper(Cu) pads) 상에서 배선본드와의 종래 기술의 직접 칩 부착에는 고비용이 드는데, 그 이유는 직접 칩 접촉 부착(DCA) 배선 본딩된 집적 회로(IC) 칩 및 구리회로를 갖는 캐리어 상에서의 고수율 배선 본딩을 수행하는 배선 본드 점퍼 회로 상에서 플레이팅에 많은 비용이 들기 때문이다.
IC 칩은 접착제 또는 열을 사용하는 솔더 칩 접촉 재료를 이용하여 회로 캐리어에 부착된다. 회로 커버코우트(covercoat) 또는 솔더 마스크는 구리 회로를 피복한다. 직접 칩 부착(DCA) 배선본딩 동작 시, 장벽 언더플레이팅(barrier underplatings)과 노블 또는 세미노블 금속 오버플레이팅 마무리(finishes) 또는 표면 코팅의 조합을 갖는 회로 캐리어 상의 상호 접속 패드에 실리콘 칩이 배선 본딩된다. 회로 캐리어 배선본딩 애플리케이션을 위한 공동의 계층화된 표면 마무리 금속은 금(Au), 팔라듐(Pd) 또는 은(Ag)의 표면 오버플레이팅 코팅 층에 의해 피복되는 니켈(Ni)의 언더플레이팅 코팅 층으로 이루어진다. 이 계층화된 표면 마무리 처리는 아래에 놓인 구리(Cu) 회로 금속화물이 상기 오버플레이트의 표면으로 확산하는 것을 막고 이어서 배선본드 패드 표면의 산화 작용을 막는다. 그렇지 않으면, 배선 본딩 이전에 패드 표면의 상당한 산화 작용이 고수율을 갖는 배선본드를 무력하게 하고 배선본드 상호 접속 신뢰성의 왜곡을 가져올 수 있다. 구리 패드 상에서 이 오버플레이팅 처리의 사용은 고수율 및 높은 신뢰도 배선본드 상호 접속을 제공하기 위해 사용되었다.
이 플레이팅 처리는 배스(bath) 화학물질을 플레이팅하는 데 요구되는 귀금속 내용물 및 강력한 프로세스 제어 때문에 고가이다. 더욱이 전해질 플레이팅을 사용하면, 플레이팅 처리를 요구하는 모든 영역에 버싱 구조(bussing configuration)가 제공되어야 한다. 버싱 구조는 보다 효율적인 배선 구성을 포함하며, 또한 패널과 회로 설계시 이용 가능한 캐리어 공간의 최대 사용을 막을 수 있다. 전해질 플레이팅은 폴리이미드(polyimide), 폴리에스테르와 같은 유연성 있는 캐리어 물질 및 글래스 에폭시 합성물 또는 세라믹, 액정 폴리머(ligquid crystal polymer, LCP)와 같은 단단한 캐리어 물질을 포함하는 패널화된(panelized) 캐리어 물질 상에 멀티 마이크로프로세서 회로 구성의 비효율적 패킹 때문에 더 높은 회로 당 가격을 가져올 수 있다.
미국 특허 5,632,438호는 구리 회로(copper circuitization) 상에 알루미늄 배선 본딩을 위한 직접 칩 부착 처리를 개시하는데, 이는 캐리어에 하나의 집적 회로 칩을 연결하고, 캐리어 및 부착된 집적 회로 칩에 구연산 및 수산계 첨가물을 포함하는 수성의 세정 용액을 붓고, 캐리어 및 부착된 집적 회로에 린스를 붓고, 캐리어에 의해 지탱되는 구리 회로 상에 배선 본딩을 하는 단계를 포함한다.
깊은 서브미크론 집적 회로 패키지를 위한 본드 능력을 향상시키는 방법이 미국 특허 6,110,816에 개시되어 있다. 이 방법은 상부의 도전층을 갖는 반도체 기판과, 상기 상부의 도전층을 피복하는 상부층과, 상기 상부층에 도포되는 포토레지스터를 제공하는 단계와, 서브미크론 크기의 구멍의 어레이를 형성하기 위해 상기 포토레지스트를 패터닝하는 단계와, 상기 상부층을 관통하여 상기 상부의 도전층으로 개구를 에칭하는 단계와, 상기 상부층의 개구를 통해 상기 상부의 도전층 내에 거친 결 표면 프로파일(rough textured surface profile)을 형성하는 단계와, 상기 상부층 위에 패시베이션막을 증착하는 단계와, 배선 볼 본딩을 위해 배선 패드 윈도우를 형성하는 단계를 포함한다.
집적 회로를 생성하기 위해 구리 배선을 구비하는 구리 패드의 배선 본딩의 기술 영역에서, 순수한 구리 배선 패드에 본딩된 순수한 구리 배선은 최고 품질 본드 및 최저 저항력을 제공한다. 그러나, 순수한 구리는 셀프 패시베이션 효과를 제공하지 않으므로 구리가 부식 및 산화될 위험이 있다. 따라서, 이 기술에서의 필요사항은 이 제조로 형성되는 구리 및 집적 회로가 셀프 패시베이션을 달성하여 내부식성 및 내산화성을 가지도록 우수한 접착성 및 우수한 셀프 패시베이션 능력과 결합되는 우수한 본드 품질을 제공하도록 구리 패드 상에 본딩된 구리 배선을 제공하는 것이다.
본 발명은 셀프 패시베이션 구리 합금을 이용하는 구리 배선을 구비하는 구리 패드의 배선 본딩에 관한 것이다. 도펀트 다량 함유 구리 합금으로부터 생기는 셀프 패시베이션 층은 구리를 부식 및 산화로부터 보호한다.
도 1은 구리 패드가 구리 합금에 의해 둘러싸이는 구리 패드와의 본딩 이전에 구리 합금 배선을 도시,
도 2는 형성된 본드가 볼이나 쐐기이며 셀프 패시베이션에 의해 특징지어지는 도펀트 다량 함유 계면이 있는, 구리 패드로의 배선본딩 및 어닐링 이후의 구리합금 배선을 도시하며 X들에 의해 도시.
발명의 개요
본 발명의 하나의 목적은 우수한 본드 품질 및 낮은 저항성을 제공하도록 구리가 셀프 패시베이션에 의해 특징지어지는 구리 패드에 본딩되는 구리 배선을 제공하는 것이다.
본 발명의 다른 목적은 우수한 본드 품질 및 낮은 저항을 제공하도록 구리 패드 상에 본딩되는 구리 배선을 제공하는 것인데, 이에 구리 패드 상에 본딩되는 구리 배선은 셀프 패시베이션 구리 합금의 사용 때문에 부식 및 산화 작용에 저항력이 있다.
본 발명의 다른 목적은 셀프 패시베이션 구리 합금의 사용 때문에 부식 및 산화 작용에 저항력이 있는 구리 합금 중 100%로 제조되는 구리 배선 및 구리 패드를 사용함으로써 우수한 본드 품질 및 더 낮은 저항을 제공하는 구리 패드 상에 본딩되는 구리 배선을 제공하는 것이다.
또 본 발명의 다른 목적은 구리 패드에 본딩되는 구리 배선을 제공하는 것인데, 구리 합금으로부터 셀프 패시베이션을 이루기 위해 구리 패드에 구리 배선을 본딩할 때 우수한 접착성 및 본드 품질을 제공하도록 배선은 솔리드 구리 합금 배선이거나, 내부 코어(core)가 구리 합금으로 구성되고, 외부 코어가 순수 구리인 이중 층 구리 배선이다.
본 발명의 다른 목적은 구리 패드에 본딩되는 구리 배선을 제공하는 것인데, 구리 배선이 이중층이고 구리 패드가 이중층(구리 합금 씨드 층(seed layer)과 순수 구리 충진(pure Cu-fill))이어서 셀프 패시베이션을 달성하므로 부식 및 산화 작용에 저항력이 있게 된다.
본 발명에 따르면, 구리 합금(Cu-Al, Cu-Mg 및 Cu-Li)을 사용하여 구리 배선으로의 구비 패드의 배선 본딩이 수행될 때 부식 및 산화 작용에의 저항성과 결합하는 우수한 접착력 및 우수한 본드 품질이 획득된다.
일반적으로, 본 발명의 문맥에서, 반도체 장치 또는 집적 회로를 생성하기 위해 셀프 패시베이션 구리 합금을 사용하는 구리 배선으로의 구리 패드의 배선본딩은 다음 일련 처리에 의해 이루어진다.
a) 유전체 내에 (이중의) 대머신 구조를 패터닝하여 배선 및 본드 패드를 형성하는 단계와,
b) 금속 라이너를 증착시키는 단계(PVD, CVD, 무전해 또는 다른 종래 기술로)(이 단계는 최적의 구리 합금을 사용함으로써 선택 가능함)와,
c) 최종 구리 충진(Cu-fill)을 위한 시드 층(seed layer)으로서 구리 합금을 (PVD, CVD, 무전해 또는 다른 종래 기술로) 증착시키는 단계와,
d) 대머신 구조를 순수 구리로 (전자 플레이팅, PVD, CVD, 무전해 또는 다른 종래 기술로) 충진하는 단계와,
e) 저온(<200℃)에서 사전 CMP(Pre-CMP) 어닐링하여 큰 구리 입자를 갖는 저저항 구리 박막을 형성하는 단계(그러나, 구리 합금에서의 도펀트의 외부 확산은 이 지점에서 멈추어져야 함)와,
f) 구리 CMP하여 구리 CMP 과충진을 제거하고, 이어서 라이너 CMP하는 단계.
후속하는 일련의 처리를 위하나 네 가지 가능한 선택 사항은 다음과 같다.
선택 사항 A:
7) 포스트 CMP 어닐링하여(온도 범위: 250℃~450℃) 구리 표면 및 구리 라이너 계면에서 셀프 패시베이션 도펀트 다량 함유 층을 형성하는 단계(힐록(hillock) 형성을 억제하기 위해 점진적 온도 증가로 개시하는 것이 이롭다. 도펀트 다량 함유 표면 층의 초기 형성 이후에 힐록 형성은 현저히 감소된다).
8) 유전체 캡 층(구리 확산 장벽, 실리콘 질화물, 블록(blok) 또는 다른 종래 기술)을 증착시키는 단계. 이 유전체 확산 장벽을 전부 제거하고 SiO2증착 또는 다른 유전체 물질(가령, 낮은 K 물질)의 증착으로 처리를 계속하는 것이 가능하다.
선택 사항 B:
7) 유전체 캡 층을 (구리 확산 장벽, 실리콘 질화물, 블록 또는 다른 종래 기술로) 증착시키는 단계.
8) 어닐링하여(온도 범위: 250℃~450℃) 구리 유전체 캡 층 계면 및 구리 라이너 계면에서 셀프 패시베이션 도펀트 다량 함유 층을 형성하는 단계.
선택 사항 C:
7) 온도 범위 250℃~400℃(이 온도 범위는 9)와 비교할 때 더 낮음)에서 포스트 CMP 어닐링하는 단계, 이 단계는 대략 50℃에서 구리 표면 및 구리 라이너 계면에서 부분적으로 셀프 배시베이션 도펀트 다량 함유 층을 형성한다. 힐록 형성을 억제하기 위해 점진적 온도 증가로 개시하는 것이 이롭다. 도펀트 다량 함유 표면 층의 초기(부분적) 형성 이후에, 힐록 형성은 현저히 감소된다.
8) 유전체 캡 층을 (구리 확산 장벽, 실리콘 질화물, 블록 또는 다른 종래 기술로) 증착시키는 단계. 이 유전체 확산 장벽을 완전히 제거하고 SiO2증착 또는 다른 유전체 물질(가령, 낮은 k 물질)의 증착으로 처리를 계속하는 것이 가능하다.
9) 포스트 캡 층 어닐링(단계 7)에서 보다 대략 50℃ 높은 300℃~450℃ 온도 범위에서 하고 포스트 어닐링하여, 라이너 및 캡 층 계면 상에서 최종의 셀프 패시베이션 층을 형성하는 단계. 두 개의 어닐 단계 7) 및 8)을 이용하는 이 방법은 힐록 형성 및 부착에 있어서 이롭다.
선택 사항 D:
7) 유전체 캡 층을 (구리 확산 장벽, 실리콘 질화물, 블록 또는 다른 종래 기술로) 증착시키는 단계. 일련 처리의 이 지점에서는 어닐링이 없으므로 셀프 패시베이션 층의 형성도 없다.
다음 단계들은 본 발명 처리의 주요 단계들이다:
10) 최종 패시베이션 층(산화물/질화물 조합물)을 증착시키는 단계와,
11) 폴리이미드 또는 광감성 폴리이미드(PSPI) 층(선택 사양적)을 증착시키는 단계와,
12) 폴리이미드(또는 PSPI) 및 최종 패시베이션(구리의 상부의 유전체 캡 층을 포함함)을 리소그래피로 패터닝하고 에칭하여 패드 영역을 개방하는 단계. 개방 패드 에칭(와 후처리) 동안에, 프로빙(probing)을 위한 세정 구리 표면을 갖추기 위해 구리/캡 층 계면에서 셀프 패시베이션 층이 제거된다.
13) 칩을 프로빙하는 단계와,
14) 구리 합금 배선과 프로빙된 패드의 배선본딩(쐐기 또는 볼 본딩) 단계와,
15) 250℃~450℃ 사이의 온도에서 본딩된 칩을 어닐링하여 개방된 구리 패드 표면 및 구리 배선 상에 셀프 패시베이션 층을 형성하는 단계.
프로빙 단계 13)와 본딩 단계 14) 사이에서, 긴 시간이 경과한다. 이 시간 동안 구리 패드를 보호하기 위해 프로빙된 구리 표면 상에 셀프 패시베이션/보호막 층을 형성하는데 추가의 단계가 삽입될 수 있다. 본딩 바로 직전에 이 층은 최적 본드 품질을 위한 세정 구리 패드 표면을 구비하기 위해 습식 세정에 의해 제거된다.
이제, 구리 패드(11)와의 본딩 이전의 구리 합금 배선(10)을 도시하는 도 1을 참조한다. 구리 패드는 구리 합금(12)에 의해 둘러싸여지며 라이너(14)에 의해 유전체(13)로부터 분리된다.
선택 사양적으로는, 점선에 의해 도시되는 바와 같이, 폴리이미드(15)가 유전체의 상부에 증착될 수 있다.
도 2로부터 알 수 있듯이, 배선본딩과 그 후의 어닐링 이후에, 패시베이션된도펀트 다량 함유 계면 층(16) 및 셀프 패시베이션된 구리 표면(17)이 형성되며 X로 표시된다. 구리 합금, 본드 볼 또는 쐐기(18) 주위에 그리고 패드와 배선 이음새(joinings)의 접합부에서 셀프 패시베이션이 형성된다. 이 도펀트 다량 함유 셀프 패시베이션 층은 힐록 구조가 아니며, 부식, 산화 작용으로부터 구리를 보호하며 주위의 반도체 장치 영역으로의 구리의 외부 확산을 막는다.
본 발명의 문맥에서, 구리 합금은 잘 알려진 구리 합금 뿐만 아니라 CuAl, Cu-Mg, Cu-Li일 수 있고, 구리 합금의 다른 구성요소의 구리가 아닌 도핑 물질의 농도는 구리 합금 중 약 0.1 내지 약 5.0% 원자 중량의 범위일 것이다.
셀프 패시베이션 구리 합금을 이용하여 구리 배선과 구리 패드를 배선 본딩은 본 발명 처리에 의해 야기되는 셀프 패시베이션에 의해 구리를 부식 및 산화 작용으로부터 보호하며 접착성을 향상시키는 것에서 특히 중요하다.
따라서, 셀프 패시베이션 구리 합금을 사용하는 구리 배선을 갖는 구리 패드는 순수 구리 패드 상에 본딩되는 순수 구리 배선에 대한 상당한 본드 품질 및 낮은 저항을 제공하고, 순수 구리 패드 상에 본딩되는 순수 구리 배선으로는 획득되지 않는 셀프 패시베이션 효과도 제공한다. 즉, 이중층 구리 패드와의 조합으로 이중 층 구리 배선(구리 합금 씨드 층과 순수 구리 충진)은 셀프 패시베이션과 낮은 저항 그리고 높은 본드 강도의 최적 특성을 나타낸다.
특정 대표적 실시예 및 세부사항이 본 발명의 바람직한 실시예를 도시하는 목적으로 도시되었지만, 첨부 청구 범위에서 한정되는 본 발명의 의미 및 범주로부터 벗어나지 않고 개시되는 본 발명에서의 다양한 변경이 이루어질 수 있다는 것이당업자에게 명백할 것이다.

Claims (18)

  1. 집적 회로 구조에서, 배선 본딩된 구리 패드 구리 배선 구성요소를 포함하는 개선물에 있어서,
    상기 구리 패드 구리 배선 구성요소는 셀프 패시베이션(self-passivation), 낮은 저항, 높은 본드 강도 및 산화 작용 및 부식에의 향상된 저항력을 특징으로 하고, 상기 구리 패드 구리배선 구성요소는
    금속화물 라인과,
    상기 금속화물 라인과 구리 패드를 둘러싸는 구리 합금을 분리하는 라이너와,
    상기 라이너를 둘러싸는 유전체와,
    구리 합금 배선에 본딩된 구리 패드를 포함하되, 상기 구리 배선 구성요소는
    a) 상기 구리 합금과 라이너 사이의 도펀트 다량 함유 계면과,
    b) 상기 구리 패드의 표면과,
    c) 상기 구리 패드와 상기 구리 합금 배선 사이의 본드의 표면과,
    d) 상기 구리 합금 배선의 표면
    상의 셀프 패시베이션 영역에 있는 것을 특징으로 하는
    집적 회로 구조.
  2. 제 1 항에 있어서,
    산화물, 질화물 또는 그 조합을 상기 유전체에 증착시키고, 이어서 약 250℃ 내지 약 450℃의 온도에서 어닐링하는 집적 회로 구조.
  3. 제 2 항에 있어서,
    상기 비활성화 영역은 상기 구리 합금의 약 0.1 내지 5.0 원자 중량의 범위에 존재하는 집적 회로 구조.
  4. 제 3 항에 있어서,
    상기 구리 합금은 Cu-Al, Cu-Mg 및 Cu-Li로 구성되는 그룹으로부터 선택하는 집적 회로 구조.
  5. 제 4 항에 있어서,
    상기 구리 합금은 Cu-Al인 집적 회로 구조.
  6. 제 4 항에 있어서,
    상기 구리 합금은 Cu-Mg인 집적 회로 구조.
  7. 제 4 항에 있어서,
    상기 구리 합금은 Cu-Li인 집적 회로 구조.
  8. 구리 배선 구성요소로 배선 본딩된 구리 패드를 포함하는 집적 회로 구조 준비 처리에 있어서,
    셀프 패시베이션 구리 패드 구리 배선은 산화 작용 및 부식에의 저항력과, 상기 구리 패드와 금속화물 라인 사이와 상기 구리 패드와 구리 합금 배선을 잇는 본드사이의 계면 간의 향상된 부착력을 특징으로 하고,
    a) 유전체 내에 (이중의) 대머신 구조를 패터닝하여 배선 및 본드 패드를 형성하는 단계와,
    b) 금속 라이너를 증착시키는 단계와,
    c) 최종 구리 충진(Cu-fill)을 위한 시드 층(seed layer)으로서 구리 합금을 증착시키는 단계와,
    d) 상기 대머신 구조를 순수 구리로 충진하는 단계와,
    e) 저온(<200℃)에서 사전 CMP(Pre-CMP)하여 큰 구리 입자를 갖는 저저항 구리 박막을 형성하는 단계와,
    f) 구리 CMP 과충진을 제거하고, 이어서 리니어 CMP하는 단계와,
    g) 약 250℃~ 약450℃의 온도 범위에서 포스트 CMP 어닐링하여 구리 표면 및 구리 리니어 계면에서 셀프 패시베이션 도펀트 다량 함유 층을 형성하는 단계와,
    h) 폴리이미드 층을 증착시키는 단계와,
    i) 개방 패드 영역에 리소그래피 및 에치 단계에 의해 폴리이미드의 패터닝 및 비활성화를 완료하여 프로빙(probing)을 위한 깨끗한 구리 표면을 제공하는 단계와,
    j) 칩을 프로빙하는 단계와,
    k) 상기 프로빙된 패드을 구리 합금 배선으로 배선본딩하는 단계와,
    l) 상기 본딩된 칩을 약 250℃ ~ 약 450의 온도에서 어닐링하여 셀프 패시베이션 층을 개방 구리 패드 표면 및 구리 배선 상에 형성하는 단계
    를 포함하는 처리.
  9. 제 8 항에 있어서,
    단계 a) 이후에, 최적량의 구리 합금을 증착시킴으로써 단계 b)를 제거하는 처리.
  10. 구리 배선 구성요소로 배선 본딩된 구리 패드를 포함하는 집적 회로 구조 준비 처리에 있어서,
    셀프 패시베이션 구리 패드 구리 배선은 산화 작용 및 부식에의 저항력과, 상기 구리 패드와 금속화물 라인 사이와 상기 구리 패드와 구리 합금 배선을 잇는 본드사이의 계면 간의 향상된 부착력을 특징으로 하고,
    a) 유전체 내에 (이중의) 대머신 구조를 패터닝하여 배선 및 본드 패드를 형성하는 단계와,
    b) 금속 라이너를 증착시키는 단계와,
    c) 최종 구리 충진(Cu-fill)을 위한 시드 층(seed layer)으로서 구리 합금을 증착시키는 단계와,
    d) 상기 대머신 구조를 순수 구리로 충진하는 단계와,
    e) 저온(<200℃)에서 사전 CMP(Pre-CMP)하여 큰 구리 입자를 갖는 저저항 구리 박막을 형성하는 단계와,
    f) 구리 CMP 과충진을 제거하고, 이어서 리니어 CMP하는 단계와,
    g) 유전체 캡 층을 증착시키는 단계와,
    h) 약 250℃~ 약450℃의 온도 범위에서 CMP 어닐링하여 구리 표면 및 구리 리니어 계면에서 셀프 패시베이션 도펀트 다량 함유 층을 형성하는 단계와,
    i) 폴리이미드 층을 증착시키는 단계와,
    j) 개방 패드 영역에 리소그래피 및 에치 단계에 의해 폴리이미드의 패터닝및 비활성화를 완료하여 프로빙(probing)을 위한 깨끗한 구리 표면을 제공하는 단계와,
    k) 칩을 프로빙하는 단계와,
    l) 상기 프로빙된 패드을 구리 합금 배선으로 배선본딩하는 단계와,
    m) 상기 본딩된 칩을 약 250℃ ~ 약 450의 온도에서 어닐링하여 셀프 패시베이션 층을 개방 구리 패드 표면 및 구리 배선 상에 형성하는 단계
    를 포함하는 처리.
  11. 제 10 항에 있어서,,
    단계 a) 후에 적량의 구리 합금을 증착함으로써 단계 b)를 제거하는 처리.
  12. 구리 배선 구성요소로 배선 본딩된 구리 패드를 포함하는 집적 회로 구조 준비 처리에 있어서,
    셀프 패시베이션 구리 패드 구리 배선은 산화 작용 및 부식에의 저항력과, 상기 구리 패드와 금속화물 라인 사이와 상기 구리 패드와 구리 합금 배선을 잇는 본드사이의 계면 간의 향상된 부착력을 특징으로 하고,
    a) 유전체 내에 (이중의) 대머신 구조를 패터닝하여 배선 및 본드 패드를 형성하는 단계와,
    b) 금속 라이너를 증착시키는 단계와,
    c) 최종 구리 충진(Cu-fill)을 위한 시드 층(seed layer)으로서 구리 합금을 증착시키는 단계와,
    d) 상기 대머신 구조를 순수 구리로 충진하는 단계와,
    e) 저온(<200℃)에서 사전 CMP(Pre-CMP)하여 큰 구리 입자를 갖는 저저항 구리 박막을 형성하는 단계와,
    f) 구리 CMP 과충진을 제거하고, 이어서 리니어 CMP하는 단계와,
    g) 약 250℃~ 약400℃의 온도 범위에서 사전 CMP 어닐링하여 구리 표면 및 구리 리니어 계면에서 부분적으로 셀프 패시베이션 도펀트 다량 함유 층을 형성하는 단계와,
    h) 유전체 캡 층을 증착시키는 단계와,
    i) 약 300℃~ 약450℃의 온도 범위에서 포스트 CMP 어닐링하여 구리 표면 및 구리 리니어 계면에서 부분적으로 셀프 패시베이션 도펀트 다량 함유 층을 형성하는 단계와,
    j) 폴리 이미드 층을 증착시키는 단계와,
    k) 개방 패드 영역에 리소그래피 및 에치 단계에 의해 폴리이미드의 패터닝 및 비활성화를 완료하여 프로빙(probing)을 위한 깨끗한 구리 표면을 제공하는 단계와,
    l) 칩을 프로빙하는 단계와,
    m) 상기 프로빙된 패드을 구리 합금 배선으로 배선본딩하는 단계와,
    n) 상기 본딩된 칩을 약 250℃ ~ 약 450의 온도에서 어닐링하여 셀프 패시베이션 층을 개방 구리 패드 표면 및 구리 배선 상에 형성하는 단계
    를 포함하는 처리.
  13. 제 12 항에 있어서,
    단계 a) 후에 최적량의 구리 합금을 증착함으로써 단계 b)를 제거하는 처리.
  14. 구리 배선 구성요소로 배선 본딩된 구리 패드를 포함하는 집적 회로 구조 준비 처리에 있어서,
    셀프 패시베이션 구리 패드 구리 배선은 산화 작용 및 부식에의 저항력과, 상기 구리 패드와 금속화물 라인 사이와 상기 구리 패드와 구리 합금 배선을 잇는 본드사이의 계면 간의 향상된 부착력을 특징으로 하고,
    a) 유전체 내에 (이중의) 대머신 구조를 패터닝하여 배선 및 본드 패드를 형성하는 단계와,
    b) 금속 라이너를 증착시키는 단계와,
    c) 최종 구리 충진(Cu-fill)을 위한 시드 층(seed layer)으로서 구리 합금을 증착시키는 단계와,
    d) 상기 대머신 구조를 순수 구리로 충진하는 단계와,
    e) 저온(<200℃)에서 사전 CMP(Pre-CMP)하여 큰 구리 입자를 갖는 저저항 구리 박막을 형성하는 단계와,
    f) 구리 CMP 과충진을 제거하고, 이어서 리니어 CMP하는 단계와,
    g) 약 250℃~ 약450℃의 온도 범위에서 포스트 CMP 어닐링하여 구리 표면 및 구리 리니어 계면에서 부분적으로 셀프 패시베이션 도펀트 다량 함유 층을 형성하는 단계와,
    h) 유전체 캡 층을 증착시키는 단계와,
    i) 폴리 이미드 층을 증착시키는 단계와,
    j) 개방 패드 영역에 리소그래피 및 에치 단계에 의해 폴리이미드의 패터닝 및 비활성화를 완료하여 프로빙(probing)을 위한 깨끗한 구리 표면을 제공하는 단계와,
    k) 칩을 프로빙하는 단계와,
    l) 상기 프로빙된 패드을 구리 합금 배선으로 배선본딩하는 단계와,
    m) 상기 본딩된 칩을 약 250℃ ~ 약 450의 온도에서 어닐링하여 셀프 패시베이션 층을 개방 구리 패드 표면 및 구리 배선 상에 형성하는 단계
    를 포함하는 처리.
  15. 제 15 항에 있어서,
    단계 a) 후에 최적량의 구리 합금을 증착함으로써 단계 b)를 제거하는 처리.
  16. 제 1 항에 있어서,
    상기 구리 패드는 구리 합금인 구조.
  17. 제 1 항에 있어서,
    상기 구리 배선은 구리 합금인 내부 코어와 순수 구리의 외부 영역의 이중 층이며, 상기 구리 패드는 구리 합금인 구조.
  18. 제 1 항에 있어서,
    상기 구리 배선은 구리 합금이고 상기 구리 패드는 구리 합금인 구조.
KR1020037008825A 2000-12-28 2001-11-14 집적 회로 구조체와 그 마련 공정 KR100542120B1 (ko)

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US09/751,479 US6515373B2 (en) 2000-12-28 2000-12-28 Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys
PCT/US2001/043960 WO2002054491A2 (en) 2000-12-28 2001-11-14 Cu-pad/bonded/cu-wire with self-passivating cu-alloys

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US6515373B2 (en) 2003-02-04
EP1348235A2 (en) 2003-10-01
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