KR100553427B1 - 입력-출력 구조체 및 그 제조 방법 - Google Patents

입력-출력 구조체 및 그 제조 방법 Download PDF

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KR100553427B1
KR100553427B1 KR1020037009776A KR20037009776A KR100553427B1 KR 100553427 B1 KR100553427 B1 KR 100553427B1 KR 1020037009776 A KR1020037009776 A KR 1020037009776A KR 20037009776 A KR20037009776 A KR 20037009776A KR 100553427 B1 KR100553427 B1 KR 100553427B1
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South Korea
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layer
metal layer
metal
barrier
feature
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KR1020037009776A
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KR20030076628A (ko
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월커조지에프
골드블라트로날드디
그루버피터에이
호톤레이몬드알
페트라르카케빈에스
볼란트리차드피
쳉티엔-젠
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인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR20030076628A publication Critical patent/KR20030076628A/ko
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Abstract

본 발명은 C4(controlled-collapse chip connections)와 같은 솔더 범프 플립 칩 접속 및 와이어본드 모두에 적합한 공통 입력-출력(I/O) 영역을 형성하는 프로세스에 관한 것이다. 본 발명은 상호접속 재료로서 구리를 사용하는 반도체 칩에 특히 적합한데, 이러한 칩을 제조하는데 사용된 연성 유전체는 결합력으로 인해 손상되기 쉽다. 본 발명은 패드의 상부면 상에 귀금속(26)을 갖는 영역을 제공하는 한편 금속 상호 접속부의 높은 도전율을 유지하도록 확산 장벽(22)을 제공함으로써 손상의 위험을 감소시킨다. 기판(20) 내에 형성된 피처(21) 내에 금속층을 선택적으로 증착시키는 방법을 제공함으로써, 기판(20) 내에 I/O 영역을 형성하는 프로세스 단계가 감소된다. 본 발명의 I/O 영역은 와이어본드 또는 솔더 범프 접속에 사용될 수도 있기 때문에, 칩 상호접속에 대한 유연성을 증가시키며, 또한 프로세스 비용을 저감한다.

Description

입력-출력 구조체 및 그 제조 방법{A COMMON BALL-LIMITING METALLURGY FOR I/O SITES}
본 발명은 반도체 프로세싱에 관한 것으로서, 특히 집적 회로(IC) 칩을 패키징하는데 사용된 입력/출력(I/O) 영역을 위한 공통 볼 제한 금속층(a common ball-limiting metallurgy) 제조 프로세스에 관한 것이다.
반도체 디바이스의 제조에 있어서, 금속 라인들이 흔히 다중 레벨 구조 내의 유전체층에 매립되는데, 특히 제조 프로세스의 나중 단계("라인의 후단(back end of the line)" 또는 "BEOL")에서 매립된다. 금속 라인을 포함하는 마지막 층(종래 기술에서는 때론 터미널 비아 또는 TV 층으로 지칭됨)은 때론 "라인의 최후단(far back end of the line)" 또는 "far BEOL"로 지칭되는 프로세스에서 금속 라인과 접촉하도록 제조된 금속 패드를 갖는다. 상기 패드와 라인은 함께 칩을 다른 시스템 구성요소에 상호접속시킨다. 대다수 IC 칩들은 상호접속을 형성하기 위해 알루미늄(Al)을 사용하지만, 보다 최근에는 구리(Cu)가 사용된다.
상호접속을 형성하는데 Al보다 Cu를 사용하면, 도전율이 높아지고(저항이 낮 아짐), 용량 부하가 낮아지며, 전력 소모가 낮아지고, 크로스토크가 감소하며, 금속층이 적어지고, 잠재적인 제조 단계가 적어지는 등의 몇몇 장점이 있다. 그러나, Cu를 사용하면, Cu의 박층을 증착하기가 더 어려워지고, 아래의 실리콘에 의해 Cu가 오염될 가능성이 있어 성능이 저하되며, 라인들 간의 Cu의 이동에 의해 단락의 위험이 증가되며, 기판과 Cu 패드 및 라인들 간의 열 팽창으로 미스매칭이 발생하는 등의 문제점이 있다. Cu 상호접속의 장점을 최대한 활용하기 위해서, Cu 상호접속 형성 방법은 구리를 이용할 때의 이러한 문제점들을 극복해야 한다.
응용에 따라서, 다른 레벨의 상호접속과 같은, 칩과 다른 구성요소들 간의 상호접속에 다양한 기법이 사용된다. 일반적인 접속은 와이어 본드(wire bond) 및 솔더 범퍼를 포함한다.
와이어 본딩은 당해 기술분야에 공지되어 있는 기술로서 대다수 IC 칩에 사용되지만, 특히 칩 기능을 테스트하는 동안 상호접속 영역의 밀도가 한정되며, 결합 영역에서 칩에 기계적인 손상을 줄 가능성이 있다고 하는 문제점이 있다. 통상적인 와이어 본드의 예가 도 1b에 도시되어 있다. 이 종래 기술의 예에서, 기판(120)은 매립된 금속 라인(115)을 갖는다. 금속 라인은 알루미늄 또는 구리일 수 있다. 흔히 알루미늄(Al)으로 이루어지는 금속 패드(114)가 금속 라인(115) 위에 형성되며, 유전체(110)에 의해 지지된다. 통상적으로, 알루미늄 패드는 알루미늄의 반응성 때문에 표면 위에 쉽게 형성되는 산화물층(112)을 갖는다. 음파 본딩과 같은 공지된 기법을 이용하여, 흔히 금(Au)으로 이루어지는 와이어(118)가 패드에 결합된다. 금과 알루미늄 간의 와이어 본드를 형성하는데 있어서 한가지 문제 점은 금이 알루미늄과 금속간 화합물(intermetallics)을 형성하여 결합의 신뢰도를 저하시킨다는 것이다.
현재의 집적 회로, 특히 Cu 금속화를 이용하는 집적 회로에 나타나는 다른 문제점은, 채용된 로우-k 유전체가 연성이며(soft) 압력에 의한 손상에 민감하다는 것이다. 최상부층 상의 임계 도전성 포인트(critical conductive points)에 대해 테스트 프로브 세트를 푸쉬함으로써 회로 테스팅이 수행된다. 테스트 프로브와 패드 금속 간의 양호한 접촉을 형성하기 위해, 표면 산화물이 제거되어야 한다(흔히 "연마(scrubbing)"로 알려진 기술에 의해). 따라서, 특히 연성의 로우-k 유전체의 경우에, 칩은 기계적으로 손상될 가능성이 있다. 따라서, 테스트 프로브로 낮은 접촉 저항을 제공하는데 연마를 필요로 하지 않는 것이 I/O 패드를 형성하는데 바람직하다.
솔더 범프 기술(당해 분야에서는 플립 칩 기술로 알려져 있음)은 잠재적으로 더 높은 밀도 및 더 높은 성능을 제공하지만, 재작업(rework) 및 테스팅에 있어서 와이어 본딩에 비해 더 큰 어려움을 겪는다. 솔더 범프 기술의 일례로는 칩과 상호접속 기판 상에 솔더 범프가 제공되는 C4(controlled-collapse chip connection)가 있는데, 그 접속은 칩과 기판의 솔더 범프를 정렬하고 솔더를 그 접속에 리플로우시킴으로써 이루어진다. 솔더 범프는 도 1a에 도시된 바와 같이 볼 제한 금속층(ball-limiting metallurgy; BLM) 상에 솔더를 증착시켜 형성된다. 알루미늄 또는 구리일 수 있는 금속 피처(15)가 기판(16) 내에 형성된다. 솔더가 금속 피처(15) 내로 확산되는 것을 막기 위해, 다층 막의 금속(10)이 금속 피처 상에 캡 으로서 형성되고, 그 후 솔더가 다층 캡(10)의 최상부 상에 형성된다. 볼 제한 금속층(10)은 크롬을 포함하는 층(11), 구리를 포함하는 층(12), 금을 포함하는 층(13)과 같은 다층 금속을 이용하여 형성된다. 솔더 볼(18)은 마스크를 통한 증발과 같은 프로세스를 이용하여, 먼저 솔더(통상적인 솔더는 95%의 납과 5%의 주석으로 되어 있다)를 증착시켜 형성되며, 이는 기판(16)의 일부와 패드를 결합시킨다. 상호접속 기판에 플립 칩을 부착하는데 사용된 솔더는 비교적 높은 용융점을 가지며, 따라서 플립 칩을 포함하는 모듈이 후속 패키징시에 조립될 때 다른 보다 낮은 용융점의 솔더가 플립 칩 솔더 접속의 재용해없이 흐를 수도 있다. 그 다음에 솔더의 가열에 의해 볼(18)이 형성되는데, 이것은 볼로 리플로우하며, 표면 장력 때문에 BLM의 치수로 제한된다.
이상의 논의를 살펴보면, 성능을 저하시키지 않고 구리 금속화를 이용할 수 있으며, 프로세스 단계들을 축소하고 I/O 영역을 준비하는데 있어서의 유연성을 증가시킬 수 있는 I/O 영역을 제공할 필요가 있다.
본 발명은 와이어 본드 및 C4(controlled-collapse chip connection) 웨이퍼 모두를 위한 공통 영역으로서 사용될 수 있는 볼 제한 금속층(BLM)을 제조하는 프로세스를 제공함으로써 전술한 요구를 해결한다.
본 발명은, 라인과 I/O 패드 사이에 확산 장벽층을 제공하고, 본 발명의 I/O 영역이 형성되는 기판 내에 형성된 피처 내에 제 1 리세스된 금속층을 제공함으로 써, 금속 라인들의 오염의 문제를 해결한다.
본 발명은 또한 I/O 영역 상의 최상위 귀금속층을 제공함으로써 프로빙 및/또는 와이어 본딩에 의한 힘에 의해 칩에 손상이 야기되는 문제를 해결하는데, 상기 귀금속층은 산화물층의 존재를 제거하고, 보다 작은 결합력을 요구하며, 와이어 본딩에 금을 이용하는 경우에는 금속간 화합물이 형성되지 않는다.
본 발명은 I/O 영역을 형성하는데 사용된 프로세스 단계의 수를 감소시킨다고 하는 이점이 있으며, 와이어 본드 또는 BLM을 위한 공통 영역이 될 수 있는 유연한 영역을 제공하여 전체 프로세싱 비용을 저감시킨다. 본 발명의 일례에 따르면, 기판(20) 내에 형성된 피처(21) 내의 입력-출력 구조체 -상기 기판(20)은 상부면을 가지며, 상기 피처(21)는 피처 측벽 및 전기 전도성 재료(27) 위에 형성된 피처 바닥을 가짐- 가 제공되는데, 상기 입력-출력 구조체는 상기 피처 측벽 및 피처 바닥을 덮는, 장벽 바닥 및 장벽 측벽을 갖는 장벽층과, 적어도 상기 장벽 바닥을 덮는, 시드 바닥 및 시드 측벽을 갖는 금속 시드층과, 내부에 리세스가 형성되어 있어 그 상부면이 상기 기판의 상기 상부면보다 더 낮은, 적어도 상기 시드 바닥을 덮는 제 1 금속층과, 상기 제 1 금속층을 덮는 제 2 금속층을 포함한다.
본 발명의 다른 예에 따르면, 기판 내의 피처 내에 입력-출력 구조체를 형성하는 방법이 제공되는데, 상기 기판은 상기 상부면을 가지며, 상기 피처는 피처 측벽 및 피처 바닥을 가지며, 피처 바닥은 전기 전도성 재료 위에 형성되고, 상기 방법은 상기 기판의 상부면, 상기 피처 측벽 및 상기 피처 바닥을 덮는, 장벽 바닥 및 장벽 측벽을 갖는 장벽층을 증착하는 단계와, 상기 장벽층의 표면을 덮는 금속 시드층을 증착하는 단계와, 상기 시드층이 적어도 상기 장벽 바닥 상의 상기 시드층의 부분으로 감소되도록 적어도 상기 상부면으로부터 상기 시드층을 선택적으로 제거하는 단계와, 상기 제 1 금속층이 그 내부에 형성된 리세스를 가져서 상기 제 1 금속층의 상부면이 상기 기판의 상부면보다 더 낮아지도록, 상기 시드층의 상기 부분을 이용하여 제 1 금속층을 전기도금하는 단계와, 상기 제 1 금속층을 덮도록 제 2 금속층을 전기도금하는 단계를 포함한다.
본 발명의 신규한 특징들은 첨부한 청구범위에 개시되어 있다. 그러나, 본 발명 그 자체와, 본 발명의 다른 목적 및 이점들은 첨부한 도면과 함께 바람직한 실시예에 때한 다음의 상세한 설명을 참조하면 가장 잘 이해할 수 있을 것이다.
도 1a는 C4 영역에 대한 종래 기술의 BLM을 도시한 도면.
도 1b는 종래 기술의 와이어 본드 영역을 도시한 도면.
도 2a는 패키징 전에 제작된 최종 레벨의 출발 구조(starting structure)로서, 버킷 피처를 갖는 유전체 기판으로 덮힌 최상위 도전층, 장벽층 및 시드층을 도시한 도면.
도 2b는 도 2a에 도시된 구조의 상부면으로부터 시드층을 제거하고, 버킷 피처 내에 시드층의 일부를 남겨둔 구조를 도시한 도면.
도 2c는 도 2b의 구조 상에 제 1 금속층을 전기도금한 구조를 도시한 도면.
도 2d는 도 2c의 구조 상에 제 2 금속층을 전기도금한 구조를 도시한 도면.
도 3a는 도 2d로부터 장벽층을 선택적으로 제거하여 와이어본드 영역을 형성한 구조를 도시한 도면.
도 3b는 도 3a의 와이어본드 영역에 와이어를 접속한 후의 구조를 도시한 도면.
도 4a는 도 2d의 구조 상에 솔더를 도금하는 단계를 도시한 도면.
도 4b는 도 4a의 구조로부터 장벽층을 선택적으로 제거한 구조를 도시한 도면.
도 4c는 도 4b에서 도금된 솔더를 리플로우한 C4 구조를 도시한 도면.
도 5a는 마스크를 이용하여 도 3a의 구조 상으로 솔더를 증발시키는 단계를 도시한 도면.
도 5b는 도 5a에 도시된 솔더의 증발 후의 구조를 도시한 도면.
도 5c는 도 5b로부터 증발된 솔더를 리플로우시킨 C4 구조를 도시한 도면.
본 발명의 바람직한 실시예에 대한 하기의 상세한 설명에 있어서, 패키징 전에 공통 볼 제한 금속층(BLM)을 형성하기 위해 제작된 최종 레벨의 형성 단계를 상세히 설명한다. 이것은 단지 예시를 위한 것일 뿐이며, 본 발명은 다양한 기판 및 금속으로 실시될 수 있음에 유의하라. 도 2a에 도시된 바와 같이, 유전체층(20)은 금속 패드의 소정의 위치에, 그 내부에 형성된 피처를 갖는다. 유전체층(20)은 적어도 하나의 유전체 재료로 이루어지지만, 바람직하게는 실리콘 질화물(SiNx) 및 실리콘 이산화물(SiO2)과 같은 유전체층의 스택으로 이루어진다. Cu를 사용하여 형성된 도전성 피처(27)의 경우에, 기판(25)은 로우-k 유전체가 바람직하다. 피처(21)의 측벽 및 바닥을 포함하여, 기판(20)의 전체 표면 상에 라이너 재료층(22)이 증착될 수도 있다. 라이너(22)는 확산 장벽 및 접착 증진물 역할을 한다. 또한, 본 발명에 따른 라이너(22)는 전기 전도성이다. Cu가 도금되는 경우, 이 라이너 재류는 탄탈 질화물(TaN) 및 탄탈(Ta)의 화합물이 바람직하며, TaN은 도전성 피처(27)의 상부면과 유전체층(20)과 접촉하는 것이 바람직하다. 라이너/장벽층(22)의 표면 상에는 화학 기상 증착(CVD) 또는 바람직하게는 물리적 기상 증착(PVD)와 같은 당해 기술분야에서 공지되어 있는 증착 방법을 이용하여 금속 시드층(23)이 증착된다. 시드층(23)은 통상적으로 얇은데, 예를 들면 약 1000Å 정도이다. 시드층은 Cu가 바람직한데, 이것은 TaN/Ta에 양호하게 접착된다.
그 다음에, 바람직하게는 화학-기계적 폴리싱을 이용하여, 적으로 피처(21)의 바닥 및 측벽 상의 시드층(23)의 부분은 남겨두고, 시드층(23)이 라이너(22)의 적어도 상부면으로부터 선택적으로 제거되는데, 도 2b에 그 결과의 구조가 도시되어 있다. 도 2b에 도시된 잔여 시드층(23)은 장벽층(22)의 상부면과 평행하지만, 시드층(23)은 피처(21)의 측벽으로부터 부분적으로 제거될 수 있다. 그 다음에 시드층(23)을 이용하여 그리고 전류를 장벽층(22)에 인가하여 제 1 전기도금된 층(24)이 형성되는데, 도 2c에 그 결과의 구조가 도시되어 있다. 층(24)이 형성되기 전에, 시드층(23)의 표면은 세정되어야 한다. 이것은 공지되어 있는 브러시 세정(brush cleaning), 습식 세정, 또는 초음파에 의한 습식 세정과 같은 세정 방법 에 의해 이루어질 수 있다. 제 1 전기 도금된 층(24)에 적절한 재료로는 백금(Pt), 금(Au), 구리(Cu), 은(Ag), 솔더, 또는 니켈(Ni) 등이 있다. 도전성 피처(27)가 Cu인 경우, 전기 도금층(24)에 선택된 재료는, 예를 들어 Ni과 같이 바람직하게는 부가적인 확산 장벽 작용을 하도록 선택된다. 도금하는 동안, 층(24)은 시드층(23) 상에만 응집되며 장벽층(22) 상에는 도금되지 않을 것이다.
그 다음에, 제 2 전기 도금된 층(26)이 제 1 전기 도금된 층(24) 상에 형성되며, 이것은 공통 I/O 영역을 위한 패드 역할을 한다. 층(26)은 Au와 같은 귀금속이 바람직하다. 전기 도금 프로세스 동안 도전성 장벽층(22)에 다시 한번 전류가 인가되는데, 이는 Ni 조(bath)가 린스된 후 Ni 층(24)이 여전히 젖어 있는 상태에서 행해지는 것이 바람직하다. 층의 두께는 원하는 응용에 따라서 가변할 수 있으며, 도 2d에 도시된 바와 같이 상부면(22a) 위로 연장될 수도 있지만, 상부면(22a) 아래로 응집되거나 리세스되도록 형성될 수 있다. 바람직하게는 Ni인 층(24)은 바람직하게는 Cu인 시드층(23)과 바람직하게는 Au인 층(26) 사이에서 장벽층 역할을 한다. 본 발명에 따른 도 2d에 도시된 구성은, 예를 들어 와이어본드 또는 C4 영역을 위한 공통 I/O 영역으로 사용하기에 적합하며, 그 결과 비용 절감 및 유연성이 증가한다. 와이어본드 및 C4 영역에 대한 본 발명의 실시예의 예들을 이하에 설명한다.
제 1 실시예 : 와이어본드 패드
도 2d의 구조로 시작하여 와이어본드 I/O 영역으로 사용하기 위한 본 발명의 실시예가 형성될 수 있다. 도 3a에 도시된 바와 같이, 장벽층(22)이 바람직하게는 Au인 도금된 층(26)에 의해 덮이지 않은 상부면의 부분으로부터 선택적으로 제거된다. 이것은 당해 기술 분야에서 공지되어 있는 선택적인 폴리싱 방법 또는 HF/질산과 같은 습식 에칭에 의해 수행될 수 있다.
장벽층(22)의 선택적인 제거 후에, 선택적으로 스크래치 보호층(도시되지 않음)이 전 표면 상에 증착될 수도 있다. 당해 기술분야에서 공지되어 있는 통상적인 스크래치 보호층은 폴리이미드이다.
도 3b에 도시된 바와 같이, 바람직하게는 Au인 와이어(35)가 패드층(26)에 본딩된다. 또한 바람직하게는 Au인 와이어(35)는 열초음파(thermosonic) 본딩, 초음파 본딩, 또는 열압착(thermocompression) 본딩과 같은 공지된 표준 기법을 이용하여 패드(26)에 본딩된다. 본 발명에 따라 형성된 패드층(26)은, 종래 기술에 비해, 와이어(35)와 패드(26)가 모두 Au이기 때문에 본딩에 보다 낮은 힘이 요구된다고 하는 이점을 갖는다. 집적 회로를 테스트하는 동안, 종래 기술의 알루미늄 패드는 충분히 큰 표면을 요구하며, 따라서 일반적으로 알루미늄의 표면 상에 형성되는 알루미늄 산화물층을 뚫기 위해 테스트 프로브가 패드의 표면을 연마할 수 있다. 종래 기술의 알루미늄 패드와는 달리, 본 발명에 따라 Au로부터 형성된 패드(26)는, 금이 귀금속이기 때문에 산화물이 없는 표면을 가질 것이다. 테스트하는 동안의 연마가 필요치 않기 때문에, 본 발명에 따라 형성된 와이어본드 패드(26)는 종래 기술의 패드보다 더 작을 수 있으며, 그 결과 I/O 영역의 밀도가 증가될 수 있다.
제 2 실시예 : 도금된 솔더를 갖는 C4 영역
도 2d의 구조는 또한 도금에 의해 솔더 범프가 형성되는 C4 영역으로서 사용하기 위한 본 발명의 일실시예에 대한 출발 구조로서 사용될 수 있다.
본 실시예에서, 도 4a에 도시된 바와 같이, 도전성 장벽층(22)에 전류를 인가함으로써 제 3 층(45)이 층(26) 상으로 전기도금된다. 또한, 장벽층(22)은 TaN 및 Ta의 화합물이 바람직하다. 층(45)을 형성하는데 사용된 재료는 솔더로서, 97%의 납(Pb)과 3%의 주석(Sn)이 바람직하지만, 공지되어 있는 바와 같이, 많은 다른 적절한 다양한 솔더가 사용될 수도 있다.
다음에, 도 4b에 도시된 바와 같이, 바람직하게는 공지되어 있는 습식 에칭 기법에 의해, 도전성 장벽층(22)이, 솔더층(45)은 남겨둔 채 선택적으로 제거된다.
마지막으로, 도 4c에 도시된 바와 같이, 공지되어 있는 표준 기술을 이용하여 솔더가 리플로우되어 C4 솔더 범프(45)를 형성한다.
제 3 실시예 : 솔더가 증발된 C4 영역
본 발명의 다른 실시예에서는, 도 2d의 장벽층(22)이 선택적으로 제거된 도 3a의 구조로부터 시작하여 C4 솔더 범프가 형성될 수 있다. 도 5a에 도시된 바와 같이, 기판의 표면 위에서 마스크(52)가 픽처 내에 수용된다. 마스크 재료는 솔더의 증발에 사용된 공지되어 있는 임의의 적절한 재료로서, 몰리브덴(Mo)이 바람직하다. 솔더의 증발은 당해 기술 분야에서 공지되어 있으며, 임의의 적절한 솔더가 사용될 수도 있지만, 97%의 Pb와 3%의 Sn의 혼합이 바람직하다.
증발 후에, 도 5b에 도시된 바와 같이 패드층(26) 상에 Pb와 Sn의 증발된 층(55)을 남겨두고 마스크(52)가 제거된다.
그 다음에, 도 5c에 도시된 바와 같이, 솔더가 리플로우하여 C4 솔더 범프(55)를 형성한다. 요약하면, 본 발명에 따라 형성된 공통 BLM 구조는 귀금속을 사용하여 I/O 패드를 형성하므로 프로세스 단계들을 단순화함으로써 비용을 절감할 수 있게 하며 보다 작은 패드 사이즈로 I/O 영역 밀도를 증가시킬 수 있게 한다.
이상, 특정 실시예를 통해 본 발명을 설명하였지만, 당업자에게 자명한많은 대안들, 변형 및 변경이 이루어질 수 있다. 따라서, 본 발명은 본 발명의 범주 및 사상 및 첨부한 청구범위 내에 있는 모든 그러한 대안들, 변형 및 변경들을 포함한다.
본 발명의 I/O 영역을 위한 공통 볼 제한 금속층은 집적 회로(IC) 칩을 패키징하는데 유용하며, 특히 Cu 상호접속부 및 연성의 로우-k 유전체 재료를 포함하는 IC 칩을 패키징하는데 유용하다.

Claims (18)

  1. 기판(20) 내에 형성된 피처(21) 내의 입력-출력 구조체 -상기 기판(20)은 상부면을 가지며, 상기 피처(21)는 피처 측벽 및 전기 전도성 재료(27) 위에 형성된 피처 바닥을 가짐- 에 있어서,
    상기 피처 측벽 및 피처 바닥을 덮는, 장벽 바닥 및 장벽 측벽을 갖는 장벽층(22)과,
    적어도 상기 장벽 바닥을 덮는, 시드 바닥 및 시드 측벽을 갖는 금속 시드층(23)과,
    상기 시드층의 모든 면을 완전히 덮는 제 1 금속층(24) -상기 시드층은 상기 장벽층과 상기 제 1 금속층에 의해 완전히 둘러싸이고, 상기 제 1 금속층은 그 내부에 형성된 리세스를 가지며, 상기 제 1 금속층(24)은 그 상부면이 상기 기판(20)의 상기 상부면보다 더 낮고, 상기 제 1 금속층(24)은 구리, 백금, 니켈, 금, 은 및 솔더로 이루어진 그룹으로부터 선택된 재료를 포함함- 과,
    상기 제 1 금속층(24)을 덮는 제 2 금속층(26) -상기 제 2 금속층은 귀금속으로 이루어짐- 을 포함하는 입력-출력 구조체.
  2. 제 1 항에 있어서,
    상기 귀금속은 금인 입력-출력 구조체.
  3. 제 1 항에 있어서,
    상기 귀금속은 금, 백금, 팔라듐으로 이루어진 그룹으로부터 선택되는 입력-출력 구조체.
  4. 제 1 항에 있어서,
    상기 시드층은 구리를 포함하는 입력-출력 구조체.
  5. 삭제
  6. 제 1 항에 있어서,
    상기 장벽층은 탄탈 및 탄탈 질화물을 포함하는 입력-출력 구조체.
  7. 제 6 항에 있어서,
    상기 탄탈 질화물은 상기 기판과 접촉하는 입력-출력 구조체.
  8. 제 1 항에 있어서,
    상기 제 2 금속층에 본딩된 와이어를 더 포함하는 입력-출력 구조체.
  9. 제 8 항에 있어서,
    상기 와이어는 금을 포함하고, 상기 귀금속은 금인 입력-출력 구조체.
  10. 제 1 항에 있어서,
    상기 제 2 금속층에 접속된 솔더 볼을 더 포함하는 입력-출력 구조체.
  11. 제 1 항의 입력-출력 구조체를 제조하는 방법에 있어서,
    상기 기판(20)의 상부면, 상기 피처 측벽 및 상기 피처 바닥을 덮는 장벽층(22)을 증착하는 단계 -상기 장벽층은 장벽 바닥 및 장벽 측벽을 가짐- 와,
    상기 장벽층(22)의 표면을 덮는 금속 시드층(23)을 증착하는 단계와,
    상기 시드층(23)이 적어도 상기 장벽 바닥 상의 상기 시드층(23)의 부분으로 감소되도록 적어도 상기 상부면으로부터 상기 시드층(23)을 선택적으로 제거하는 단계와,
    제 1 금속층(24)이 그 내부에 형성된 리세스를 가져서 상기 제 1 금속층(24)의 상부면이 상기 기판(20)의 상부면보다 더 낮아지도록, 상기 시드층(23)의 상기 부분을 이용하여 상기 제 1 금속층(24)을 전기도금하는 단계와,
    제 2 금속층(26)을 전기도금하여, 상기 제 2 금속층(26)이 상기 제 1 금속층(24)을 덮는 단계를 포함하는 방법.
  12. 제 11 항에 있어서,
    상기 시드층을 증착하는 단계는 물리적 기상 증착 또는 화학 기상 증착을 포함하는 방법.
  13. 제 11 항에 있어서,
    상기 시드층을 선택적으로 제거하는 단계는 화학-기계적 폴리싱(CMP)을 포함하는 방법.
  14. 제 11 항에 있어서,
    와이어를 상기 제 2 금속층에 본딩하는 단계를 더 포함하는 방법.
  15. 제 14 항에 있어서,
    상기 와이어를 본딩하는 단계는 열초음파(thermosonic) 본딩, 초음파 본딩, 및 열압착(thermocompression) 본딩으로 이루어진 그룹으로부터 선택되는 방법.
  16. 제 11 항에 있어서,
    상기 제 2 금속층에 접속된 솔더 볼을 형성하는 단계를 더 포함하는 방법.
  17. 제 16 항에 있어서,
    상기 솔더 볼을 형성하는 단계는 도금(plating)을 포함하는 방법.
  18. 제 16 항에 있어서,
    상기 솔더 볼을 형성하는 단계는 증발을 포함하는 방법.
KR1020037009776A 2001-02-09 2001-12-19 입력-출력 구조체 및 그 제조 방법 KR100553427B1 (ko)

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US09/781,121 2001-02-09
PCT/US2001/049137 WO2002065540A1 (en) 2001-02-09 2001-12-19 A common ball-limiting metallurgy for i/o sites

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