CN1835231A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN1835231A
CN1835231A CNA2006100717151A CN200610071715A CN1835231A CN 1835231 A CN1835231 A CN 1835231A CN A2006100717151 A CNA2006100717151 A CN A2006100717151A CN 200610071715 A CN200610071715 A CN 200610071715A CN 1835231 A CN1835231 A CN 1835231A
Authority
CN
China
Prior art keywords
pad
bonding wire
semiconductor chip
chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006100717151A
Other languages
English (en)
Other versions
CN100464418C (zh
Inventor
太田充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1835231A publication Critical patent/CN1835231A/zh
Application granted granted Critical
Publication of CN100464418C publication Critical patent/CN100464418C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H01L2224/78314—Shape
    • H01L2224/78317—Shape of other portions
    • H01L2224/78318—Shape of other portions inside the capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85053—Bonding environment
    • H01L2224/85095—Temperature settings
    • H01L2224/85099—Ambient temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T408/00—Cutting by use of rotating axially moving tool
    • Y10T408/55—Cutting by use of rotating axially moving tool with work-engaging structure other than Tool or tool-support
    • Y10T408/563—Work-gripping clamp
    • Y10T408/5638—Adjustable relative to tool-axis

Abstract

本发明提供一种能够实现高集成度的半导体装置及其制造方法。根据本发明一个实施例的多芯片模块包括：具有第一焊盘的第一半导体芯片；具有第二焊盘的第二半导体芯片，所述第二焊盘比第一焊盘更薄；以及与所述第一焊盘和第二焊盘中的每一个相连的焊线，所述第一焊盘与所述焊线的第一焊接侧端部相连，所述第二焊盘与所述焊线的第二焊接侧端部相连。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。特别是，本发明涉及具有多个半导体芯片的半导体装置及其制造方法。
背景技术
为了适应近来电子装置小型化的趋势，存在以高密度或高集成度封装半导体芯片的日益增加的要求。为了该目标，开发了通过将多个半导体芯片集成到一个封装中而制备的多芯片模块(例如，参见日本特开2003-273314、2000-68316和2000-114452号公报)。
通常，多芯片模块在引线框上具有多个半导体芯片，它们通过任意连接晶体管、电阻器或其他的此类元件构成电路来获得。图5是示出传统的多芯片模块10的结构的示意图，其中，两个半导体芯片12安装在同一引线框11上。如图5所示，在引线框11的岛上，半导体芯片12面朝上(face up)经由管芯(die)安装部件13相连。形成在每一个半导体芯片12上的是电路配线14和焊盘15。各个芯片上的焊盘15经由焊线16相互连接。
顺带提及的是，在前述的多芯片模块10中，用于通过焊线16焊接半导体芯片12的焊盘15形成为厚度足以抑制对半导体芯片的破坏，以便使焊接时对半导体芯片的破坏最小。
随着近来半导体芯片的高密度集成，需要减小电路配线14的间距(pitch)，以及减小每个电路配线14的厚度，用于实现具有高尺寸精度的处理。然而，电路配线14和焊盘15是同时形成的，因此，如果焊盘15很厚，则电路配线14也相应地很厚。这样，就难以减小电路配线14的间距以及使半导体芯片12小型化。另外，在仅刻蚀电路配线14的情况中，需要附加的步骤来增加焊盘15的厚度，这使成本升高。
发明内容
根据本发明的一个方面，一种半导体装置包括：多个半导体芯片，其包括：具有第一焊盘的第一半导体芯片；和具有第二焊盘的第二半导体芯片，所述第二焊盘比第一焊盘更薄；以及与所述第一焊盘和第二焊盘中的每一个相连的焊线，所述第一焊盘与所述焊线的第一焊接侧端部相连，所述第二焊盘与所述焊线的第二焊接侧端部相连。因此，能够降低电路配线的厚度，以小间距、高尺寸精度形成电路配线，并提供高集成度的半导体装置。
根据本发明的另一方面，提供一种制造包括多个半导体芯片的半导体装置的方法，其包括：布置具有第一焊盘的第一半导体芯片；布置具有第二焊盘的第二半导体芯片，所述第二焊盘比第一焊盘更薄；以及将焊线的一端焊接到第一焊盘，然后将所述焊线的另一端焊接到第二焊盘。因此，能够降低电路配线的厚度，而不需要增加焊盘厚度的附加步骤，并且能够以小间距、高尺寸精度形成电路配线。
附图说明
从以下说明并结合附图，本发明的上述及其他目的、优点和特征将更加明显，其中：
图1是示出根据本发明第一实施例的半导体装置的结构的示意图；
图2A示出根据本发明第一实施例的半导体装置的制造方法；
图2B示出根据本发明第一实施例的半导体装置的制造方法；
图2C示出根据本发明第一实施例的半导体装置的制造方法；
图2D示出根据本发明第一实施例的半导体装置的制造方法；
图3A示出如何连接第一焊盘和焊线；
图3B示出如何连接第二焊盘和焊线；
图4是示出根据本发明第二实施例的半导体装置的结构的示意图；以及
图5是示出传统的半导体装置的结构的示意图；
具体实施方式
在此结合示出的实施例来描述本发明。本领域技术人员会认识到，利用本发明的教导能够实现许多替代实施例，并且本发明不限于为了说明目的所示出的实施例。
第一实施例
参考图1，说明根据本发明第一实施例的半导体装置。图1是示出作为本实施例的半导体装置的多芯片模块100的结构的示意图。如图1所示，多芯片模块100包括引线框101、第一半导体芯片102a、第二半导体芯片102b和管芯安装部件103。从现在开始，给出两个半导体芯片(即第一半导体芯片102a和第二半导体芯片102b)安装在同一引线框101上的情况的说明。本实施例的特征在于用于在第一半导体芯片102a和第二半导体芯片102b之间连接的焊盘105。
引线框101是支持第一半导体芯片102a和第二半导体芯片102b的衬底。形成在引线框101上的是与第一半导体芯片102a和第二半导体芯片102b相连的岛(未示出)。在相应的岛上，第一半导体芯片102a和第二半导体芯片102b面朝上通过管芯安装部件103相连。
第一半导体芯片102a和第二半导体芯片102b在之前的步骤中通过任意连接晶体管、电阻器或其他此类元件构成电路。此外，在第一半导体芯片102a上，形成电路配线104和第一焊盘105a。另一方面，在第二半导体芯片102b上，形成电路配线104和第二焊盘105b。电路配线104和焊盘105通常通过相同的处理(例如光刻或构图)同时形成。例如Al、AlSi、AlSiCu或Cu等导电材料可以用作焊盘105的材料。稍后详细描述焊盘105。
此外，第一焊盘105a与第二焊盘105b经由焊线106电连接。例如Al、AlSi、AlNi或AlSiNi等含Al材料可以用作焊线106的材料。此外，可以根据众所周知的楔焊方法将焊盘105焊接到焊线106。楔焊方法是指使用楔子的丝焊方法，其用超声波振动楔子的边缘将焊线106压在焊盘105上，在一定荷重之下通过超声波在室温将焊线焊接到焊盘上。此外，Au线可以用作焊线106来通过低温加热进行楔焊。
下面参考图2A到2D，说明本实施例的半导体装置的制造方法。通过上面所述的楔焊将焊盘105焊接到焊线106。为了简化说明，从图2A到2D中省略了电路配线104等。
首先，如图2A所示，预先从焊线卷轴将焊线106提供到楔子107的边缘。然后，向下移动楔子107，以使焊线106与第一焊盘105a相接触。此后，进一步向下移动楔子107，以将焊线106压在第一焊盘105a上。
如图2B所示，当焊线106压在第一焊盘105a上时，从楔子107传递超声波振动，以将第一焊盘105a焊接到焊线106。这里，第一焊盘105a和焊线106之间的接合称为第一焊接。在第一焊接中，焊线106的末端(tip end)并不用于与焊盘105a焊接，而保持未使用。
接下来，如图2C所示，当焊线106焊接到第一焊盘105a时，将楔子107向上移动到恰好在第二焊盘105b之上的位置。之后，如图2D所示，再次向下移动楔子107，以将焊线106压在第二焊盘105b上。以这种方式，在压住焊线106时通过楔子107施加超声波振动，以将第二焊盘105b焊接到焊线106上。如上所述，焊线106连接在第一焊盘105a和第二焊盘105b之间，形成环路。这里，第二焊盘105b和焊线106之间的接合称为第二焊接。另外，连接在第一焊盘105a和第二焊盘105b之间的焊线106的环路的第一焊接侧的端部称为第一焊接侧端部，而其第二焊接侧的端部称为第二焊接侧端部。
之后，扯下并切断焊线106。这样，在第二焊接处，存在焊线106被扯下的痕迹。如上所述，第一焊接和第二焊接之间的焊线形状是不同的。因此，能够通过显微镜，根据焊线106的形状，容易地目测检查焊线106的环路的端部是在第一焊接侧还是在第二焊接侧。在完成对所有部分的焊接之后，将引线框101、半导体芯片102和焊线106全部密封，从而就完成了多芯片模块100。
下面，说明本实施例的焊盘105。如上所述，焊盘105用于在第一半导体芯片102a和第二半导体芯片102b这两个半导体芯片之间电连接。
如图3A所示，在首先焊接到焊线106的第一焊盘105a中，具有自由端的焊线106从楔子107延伸预定的长度，并在一定的角度与第一焊盘105a形成接触。焊线106在其端部没有球状物，并且其直径是基本一致的。通常，第一焊盘105a和焊线106之间的角度为45°。随后，进一步向下移动楔子107，以将焊线106的延伸部分压在第一焊盘105a上。当被压在焊线106上时，第一焊盘105受到相当大的破坏。此时，如果焊盘105的厚度不够厚，则半导体芯片102a可能受到破坏。
另一方面，在第一焊盘105a焊接到焊线106之后，将第二焊盘105b焊接到焊线106。因此，焊线106的中间部分与第二焊盘105b形成接触。焊线106将第一焊盘105a和第二焊盘105b连接，以形成环路，并由此被向上拉伸。因此，如图3B所示，当与第二焊盘105b形成接触时，焊线106沿楔子107弯曲并与第二焊盘105b几乎平行延伸。因此，在楔子107向下移动以将焊线106压在第二焊盘105b上时所施加的破坏小于第一焊盘105a的破坏。
另外，在焊接时，并不是所有超声波振动的能量都用于在焊盘105和焊线106之间焊接；在焊线106上存在能量损失。亦即，在用于焊接第一焊盘105a和焊线106的第一焊接操作时，焊线106的末端是自由端。因此，在焊接操作期间所产生的振动能量仅在焊线106的一侧浪费，即在焊线106的供给侧。
另一方面，在焊接第一焊盘105a之后，将第二焊盘105b焊接到焊线106。此时，焊线106与第一焊盘105a相连接。在这种状态下，在焊线106的两侧，即供给侧和第一焊接侧，都存在在焊接操作期间所产生的振动能量的损失。因此，用于将第二焊盘105b焊接到焊线106的振动能量小于用于焊接第一焊盘105a的振动能量。因此，在第二焊接操作中焊接的第二焊盘105b比在第一焊接操作中焊接的第一焊盘105a受到更小的破坏。
因此，在焊接第一焊盘105a和焊线106之后，将第二焊盘105b焊接到焊线106，由此能够将第二焊盘105b构造得比第一焊盘105a更薄。
由于该原因，如果第二焊盘105b比首先焊接的第一焊盘105a更薄，第二半导体芯片102b的内部电路不会因与焊线106焊接而受到这样的破坏。如上所述，能够根据焊线106的残余部分的形状，通过显微镜，容易地目测检查第一焊盘105a(或第二焊盘105b)是在第一焊接侧还是在第二焊接侧。
以这种方式，首先将焊线106焊接到厚的第一焊盘105a，然后再焊接到薄的第二焊盘105b。亦即，把已焊接到第一焊盘105a的焊线106焊接到比第一焊盘105a更薄的第二焊盘105b。以这种结构，即使第二焊盘105b薄，也能够在不破坏半导体芯片102的情况下进行满意的焊接。
此外，焊盘105一般与电路配线104通过相同的处理同时形成。因此，在第二半导体芯片102b中，要与第二焊盘105b一起形成的电路配线104能够以较小的厚度形成。因此，能够以小间距、高尺寸精度形成电路配线104，以提高第二半导体芯片102b的集成度。此外，能够减小半导体芯片102b的尺寸，从而能够减小整个多芯片模块100的尺寸。
此外，在第二半导体芯片102b中，不必形成厚的第二焊盘105b。因此，与电路配线104分离形成第二焊盘105b的步骤是不必要的。因此，能够防止制造过程中步骤数量的增加，从而降低制造成本。
输出芯片提供电力，并包括大电流类型的功率MOS晶体管。因此，需要输出芯片具有厚的电路配线，用于承受大的电流量。此外，控制电路芯片是其中形成有逻辑电路的LSI电路芯片。需要控制电路芯片具有薄的电路配线，用于提高集成度。因此，例如，具有厚的第一焊盘105a的第一半导体芯片102a用作需要具有厚电路配线的输出芯片，而具有薄的第二焊盘105b的第二半导体芯片102b用作具有高集成度的控制电路芯片。
第二实施例
参考图4，说明根据本发明第二实施例的半导体装置。图4是示出作为本实施例的半导体装置的多芯片模块100的结构的示意图。本实施例与第一实施例的区别在于，第二半导体芯片102b安装到第一半导体芯片102a上，第一半导体芯片102a连接到引线框101上。在图4中，与第一实施例中相同的元件用相同的参考标记表示，并省略了其说明。
在根据本实施例的多芯片模块100中，与第一半导体芯片102a相连的岛(未示出)形成在引线框101上。第一半导体芯片102a面朝上通过管芯安装部件103连接到该岛上。
形成在第一半导体芯片102a上的是在之前的步骤中形成的电路配线104和第一焊盘105a。此外，与第二半导体芯片102b相连的岛108形成在第一半导体芯片102a上。
第二半导体芯片102b面朝上通过管芯安装部件103连接到第一半导体芯片102a的岛108上。第二半导体芯片102b具有足够小的芯片尺寸，从而不覆盖形成在第一半导体芯片102a上的焊盘105a。形成在第二半导体芯片102b上的是电路配线104和第二焊盘105b。此外，第二焊盘105b比第一焊盘105a更薄。
第一焊盘105a与第二焊盘105b通过焊线106电连接。如上所述，在将厚的第一焊盘105a与焊线106焊接之后，焊接第二焊盘105b，以防止半导体芯片102被破坏。
因此，能够将第二半导体芯片102b的电路配线104构造得薄，以提高第二半导体芯片102b的集成度。因此，例如，第一半导体芯片102a可以用作输出芯片，其需要具有厚电路配线，用于承受大的电流量。另外，第二半导体芯片102b可以用作控制电路芯片，其需要具有薄电路配线，用于提高集成度。因此，能够降低制造成本，提高多芯片模块100的集成度。
本发明可应用于在三维空间层叠半导体芯片102的多芯片模块。
顺带提及的是，本实施例说明了将安装在第一半导体芯片102a上的第二半导体芯片102b的第二焊盘105b构造得比第一焊盘105a更薄的例子，但是本发明不限于此。通过改变焊接顺序，在第二半导体芯片102b之下的第一半导体芯片102a的第一焊盘105a可以比第二焊盘105b更薄。亦即，在三维空间层叠芯片的多芯片模块中，无论选择上部的半导体芯片还是下部的半导体芯片，都能将第二焊接侧上的焊盘构造得更薄。
此外，不用说，本发明适用于具有多个岛的封装。
如上所述，考虑到多芯片模块100的半导体芯片102与焊线106之间焊接时的焊接顺序，与半导体芯片102中的一个相连的焊盘105能够以较小的厚度以低成本形成。因此，能够降低半导体芯片102的电路配线104的线间距，并且由此能够容易地减小半导体芯片102的尺寸。这有助于高集成度和小尺寸半导体装置的生产。
很显然，本发明不限于上述实施例，其可以修改和变化，而不脱离本发明的范围和要旨。

Claims (11)

1.一种半导体装置，其包括：
多个半导体芯片，包括：
具有第一焊盘的第一半导体芯片；和
具有第二焊盘的第二半导体芯片，所述第二焊盘比第一焊盘更薄；以及
与所述第一焊盘和第二焊盘中的每一个相连的焊线。
2.如权利要求1所述的半导体装置，其中，所述焊线是包含Al的金属。
3.如权利要求1所述的半导体装置，其中，所述第一半导体芯片是输出芯片，所述第二半导体芯片是控制电路芯片。
4.如权利要求3所述的半导体装置，其中，所述第一半导体芯片具有功率MOS晶体管。
5.如权利要求1所述的半导体装置，其中，在将所述第二焊盘焊接到所述焊线时施加到所述第二焊盘的外力小于将所述第一焊盘焊接到所述焊线时施加到所述第一焊盘的外力。
6.一种制造包括多个半导体芯片的半导体装置的方法，其包括：
布置具有第一焊盘的第一半导体芯片；
布置具有第二焊盘的第二半导体芯片，所述第二焊盘比第一焊盘更薄；以及
将焊线的一端焊接到第一焊盘，然后将所述焊线的另一端焊接到第二焊盘。
7.如权利要求6所述的制造半导体装置的方法，其中，所述第一焊盘和第二焊盘中的每一个都通过楔焊焊接到所述焊线。
8.如权利要求6所述的制造半导体装置的方法，其中，所述焊线是包含Al的金属。
9.如权利要求6所述的制造半导体装置的方法，其中，所述第一半导体芯片是输出芯片，所述第二半导体芯片是控制电路芯片。
10.如权利要求9所述的制造半导体装置的方法，其中，所述第一半导体芯片具有功率MOS晶体管。
11.如权利要求6所述的制造半导体装置的方法，其中，在将所述第二焊盘焊接到所述焊线时施加到所述第二焊盘的外力小于将所述第一焊盘焊接到所述焊线时施加到所述第一焊盘的外力。
CNB2006100717151A 2005-03-18 2006-03-16 半导体装置及其制造方法 Expired - Fee Related CN100464418C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005079520 2005-03-18
JP2005079520A JP4666592B2 (ja) 2005-03-18 2005-03-18 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN1835231A true CN1835231A (zh) 2006-09-20
CN100464418C CN100464418C (zh) 2009-02-25

Family

ID=37002914

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100717151A Expired - Fee Related CN100464418C (zh) 2005-03-18 2006-03-16 半导体装置及其制造方法

Country Status (3)

Country Link
US (2) US7256485B2 (zh)
JP (1) JP4666592B2 (zh)
CN (1) CN100464418C (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009194153A (ja) * 2008-02-14 2009-08-27 Toshiba Corp 半導体装置の製造方法及び超音波接合装置
US20100181675A1 (en) * 2009-01-16 2010-07-22 Infineon Technologies Ag Semiconductor package with wedge bonded chip
US20100193920A1 (en) * 2009-01-30 2010-08-05 Infineon Technologies Ag Semiconductor device, leadframe and method of encapsulating
US8022558B2 (en) * 2009-02-13 2011-09-20 Infineon Technologies Ag Semiconductor package with ribbon with metal layers
CN102637613B (zh) * 2012-05-09 2015-07-01 四川立泰电子有限公司 一种粗铝丝引线键合的实现方法
DE102021118992A1 (de) * 2020-08-18 2022-02-24 Infineon Technologies Ag Bondingpad-metallschichtstruktur enthaltende halbleitervorrichtung

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582013B2 (ja) * 1991-02-08 1997-02-19 株式会社東芝 樹脂封止型半導体装置及びその製造方法
JPS59181040A (ja) * 1983-03-30 1984-10-15 Toshiba Corp 半導体装置の製造方法
JPS61189652A (ja) * 1985-02-19 1986-08-23 Toshiba Corp 半導体装置
JPS63143826A (ja) * 1986-12-08 1988-06-16 Nec Corp 半導体装置
US5425215A (en) * 1993-04-16 1995-06-20 Brown & Williamson Tobacco Corporation Apparatus for packaging loose leaf material
JP3837181B2 (ja) * 1996-03-29 2006-10-25 三洋電機株式会社 半導体素子及びそれを用いる線状光源
JPH10335366A (ja) * 1997-05-30 1998-12-18 Sanyo Electric Co Ltd 半導体装置
JP2000068316A (ja) 1998-08-21 2000-03-03 Sony Corp 集積回路装置
JP3378809B2 (ja) 1998-09-30 2003-02-17 三洋電機株式会社 半導体装置
JP3869562B2 (ja) * 1998-10-16 2007-01-17 三洋電機株式会社 半導体装置の製造方法
JP3865055B2 (ja) * 2001-12-28 2007-01-10 セイコーエプソン株式会社 半導体装置の製造方法
JP2003273314A (ja) 2002-03-18 2003-09-26 Toyota Motor Corp マルチチップモジュールの接合方法
JP2004014637A (ja) * 2002-06-04 2004-01-15 Sony Corp 半導体装置及びワイヤボンディング方法
TWI245397B (en) * 2004-06-29 2005-12-11 Advanced Semiconductor Eng Leadframe with a chip pad for double side stacking and method for manufacturing the same

Also Published As

Publication number Publication date
CN100464418C (zh) 2009-02-25
US7256485B2 (en) 2007-08-14
US20070224805A1 (en) 2007-09-27
JP4666592B2 (ja) 2011-04-06
US20060220231A1 (en) 2006-10-05
US7331737B2 (en) 2008-02-19
JP2006261542A (ja) 2006-09-28

Similar Documents

Publication Publication Date Title
CN1204623C (zh) 半导体装置
CN100536119C (zh) 半导体器件及其制造方法
CN1870256A (zh) 连接主装置元件的带自动键合封装
JP2003243436A (ja) バンプの形成方法、バンプ付き半導体素子及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
KR101153693B1 (ko) 반도체 장치
US20060216863A1 (en) Method of manufacturing semiconductor device
JP2008034567A (ja) 半導体装置及びその製造方法
CN1835231A (zh) 半导体装置及其制造方法
JP2003243442A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
CN2838038Y (zh) 半导体封装物
JP2003243441A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
CN101060090A (zh) 半导体装置的制造方法
US8587135B2 (en) Semiconductor device having electrode/film opening edge spacing smaller than bonding pad/electrode edge spacing
CN1700434A (zh) 在焊盘内的测试电路
CN1532930A (zh) 半导体装置、电子设备及它们的制造方法，以及电子仪器
US7566970B2 (en) Stacked bump structure and manufacturing method thereof
TWI260753B (en) Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
US20090289361A1 (en) Semiconductor device and method of manufacturing a semiconductor device
CN1779958A (zh) 复晶球阵列封装的结构
JP2010087403A (ja) 半導体装置
CN1851912A (zh) 芯片封装体
US8110907B2 (en) Semiconductor device including first substrate having plurality of wires and a plurality of first electrodes and a second substrate including a semiconductor chip being mounted thereon, and second electrodes connected with first electrodes of first substrate
CN1481004A (zh) 将集成电路连接到基片上的方法及相应电路配置
CN1808711A (zh) 封装体及封装体模块
KR20070087765A (ko) 적층형 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: RENESAS ELECTRONICS CORPORATION

Free format text: FORMER NAME: NEC CORP.

CP01 Change in the name or title of a patent holder

Address after: Kanagawa, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Patentee before: NEC Corp.

CP02 Change in the address of a patent holder

Address after: Tokyo, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Patentee before: Renesas Electronics Corporation

CP02 Change in the address of a patent holder
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090225

Termination date: 20190316

CF01 Termination of patent right due to non-payment of annual fee