CN100536119C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN100536119C
CN100536119C CNB2006101418119A CN200610141811A CN100536119C CN 100536119 C CN100536119 C CN 100536119C CN B2006101418119 A CNB2006101418119 A CN B2006101418119A CN 200610141811 A CN200610141811 A CN 200610141811A CN 100536119 C CN100536119 C CN 100536119C
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China
Prior art keywords
pad
bump electrode
semiconductor
lead
film
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CNB2006101418119A
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English (en)
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CN1945817A (zh
Inventor
吉冈明彦
铃木进也
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株式会社瑞萨科技
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Priority to JP2005294902A priority Critical patent/JP4708148B2/ja
Priority to JP294902/2005 priority
Application filed by 株式会社瑞萨科技 filed Critical 株式会社瑞萨科技
Publication of CN1945817A publication Critical patent/CN1945817A/zh
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Publication of CN100536119C publication Critical patent/CN100536119C/zh

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    • HELECTRICITY
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
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Abstract

一种可以减小半导体芯片的尺寸的半导体器件制造技术。首先,在绝缘膜上方形成焊盘和其他导线。在包括焊盘和导线的绝缘膜上方形成表面保护膜,并且在表面保护膜中制作开口。该开口位于焊盘上方并露出该焊盘的表面。在包括开口的表面保护层上方形成凸点电极。在此,焊盘小于凸点电极。因此,在与焊盘的同一层中的凸点电极的正下方布置导线。换句话说,在由于焊盘足够小而变得可用的空间中布置导线。

Description

半导体器件及其制造方法

技术领域

本发明涉及一种半导体器件及其制造方法,并且更特别地涉及一种

对于在LCD (液晶显示器)驱动器中使用的半导体器件有用的技术。背景技术

曰本未审专利公开No.Hei 10(1998)-233507公开了一种技术,对于诸如具有多个输出焊盘的驱动器IC之类的半导体集成电路以及诸如电子时钟之类的电子电路设备,该技术能够减小芯片面积,并实现生产效率的提高和成本的降低。

具体地,输出焊盘放置在待与该输出焊盘连接的驱动晶体管上方,或者放置在逻辑电路上方,使得它们在平面上相互重叠。此外,不仅铝导线,而且凸点电极或阻挡金属也用于半导体器件的布线互连。同样,在半导体集成电路倒装地电键合在印刷电路板上方的情况下,通过将该

半导体集成电路的焊剂凸点与该印刷电路板的导线直接连接形成电连接。在这种情况下,凸点电极作为该半导体集成电路的外部连接端子叠置在晶体管上方。

例如,上述专利文献的图18示出,凸点输出焊盘位于驱动晶体管上方。因此,由于驱动晶体管与输出焊盘在平面上重叠,所以可减小芯片面积。此外,文献的图26示出, 一个扩散区以及另一个扩散区通过凸点互连电连接。与传统结构相比,该结构4吏得可以具有多个布线层。

发明内容

近年来,使用液晶作为显示设备的LCD已经得到迅速的推广。这些LCD由驱动它们的驱动器控制。LCD驱动器包括半导体芯片,其典型地安装在玻璃衬底上。构成LCD驱动器的该半导体芯片具有这样的结构:多个晶体管和多层互连形成于表面上具有凸点电极的半导体衬底上方。该芯片通过形成在表面上的凸点电极安装到玻璃衬底上方。在此,半导体芯片和玻璃衬底通过凸点电极连接。为了增大粘着力,扩大凸点电极面积以增大半导体芯片与玻璃衬底之间的接触面积。换句话说,构成LCD驱动器的半导体芯片的凸点电极远大于用于一般目的的半导体

芯片的凸点电极。

在LCD驱动器中,用作钝化膜的绝缘膜形成在凸点电极下方,并通过绝缘膜中的开口与形成于多层互连的顶层中的焊盘连接。通常,根据凸点电极的面积确定开口的面积和焊盘的面积,以使它们几乎相等。

如上所述,匹配较大凸点电极的焊盘形成于半导体芯片多层互连的顶层中。更具体地,具有几乎与凸点电极相同面积的焊盘形成于顶层中。这意味着为了留出用于在多层互连的顶层中形成不同于焊盘的互连导线的空间,半导体芯片的尺寸必须比较大。

另一个问题在于,在其中凸点电极形成于键合焊盘正上方的普通结构中,凸点电极的位置是固定的,存在关于诸如焊盘之类的布线单元的布局布置的限制。因此,4艮难采用允许有效地减小半导体芯片尺寸的布局布置。

本发明的一个目的是提供一种允许减小半导体芯片尺寸的技术。本发明的另一个目的是提供一种允许形成于半导体芯片中的互连

导线的布局布置的较大裕度的技术。

根据本说明书的以下详细描述以及附图,本发明的上述和其他目的

以及新颖特征将变得更加明显。

根据本发明的一个方面, 一种^导体器件^包:半导体芯片,该半导体芯片包括:(a)焊盘,其形成于半导体村底上方;(b)绝缘膜,其形成在该焊盘上方,并具有一个开口以露出该焊盘的表面,该开口的尺寸小于该焊盘的尺寸;以及(c)凸点电极,其形成于包括该开口的绝缘膜的上方并填充该开口。在此,焊盘的尺寸小于凸点电极的尺寸,并且与焊盘不相接的导线形成在凸点电极下方的绝缘膜中并形成在与焊盘相同的层中,、

根据本发明的另一个方面, 一种半导体器件的制造方法,包括以下步骤:(a )在半导体衬底上方的层中形成焊盘以及与焊盘不相接的导线;(b)在焊盘以及与焊盘不相接的导线上方形成绝缘膜;(c)在绝缘膜中制作开口以露出焊盘的表面,开口的尺寸小于焊盘的尺寸;以及(d)

在包括开口的绝缘膜上方形成凸点电极,凸点电极填充该开口,焊盘的尺寸小于凸点电极的尺寸,其中在凸点电极下方的绝缘膜中形成焊盘以及与焊盘不相接的导线。

根据本发明的又一个方面, 一种半导体器件,包括:(a)矩形形状的半导体衬底;(b)半导体元件,形成在半导体衬底的主表面上;(c)第一绝缘膜,形成在半导体衬底的主表面上方,以覆盖半导体元件;(d)多个焊盘,形成在第一绝缘膜上;(e)与多个焊盘不相接的布线层,形成在第 一绝缘膜上,布线层由多层互连结构中与多个焊盘相同层的布线层形成;(f)第二绝缘膜,形成为覆盖多个焊盘和布线层,第二绝缘膜在多个焊盘的上侧分别具有开口 ,每个开口的尺寸小于多个焊盘的每个焊盘的尺寸;以及(g)多个矩形形状的凸点电极,形成在第二绝缘膜上,多个凸点电极分别经由第二绝缘膜的开口电连接到多个焊盘;其中多个焊盘的每个焊盘的面积小于多个凸点电极的每个凸点电极的面积,其中多个凸点电极在第一方向上以预定间隔布置,第一方向沿着半导体衬底的长边,其中布置多个凸点电极的每个凸点电极,使得多个凸点电极的每个凸点电极的长边沿着半导体衬底的短边,以及其中布线层布置在多个凸点电极下方并且沿着第一方向延伸。

下面简要描述由本发明的优选实施例带来的效果。可以有效地使用凸点电极之下的空间并且可以减小半导体芯片的尺寸。可以与凸点电极的位置无关地布置焊盘,这允许包括焊盘的互连导线的布局布置的较大裕度。

附图说明

将参考附图更加具体地描述本发明,其中:

图1是根据本发明的第一实施例的半导体芯片的平面图;

图2是沿着图1中的线A-A,所取的截面图;

图3是沿着图1中的线B-B,所取的截面图;

图4是图1中的线C所指示的区域的放大平面图,其示出导线形成于线性布置的凸点电极的正下方;图5是图1中的线D所指示的区域的》丈大平面图,其示出导线形成于以Z字形图案布置的凸点电极的正下方;

图6是表示在根据笫一实施例的半导体器件制造工艺中的一个步骤的截面图;

图7是表示在半导体器件制造工艺中图6中的步骤之后的步骤的截面图;

图8是表示在半导体器件制造工艺中图7中的步骤之后的步骤的截面图;

图9是表示在半导体器件制造工艺中图8中的步骤之后的步骤的截面图;

图IO是表示在半导体器件制造工艺中图9中的步骤之后的步骤的截面图;

图ll是表示在半导体器件制造工艺中图IO中的步骤之后的步骤的截面图;

图12表示将半导体芯片安装在玻璃衬底上;

图13是安装在玻璃衬底上的半导体芯片的放大图;

图14表示LCD的一般结构;

图15表示另一类型LCD的一般结构;

图16表示如何将半导体芯片安装到TCP (带式载体封装)形式的封装衬底上;

图17表示以TCP形式封装的半导体芯片位于玻璃衬底与印刷电路板之间的例子;

图18表示如何将半导体芯片安装在COF (薄膜上芯片)形式的封装衬底上;

图19表示以COF形式封装的半导体芯片位于玻璃衬底与印刷电路板之间的例子;

图20是根据本发明的第二实施例的半导体芯片的局部平面图;图21是表示第二实施例的一种变体的平面图;以及图22是表示第二实施例的另一种变体的平面图。具体实施方式

以下将根据需要分别描述下述的优选实施例,但是除非另有说明,否则这些优选实施例并非是彼此不相关的。这些实施例在整体上或部分地是彼此的变体,并且有时一种描述是另 一种描述的具体形式或补充形式。

同样,在下述的优选实施例中,即使在元件的数值数据(件数、数值、数量、范围等)是用特定的数值数字来表示时,除非另有说明或者其在理论上限于该特定的数值数字,否则这些数值数据都不限于所表示

的特定数值数字;其可以大于或小于该特定的数值数字。

在下述的优选实施例中,无需赘言,除非另有说明或在理论上必要,否则其组成元件(包括组成步骤)并非是必需的。

同样地,在下述的优选实施例中,当对某些元件指示特定的形式或位置关系时,除非另有说明或者除非从理论的观点看只应当使用该特定的形式或位置关系,否则其都应当解释为包括与这些特定形式或位置关系等同或相似的形式或位置关系。对于上面提到的数值或范围,情况也是如此。

接下来,将参考附图详细地描述本发明的优选实施例。在用于说明优选实施例的所有图中,基本上用相同的参考标号表示具有相同功能的元件,并且省略其重复描述。

第一实施例

图l是表示根据第一实施例的半导体芯片1(半导体器件)的结构的平面图。根据第一实施例的半导体芯片1是用于LCD的驱动器。参考图1,半导体芯片l具有半导体衬底2,该衬底例如采取拉长的矩形的形状,并且例如,在其主表面上形成驱动液晶显示器的LCD驱动器。该驱动器具有通过给构成LCD的单元阵列中的每个像素提供电压而控制液晶分子的定向的功能,并且该驱动器包括栅极驱动电路3 、源极驱动电路4、液晶电路5、图形RAM (随机访问存储器)6以及外围电路

97。

在半导体芯片1的外围附近,沿着半导体芯片1的外围以规则的间

隔布置多个凸点电极8。这些凸点电极8位于半导体芯片1的元件和互连导线所处的有源区域上方。多个凸点电极8包括用于集成电路的凸点电极,其对于集成电路配置来说是必需的,还包括假电极(dummyelectrode),其对于集成电路配置来说不是必需的。凸点电极8在半导体芯片1的一个长边和两个短边的附近以Z字形图案布置。以Z字形图案布置的多个凸点电极8主要作为用于栅极输出信号或源极输出信号的凸点电极来4吏用。围绕半导体芯片1的长边的中心以Z字形图案布置的凸点电极8是用于源极输出信号的凸点电极,而沿着半导体芯片1的长边、在其角的附近以Z字形图案布置的那些凸点电极8以及沿着半导体芯片1的短边以Z字形图案布置的那些凸点电极8是用于栅极输出信号的凸点电极。这种Z字形图案使得可以布置很多对栅极输出信号和源极输出信号来说必需的凸点电极,同时又不需要增大半导体芯片l的尺寸。换句话说,可以减小芯片尺寸并且同时增大凸点电极的数目。

在半导体芯片1的另一个长边的附近,不是以Z字形图案而是线性地布置凸点电极8。线性布置的凸点电极8是用于数字输入信号或模拟输入信号的凸点电极。同样,假凸点电极围绕半导体芯片l的四个角布置。在图l所示的例子中,用于栅极输出信号或源极输出信号的凸点电极8以Z字形图案布置,并且用于数字输入信号或模拟输入信号的凸点电极8线性地布置。然而,还可以是用于栅极输出信号或源极输出信号的凸点电极8线性地布置,而用于数字输入信号或模拟输入信号的凸点电极8以Z字形图案布置。

图2是沿着图1中的线A-A,所取的截面图。在图2中,省略了顶层下方的层。尽管没有在图2中示出,但是在半导体衬底上方形成诸如MISFET (金属绝缘体半导体场效应晶体管)之类的半导体元件,并在该半导体元件上方制作多层互连。图2示出了在多层互连结构的顶层之上的多层互连。

如图2所示,在例如氧化硅的绝缘膜9上方制作顶层互连布线。该顶层互连布线包括例如焊盘IO和不同于焊盘10的导线lla和llb。导 线lla和llb例如是用于信号的信号线或用于电源的电源线或假导线。 焊盘10和导线lla、 lib例如包括铝膜。

在焊盘10和导线lla、 11b上方形成表面保护膜(钝化膜)12,使得 覆盖焊盘IO和导线lla、 llb。例如,表面保护膜12包括氮化硅的绝缘 膜。在表面保护膜12中制作开口 13以露出焊盘10的表面,并通过UBM 膜14作为内层(undercoat)金属膜,在包括开口 13的内部的表面保护 膜12上方形成凸点电极8。

在凸点电才及8下方是包括焊盘10和导线lla、 lib的布线层以及位 于该包括焊盘IO和导线1la、llb的布线层下方的多个其他的布线层(未 示出)。类似地,在凸点电极8下方形成诸如上述的MISFET之类的半 导体元件(未示出)。由此,本实施例橫:得可以通过有效地利用凸点电 极8下方的空间而减小半导体芯片l的芯片面积。

本发明的一个特点在于,开口 13和焊盘10小于凸点电极8。传统 地,在凸点电极8下方形成尺寸几乎等于凸点电极8的开口 13,并且在 开口 13下方形成大于凸点电极8的焊盘10。换句话说,在凸点电极8 下方形成焊盘10,并且焊盘10的尺寸与凸点电极8的尺寸几乎相同。 然而,在构成LCD驱动器的半导体芯片1中,应当扩大凸点电极8以 便确保其与玻璃衬底的粘着。因此,在凸点电极8下方的层中形成的焊 盘10应当较大。如果焊盘10太大,则很难在多层互连的顶层中给不同 于焊盘10的导线留下空间,并且因此,必须要增大半导体芯片1的尺 寸。另一方面,在这个第一实施例中,如图2所示,开口 13和焊盘10 小于凸点电极8。换言之,凸点电极8大于焊盘10。以这种方式,当焊 盘10小于凸点电极8时,在凸点电极8下方的层中为不同于焊盘10的 导线lla、 lib留下了空间。这可以如下文来进行。在传统的结构中, 由于焊盘10位于凸点电极8正下方的顶层中,所以不可能在同一顶层 中制作其他的导线。另一方面,在第一实施例中,由于焊盘10小于凸 点电极8,所以在焊盘10所处的同一顶层中凸点电极8的正下方留出可 用于其他导线lla、 llb的形成的空间。因此,除了焊盘10以外,可以在凸点电极8正下方形成导线lla和lib,使得可以有效地利用凸点电 极8正下方的空间,并可以减小半导体芯片1的尺寸。

第一实施例的特征在于,凸点电极8的尺寸保持不变,并且焊盘IO 小于凸点电极8,为不同于用于凸点电极8的焊盘IO的导线的形成留出 空间。总之,在凸点电极8粘着到玻璃衬底的面积足够大的同时,为不 同于焊盘10的导线留出空间以便可以减小半导体芯片1的尺寸。在前 面的"背景技术"中引用的专利文献中既没有描述也没有暗示该技术思 想,这是第一实施例所独有的。例如,可以通过增大凸点电极的尺寸而 不改变焊盘尺寸,制作大于焊盘的凸点电极;然而,在这种情况下,焊 盘本身的尺寸没有减小,并且不能获得由于减小焊盘尺寸而留出的空

间。因此,不能减小半导体芯片的尺寸。此外,较大的凸点电极导致较 大的半导体芯片,这意味着不可能减小半导体芯片的尺寸。如上所述, 有两种方法可以实现小于凸点电极的焊盘电极: 一种是增大凸点电极的 尺寸,另一种是减小焊盘的尺寸。这两种方法在焊盘电极小于凸点.电极 方面是相同的,但是减小焊盘尺寸的那种方法与另一种方法的明显不同 在于,在焊盘所处的同一层中在凸点电极下方为不同于焊盘的导线留出 空间。此外,由于焊盘本身的尺寸减小,因此焊盘宽度可以小于不同于 焊盘的相对宽的导线,诸如电源线。

图3是沿着图1的线B-B,所取的截面图。如图3所示,在沿着线 B-B,所取的截面中,在绝缘膜9上方形成焊盘10,并且形成表面保护膜 121吏得覆盖焊盘10。在表面保护膜12中制作开口 13,并在开口 13的 底部露出焊盘10的表面。在包括开口 13的内部的表面保护膜12上方 通过UBM膜14形成凸点电极8。在沿着线B-B,所取的截面的方向上, 焊盘10的宽度几乎等于或大于凸点电极8的宽度。换句话说,在沿着 图2中线A-A,所取的截面的方向上,焊盘10的宽度小于凸点电极8的 宽度,并且在凸点电极8的正下方形成焊盘10以及其他信号线和电源 线。另一方面,在沿着图3中的线B-B,所取的截面的方向上,在凸点电 极8的正下方形成的焊盘10的宽度几乎等于凸点电极8的宽度。

图4是图1中的区域C的放大平面图,表示导线形成在线性布置的

12凸点电极8的正下方。如图4所示,矩形凸点电极8沿着短边方向(垂 直于长边方向)并排排列。在凸点电才及8下方形成表面保护膜12,并且 在表面保护膜12中制作开口 13。在形成于表面保护膜12中的开口 l3 下方的层中形成焊盘10。焊盘10与部分地埋于开口中的凸点电极8电 连接。焊盘10是方形的,并且其一个边稍微长于凸点电极8的短边。 因此如图4所示,焊盘10的长度稍微大于凸点电极8的短边方向上的 凸点电极8的长度。另一方面,焊盘10的长度远远小于凸点电极8的 长边方向上的凸点电极8的长度。具体地,焊盘10小于凸点电极8,并 且焊盘10只位于凸点电极8的一端的下方。因此,在凸点电极8的长 边方向上,在焊盘10所处的同一布线层中留出空间。在该空间中形成 不同于焊盘10的导线lla-llc。才艮据第一实施例,如上所述,可以在 焊盘10所处的同一层中在凸点电极8的正下方形成导线lla-llc。由 于可以有效地使用矩形大凸点电极8正下方的空间,因此可以減小半导 体芯片的尺寸。

导线11a-llc是信号线、电源线或假导线,并且可以具有不同的 宽度。图4表示导线llc宽于导线lla和llb。传统地,焊盘尺寸与凸 点电极8的尺寸相似,并且焊盘宽度与其他导线相比相对较大。另一方 面,在本第一实施例中,焊盘10小于凸点电极8,并且在凸点电极8 的正下方留出可用于形成导线的空间。因此,焊盘10的宽度可能小于 例如在上述空间中形成的电源线的宽度。因此,根据笫一实施例,焊盘 10的宽度可以小于其它导线的宽度。

导线lla-llc沿着与凸点电极8的长边方向垂直的方向延伸。尽 管从有效利用空间的角度出发希望导线lla- 11c能够垂直于凸点电极8 的长边方向,但是它们并不一定要垂直于凸点电极8的长边方向。例如, 依赖于互连图案,导线可以与凸点电极8的长边倾斜地交叉。即使在这 种情况下,凸点电极8正下方的空间也是可用的,并且半导体芯片可以 更小。

图5是图1中的区域D的放大平面图,表示导线位于以Z字形图 案布置的凸点电极8的正下方。如图5所示,如图4中那样,在凸点电极8的长边方向上,凸点电极8的宽度远远大于焊盘10的宽度,并且 在焊盘10所处的同一层中在凸点电极8的长边方向上留出空间。在该 空间中形成导线lid-llk。当凸点电极8以Z字形图案布置时,它们形 成如图5所示的两行。因此,在凸点电极8的正下方留出的空间大于当 凸点电极8形成一行时的情况。这意味着如果形成与凸点电极8的尺寸 类似的焊盘,则将不可能在凸点电极8的正下方形成除了焊盘之外的其 他导线。在这种情况下,当凸点电极8以Z字形图案布置时(这意味着 它们布置成两行),可用于形成导线的空间将小于当凸点电极8布置成 一行时的情况。然而,如图5所示,在第一实施例中,在第一行中的凸 点电极8的正下方形成导线lid- llg,并且在第二行的凸点电极8的正 下方形成导线llh - 11k。因此,即使当凸点电极8以Z字形图案布置时, 也可以几乎与当凸点电极8布置成一行时一样有效地使用凸点电4及8正 下方的空间。关于半导体芯片的凸点电极8,不仅可以在布置成一行的 凸点电极8的下方,而且可以在布置成Z字形图案的凸点电才及8的下方 形成导线,并且由此可以减小半导体芯片的尺寸。

图1中的区域D (图5)中的凸点电才及8的凄t目大于图1的区3或C (图4)中的凸点电极8的数目。这是因为在图1的区域D中需要更多 的凸点电才及8,以4更驱动如图15所示的LCD屏幕区i或20(稍后将描述) 的元件。图1的区域D中的凸点电极8主要用于LCD屏幕区域20的元 件的栅极和源极。

接下来,将参考附图描述根据第 一 实施例的半导体器件的制造方 法。例如,在单晶硅的半导体衬底上方形成诸如MISFET之类的半导体 元件,并且在该半导体元件上方制作多层互连,尽管没有示出。图6表

例如,如图6所示,形成二氧化硅的绝缘膜9。可以使用CVD(化 学汽相淀积)工艺形成绝缘膜9。可以在绝缘膜9上方叠置钛或氮化钛 膜、铝膜和钛或氮化钛膜。然后,通过光刻或蚀刻在该叠置膜上进行构 图,并且通过该构图工艺形成焊盘10和导线lla、 llb。由此形成的焊 盘10小于通过稍后将描述的工艺形成的凸点电极。导线lla和Ub形成于凸点电极的正下方。

接下来,如图7所示,在其中形成焊盘IO和导线lla、 llb的绝缘 膜9上方形成表面保护膜12。表面保护膜12例如包括氮化石圭膜,并通 过CVD工艺制成。接下来,通过光刻或蚀刻在表面保护膜12中制作一 个开口 13。该开口 13位于焊盘10上方,并且使焊盘IO的表面露出。 开口 13应当小于焊盘10。

接下来,如图8所示,在包括开口 13的内部的表面保护膜12上方 形成UBM (凸点下金属:under bump metal)膜14。 UBM膜14通过溅 射制成,并且包括钬、镍、钇、钬鴒合金、氮化钛或金的单膜,或这些 材料的叠层膜。UBM膜14不仅具有改善凸点电极8与焊盘10和表面 保护膜12的粘着的功能,而且还具有可以抑制或防止由后续工艺制成 的导电膜16的金属元件向导线lla、 lib等的移动,或导线lla、 lib 等的金属元件向导电膜16的移动的阻挡功能。UBM膜14的平面图尺 寸大于开口13的尺寸,并且几乎等于导电膜16的尺寸。

接着,如图9所示,在UBM膜14上方涂覆光刻胶(resist)膜15 之后,通过对光刻胶膜15进行曝光和显影进行构图。以一种不会在凸 点电极形成区域中留下光刻胶膜15的方式来进行构图。然后,如图10 所示,例如,通过镀覆(plate)形成金膜作为导电膜16。然后,如图 11所示,通过去除构图光刻胶膜15以及被光刻胶膜15覆盖的UBM膜 14部分,可以形成包括导电膜16和UBM膜14的凸点电极8。接下来, 通过对半导体衬底进4亍划片来生产单独的半导体芯片。

根据笫一实施例,由于在凸点电极8的正下方形成的焊盘IO较小, 因jt匕可以在凸点电极8的下方形成导线lla和llb。可以在凸点电极8 的正下方的同一层中形成焊盘IO和导线lla、 llb,以便能够有效地使 用凸点电4及8正下方留出的空间,并减小半导体芯片的尺寸。

根据第一实施例的半导体器件制造方法与传统的半导体器件制造 方法相同,除了以一种在凸点电极8的正下方形成焊盘10以及应当与 焊盘iO位于同一层中的导线lla和lib的方式来进行构图。因此,制 造根据第一实施例的半导体器件不需要复杂的制造工艺。这意味着在不需要任何对制造工艺的重大改变的情况下可以获得有利的效果。

4妄下来,将如上所述地生产的半导体芯片4走合到封装衬底上。图12 表示在玻璃衬底17a上方安装半导体芯片1 (COG:玻璃上芯片)的情 况。如图12所示,在玻璃衬底17a上安装玻璃衬底17b,形成一个LCD 屏幕区域。将作为LCD驱动器的半导体芯片1安装到该LCD屏幕区域 的附近的玻璃衬底17a上。半导体芯片l具有凸点电极8,其中凸点电 极8通过各向异性导电膜19与玻璃衬底17a上形成的端子相连接。该 玻璃衬底17a和柔性印刷电路板18同样通过各向异性导电膜19而连接。 在以这种方式安装到玻璃衬底17a上的半导体芯片1中,用于输出的凸 点电4及8与LCD屏幕区域电连接,并且用于输入的凸点电极8与柔性 印刷电路板18相连接。

图13是安装到玻璃衬底17a上的半导体芯片1的》文大图。如图13 所示,端子20a位于玻璃衬底17a上方,并且半导体芯片1的凸点电极 8与端子20a电连接。在此,凸点电极8和端子20a不是直接连接,而 是通过各向异性导电膜19而连接。

图14表示LCD的一般结构。如图14所示,LCD屏幕区域20位于 玻璃衬底上方,并且图像显示在屏幕区域20上。将作为LCD驱动器的 半导体芯片1安装在屏幕区域20的附近的玻璃衬底上方。将柔性印刷 电路寺反18安装在半导体芯片1的附近,并且半导体芯片l作为驱动器 位于印刷电路板18与LCD屏幕区域20之间。半导体芯片l可以以这 种方式安装到玻璃衬底17a上方。

迄今为止,已经将LCD驱动器安装到封装衬底上的工艺作为COG 的一个例子进行了说明,其中将半导体芯片l安装到玻璃衬底17a上。 才矣下来,将说明封装半导体芯片1的其他形式的工艺。

封装)形式21和COF"(薄膜上芯片)形式22。图16示出了如7可将半 导体芯片1安装到TCP形式的封装衬底上。参考图16,封装衬底是带 状(带衬底)的薄膜衬底23,并且,例如,在薄膜衬底23上方形成铜 的引线24。将半导体芯片1安装到薄膜衬底23上方,使得凸点电极8粘附到引线24。用树脂25密封半导体芯片1。图17示出了以TCP形 式封装的半导体芯片1位于玻璃衬底17a与印刷电路板28之间的例子。 如图17所示,玻璃衬底17a通过各向异性导电膜26与形成于薄膜衬底 23上方的引线24连接,并且类似地,形成于薄膜衬底23上方的引线 24通过各向异性导电膜27与印刷电路板28相连接。

图18示出了如何以COF形式将半导体芯片1安装到封装村底上。 参考图18,封装衬底是带状的薄膜衬底29。如在TCP形式中那样,铜 的引线30位于薄膜衬底29上方,但是与TCP形式不同,将引线30固 定在薄膜衬底29上正好与凸点电极8相连接的区域。以一种使凸点电 极8粘附到引线30的方式将半导体芯片1安装到薄膜村底29上方。在 半导体芯片1与薄膜衬底29之间的间隙中有底层填料(underfill) 31。 图19示出了以COF形式将半导体芯片1安装到玻璃衬底17a与印刷电 路板28之间的例子。如图19所示,玻璃村底17a通过各向异性导电膜 26与形成于薄膜衬底29上方的引线30相连接,并且类似地,形成于薄 膜衬底29上方的引线30通过各向异性导电膜27与印刷电路板28相连 接。

可以以如上所述的各种形式来封装作为LCD驱动器的半导体芯片1。

第二实施例

第二实施例涉及具有宽布局裕度的半导体器件,其与凸点电极位置 无关地优化焊盘的位置。

图20是根据第二实施例的半导体芯片的局部平面图。参考图20, 焊盘IO通过形成在表面保护膜12中的开口 13与作为凸点电极8的一 部分的焊盘连接部分8a连接。凸点电极8包括:将与焊盘10连接的焊 盘连接部分8a;将与封装衬底的端子连接的端子连接部分8c;以及连 接焊盘连接部分8a与端子连接部分8c的布线部分8b。传统的凸点电极 只包括连接焊盘的端子连接部分。换句话说,在传统的凸点电极中,端 子连接部分还用作焊盘连接部分,这意味着焊盘连接部分与端子连接部分在平面上彼此重叠。另一方面,在根据第二实施例的凸点电极8中, 焊盘连接部分8a与端子连接部分8c形成于如平面图中所见的不同位 置,并且如平面图中所见的不同位置中的焊盘连接部分8a与端子连接 部分8c通过布线部分8b连接。焊盘连接部分8a和端子连接部分8c在 导线宽度上大于布线部分8b,如平面图中所见的那样。这是因为焊盘连 接部分8a和端子连接部分8c必须分别与玻璃衬底(或薄膜村底)上的 焊盘IO和引线连接,并且因此它们的平面表面必须足够大以确保连接。 由于布线部分8b的导线宽度相对较小,因此不太可能与其他的布线部 分8b接触,从而允许互连布线配置的较大裕度。

由于这样来构造每个凸点电才及8,因此焊盘10不以Z字形图案来 布置,而是在X方向上布置成一4亍,同时凸点电极8的端子连接部分 8c以Z字形图案布置。这意味着可以与凸点电极的位置无关地确定焊 盘的位置。传统地,凸点电极和焊盘在平面上相互重叠;并且当凸点电 极在Y方向上以Z字形图案布置时,焊盘也应当在Y方向上以Z字形 图案布置。在这种情况下,焊盘布置成两行,并且不同于焊盘的导线不 能位于焊盘所处的区域中。因此,在这种情况下,即使当焊盘形成得小 于凸点电极以便如上所述地根据第一实施例形成不同于焊盘的导线,也 不可能增大用于形成不同于焊盘的导线的空间,因为焊盘在Y方向上形 成为两行。另一方面,根据第二实施例,即使当凸点电极8以Z字形图 案布置时,焊盘IO也不必以Z字形图案布置,而可以如图20所示的那 样在X方向上布置成一行。因此,焊盘IO所占的空间比焊盘IO布置成 两行的时4荧要小。由于焊盘IO所占的空间较小,因此可以在焊盘10所 处的同一层中在凸点电极8下方留出足够的空间来形成不同于焊盘10 的导线lla-llk。因此,可以进一步减小半导体芯片的尺寸。形成于凸 点电极8正下方的导线11a- llk不一定是线性的;它们可以是折叠或 弯曲的。

如上所述,本发明的一个特点在于,凸点电极8包括焊盘连接部分 8a、布线部分8b以及端子连接部分8c,并且焊盘连接部分8a与端子连 接部分8c在平面上不重叠。焊盘连接部分8a、布线部分8b以及端子连

18接部分8c在同一层中。这使得可以在Y方向上延伸的凸点电极8以Z 字形图案布置,同时焊盘IO在X方向上布置成一行。由于作为凸点电 极8的一部分的端子连接部分8c键合到诸如玻璃衬底的封装衬底,因 此其宽度形成得大于布线部分8b的宽度以及焊盘连接部分8a的宽度, 以便确保所需的粘着力。可以如下来解释本实施例的凸点电极8包括焊 盘连接部分8a、布线部分8b和端子连接部分8c的这一特点:凸点电极 8包括较窄的布线部分(第一部分)8b以及宽于布线部分8b的端子连 接部分(第二部分)8c。这使得与封装衬底接触的面积可以足够大,并 且凸点电极8以较小的间隔以Z字形图案布置。换句话说,凸点电极8 的端子连接部分8c相对较宽,因为端子连接部分8c将要4建合到封装衬 底,而布线部分8b的宽度相对较小,因为布线部分8b只是用于连接焊 盘连接部分与端子连接部分,因此凸点电极8可以以较小的间隔以Z字 形图案布置。

根据第二实施例,可以与凸点电极位置无关地确定焊盘的位置,使 得有效地减小半导体芯片的尺寸。换句话说,由于允许焊盘配置的较大 裕度,因此可以有效地减小半导体芯片的尺寸。此外,由于可以与焊盘 10无关地增大凸点电极8的端子连接部分8c的面积,因此可以灵活地 改变与封装衬底的接触面积。

根据第二实施例的半导体器件的制造方法几乎与在第一实施例中 的相同。不同之处在于,凸点电极8包括焊盘连接部分8a、布线部分 8b以及端子连接部分8c,并且焊盘连接部分8a与端子连接部分8c在 平面上不重叠。此外,端子连接部分8c的宽度应当大于布线部分8b的 宽度。制造根据第二实施例的半导体器件时考虑了这些方面。

接下来,将说明第二实施例的一个变体。图21是第二实施例的一 个变体的平面图。图21示出了焊盘IO在X方向上布置成一行并且凸点 电才及8的端子连接部分8c在Y方向上布置成一行的情况。该变体也是 通过使用包括焊盘连接部分8a、布线部分8b和端子连接部分8c的凸点 电极8来实现的。例如,即使当凸点电极8的端子连接部分8c在Y方 向上布置成一行以便符合用户要求时,焊盘IO也可以在X方向上布置成一行。焊盘10的位置可以与形成端子连^l妄部分8c的位置无关地进行 确定。同样,尽管在图21中没有示出,但不同于焊盘10的导线形成于 焊盘10所处的同一层中的凸点电极8的正下方。因此,可以有效地利 用凸点电极8正下方的空间,使得减小半导体芯片的尺寸。此外,由于 这允许焊盘10的布局布置的较大裕度,因此可以通过优化焊盘10的位 置来进一步减小半导体芯片的尺寸。图21表示出凸点电极8的布线部 分8b弯曲成直角;然而,作为替代,它们也可以是成曲线的。

图22是表示笫二实施例的另一个变体的平面图。图22示出了焊盘 10在X方向上布置成一行并且凸点电极8的端子连接部分8c在Y方向 上以Z字形图案布置的情况。该变体也是通过使用包括焊盘连接部分 8a、布线部分8b以及端子连接部分8c的凸点电极8而实现的。例如, 即使当凸点电极8的端子连接部分8c在Y方向上以Z字形图案布置以 便符合用户要求时,焊盘10也可以在X方向上布置成一行。焊盘10 的位置可以与形成端子连接部分8c的位置无关地进行确定。同样,.尽 管在图22中没有示出,但不同于焊盘10的导线形成于焊盘IO所处的 同一层中的凸点电极8的正下方。因此,可以有效地利用凸点电极8正 下方的空间,使得减小半导体芯片的尺寸。此外,由于这允许焊盘10 的布局布置的较大裕度,因此可以通过优化焊盘10的位置来进一步减 小半导体芯片的尺寸。

迄今为止,已经参照本发明的实施例对本发明人做出的本发明进行 了详细的^兌明。然而,本发明不限于此,并JM艮明显,在不偏离本发明 的精神和范围的情况下,可以以各种方式对这些细节进行修改。

尽管在上述实施例中凸点电极8和焊盘IO都沿着半导体芯片的四 个边而定位,但是4艮明显本发明不限于这种情况。例如,焊盘10还可 以位于半导体芯片l的四个边的附近,而凸点电极8延伸到半导体芯片 1的中心。可选地,焊盘IO还可以位于半导体芯片1的中心,而凸点电 极8延伸到半导体芯片1的四个边。

在对上述实施例的描述中,假设了半导体器件用作LCD驱动器, 但是本发明并不限于这种情况,并且本发明可以适用于具有凸点电极的各种各样的半导体器件。

本发明可以广泛地用于半导体制造工业。

Claims (18)

1.一种半导体器件,包括半导体芯片,所述半导体芯片包括: (a)焊盘,其形成于半导体衬底上方; (b)绝缘膜,其形成在所述焊盘上方,并具有一个开口以露出所述焊盘的表面,所述开口的尺寸小于所述焊盘的尺寸;以及 (c)凸点电极,其形成在包括所述开口的所述绝缘膜的上方并填充所述开口, 其中所述焊盘的尺寸小于所述凸点电极的尺寸,并且 其中与所述焊盘不相接的导线形成在所述凸点电极下方的所述绝缘膜中并形成在与所述焊盘相同的层中。
2. 根据权利要求1所述的半导体器件,其中所述与所述焊盘不相接 的导线包括假导线。
3. 根据权利要求1所述的半导体器件,其中所述与所述焊盘不相接 的导线包括信号线或电源线。
4. 根据权利要求1所述的半导体器件,其中存在多条所述与所述焊 盘不相接的导线。
5. 根据权利要求1所述的半导体器件,其中所述凸点电极在指定的 方向上延伸。
6. 根据权利要求1所述的半导体器件,其中所述凸点电极以Z字 形图案布置。
7. 根据权利要求4所述的半导体器件,其中所述焊盘的宽度小于包 括在所述与所述焊盘不相接的导线中的给定导线的宽度。
8. —种半导体器件的制造方法,包括以下步骤:(a)在半导体衬底上方的层中形成焊盘以及与所述焊盘不相接的 导线; ":,曰"、、^ ;—:,:〜:、、,…、、,一膜;(c)在所述绝缘膜中制作开口以露出所述焊盘的表面,所述开口的尺寸小于所述焊盘的尺寸;以及(d)在包括所述开口的所述绝缘膜上方形成凸点电极,所述凸点 电极填充所述开口 ,所述焊盘的尺寸小于所述凸点电极的尺寸,其中在所述凸点电极下方的所述绝缘膜中形成所述焊盘以及所述 与所述焊盘不相接的导线。
9. 一种半导体器件,包括:(a) 矩形形状的半导体衬底;(b) 半导体元件,形成在所述半导体衬底的主表面上;覆盖所述半导体元件;(d) 多个焊盘,形成在所述第一绝缘膜上;(e) 与所述多个焊盘不相接的布线层,形成在所述第一绝缘膜上, 所述布线层由多层互连结构中与所述多个焊盘相同层的布线层形成;(f) 第二绝缘膜,形成为覆盖所述多个焊盘和所述布线层,所述 第二绝缘膜在所述多个焊盘的上侧分别具有开口,每个所述开口的尺寸 小于所述多个焊盘的每个焊盘的尺寸;以及(g) 多个矩形形状的凸点电极,形成在所述第二绝缘膜上,所述 多个凸点电极分别经由所述第二绝缘膜的所述开口电连接到所述多个 焊盘;其中所述多个焊盘的每个焊盘的面积小于所述多个凸点电极的每 个凸点电纟及的面积,其中所述多个凸点电极在第一方向上以预定间隔布置,所述第一方 向沿着所述半导体衬底的长边,其中布置所述多个凸点电极的每个凸点电极,使得所述多个凸点电 极的每个凸点电极的长边沿着所述半导体衬底的短边,以及其中所述布线层布置在所述多个凸点电极下方并且沿着所述第一 方向延伸。
10. 根据权利要求9所述的半导体器件,其中所述布线层是电源线。
11. 根据权利要求9所述的半导体器件,其中所述布线层布置成在多个凸点电极重叠,并且与所述多个凸点电极的每个凸点 电极的所述长边交叉。
12.根据权利要求9所述的半导体器件,其中在所述第二绝缘膜与 所述多个凸点电极的每个凸点电极之间形成金属膜,作为用于所述多个 凸点电极的内层金属膜。
13. 根据权利要求12所述的半导体器件,其中所述第二绝缘膜是 氮化硅膜。
14. 根据权利要求]3所述的半导体器件,其中所述第一绝缘膜是 氧化硅膜。
15. 根据权利要求12所述的半导体器件,其中所述多个凸点电极 的每个凸点电极由金膜形成。
16. 根据权利要求11所述的半导体器件,其中所述布线层和所述 多个焊盘二者都包括铝膜,并且其中所述布线层的所述铝膜由与所述多 个焊盘的所述铝膜相同的步骤形成。
17. 根据权利要求16所述的半导体器件,其中所述布线层和所述 多个焊盘中的每一个在所述铝膜的上表面和下表面上还包括钛膜或氮 化钛膜。
18. 根据权利要求9所述的半导体器件,其中所述多个凸点电极的 连接。
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