CN1779958A - 复晶球阵列封装的结构 - Google Patents

复晶球阵列封装的结构 Download PDF

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Publication number
CN1779958A
CN1779958A CNA2005100042255A CN200510004225A CN1779958A CN 1779958 A CN1779958 A CN 1779958A CN A2005100042255 A CNA2005100042255 A CN A2005100042255A CN 200510004225 A CN200510004225 A CN 200510004225A CN 1779958 A CN1779958 A CN 1779958A
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China
Prior art keywords
encapsulation
conductive layer
fcbga
dielectric layer
elastomeric dielectric
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CNA2005100042255A
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English (en)
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杨文焜
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Priority claimed from US10/997,343 external-priority patent/US20050242427A1/en
Application filed by Yupei Science & Technology Co Ltd filed Critical Yupei Science & Technology Co Ltd
Publication of CN1779958A publication Critical patent/CN1779958A/zh
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本发明揭露一种复晶球阵列封装的结构。上述复晶球阵列封装结构包含一具有复数个焊锡凸块(solder bumps)的复晶焊锡凸块(flip chipsolder bumping)结构。一基底具有复数个导线与上述复数个焊锡凸块电性耦合。一印刷电路板具有复数个焊锡球(solder balls)与上述复数个导线电性耦合。

Description

复晶球阵列封装的结构
技术领域
本发明与一种晶圆封装有关，特别是有关于一种复晶球阵列(FlipChip Ball Grid Array：FCBGA)封装的结构，上述封装结构可以避免焊锡球与印刷电路板结合后，因为温度变化产生位移拉力加大造成焊锡球龟裂而开路(open)的情形。
先前技术
早期的导线架封装技术已经不适合端点(terminals)密度过高的更进步的半导体晶粒。因此，一新的球阵列(Ball Grid Array：BGA)封装技术已经发展以满足上述更进步的半导体晶粒的封装需求。上述球阵列封装具有一个好处，也就是它的球形端点(terminals)具有比上述导线架封装来得小的间距(pitch)，并且上述端点(terminals)不容易损害与变形。此外，较短的信号传递距离可以有益于提升操作频率以符合更快效率的需求。大部分的封装技术都是先将一晶圆上的晶粒分离成为个别的晶粒，然后再在封装与测试上述个别的晶粒。另外，一种称为晶圆型态封装(wafer level package：WLP)的封装技术可以在分离个别的晶粒的前就封装上述晶圆上的晶粒。上述晶圆型态封装(wafer levelpackage：WLP)具有一些好处，例如：一个较短的生产周期(cycle time)、较低的价格以及不需要填充物(under-fill)或铸模(molding)。
此外，目前市场上所使用的封装(package)部分结构如图1所示。其中包含一绝缘层103与一集成电路元件100的保护层(passivation)102，上述绝缘层103的材质可以为厚度5微米(micron)的BCB、聚乙醯(polyimides)等介电材质，而保护层102的材质可以为聚乙醯(polyimides)或氮化硅(SiN)。重布导电层(RDL：redistribution layer)104与上述绝缘层103、集成电路元件的铝垫(Al pads)101结合，上述重布导电层104的材质可以为厚度15微米(micron)的铜镍金(Cu/Ni/Au)合金。此外，绝缘层105复盖上述导电层104，且上述绝缘层105中具有复数个开口，每一该开口上具有一焊锡球(solder ball)106以利于与一印刷电路板(PCB)或外部装置电性连接。上述绝缘层105的材质可以为BCB、环氧化物(Epoxy)、树脂(Resin)或聚乙醯(polyimides)等介电材质。
上面所述的传统的封装结构通常使用最外层材料来加强固定焊锡球106。其缺点包含：上述导电层104与绝缘层103的结合强度太强而导致负面效应。当焊锡球106与印刷电路板结合后因温度变化而产生拉力时，在受力区107于上述焊锡球106与导电层104的接合处将因为温度变化产生位移拉力加大，结果造成焊锡球106与焊垫(pad)之间龟裂而形成开路(open circuit)的情况。
有监于此，本发明提出一改良性封装的结构以改善以上的缺点。
发明内容
本发明的目的在于提供一种复晶球阵列(Flip Chip Ball GridArray：FCBGA)封装的结构。本发明的封装结构可以避免焊锡球与印刷电路板结合后，因为温度变化产生位移拉力加大(enforcing stress)而造成焊锡球龟裂导致开路(open circuit)的情形。
本发明揭露一种复晶球阵列封装的结构，其特征在于，包含：
一基底，具有复数个导线；
复数个焊锡凸块，电性耦合该复数个导线；
一图案化第一弹性介电层，复盖晶片上的保护层的部分区域；
一导电层，形成于该图案化第一弹性介电层之上，基于该图案化第一弹性介电层的图案而产生曲折的导电层图案，其中该曲折导电层图案是部分附著于该保护层之上与部分附著于该图案化第一弹性介电层之上；以及
一第二弹性介电层，复盖该导电层，该第二弹性介电层具有复数个开口，每一该开口上具有该复数个焊锡凸块的一以利于与该复数个导线之一耦合。
其中还包含一印刷电路版，具有复数个焊锡球电性耦接该复数个导线。
其中还包含一填充物质形成于该复数个焊锡凸块之间。
其中当该焊锡凸块置于该基底之上时，该封装结构的固定区中的该导电层不会直接受力到该晶片的焊垫上，该曲折的导电层图案作为该封装结构的缓冲物以用来吸收拉力。
其中还包含一图案化的第三绝缘层形成于该图案化第一弹性介电层与该导电层之间。
其中该第三绝缘层的材质为BCB、硅胶、环氧化物、聚乙醯或树脂。
其中该第一弹性介电层的材质为BCB、硅胶、环氧化物、聚乙醯或树脂。
其中该保护层的材质为聚乙醯。
其中该导电层的材质为一金属合金。
其中该金属合金为钛铜合金或铜镍金合金；该钛铜合金是利用溅镀方式形成，而该铜镍金合金是利用电镀方式形成。
其中该钛铜合金是利用溅镀方式形成。
其中该铜镍金合金是利用电镀方式形成。
其中该金属合金的厚度为10微米到20微米之间。
其中该焊垫的材质为铝或铜。
其中该第二弹性介电层的材质为BCB、硅胶、环氧化物、聚乙醯或树脂。
其中该曲折的导电层图案是从该焊垫延伸至该焊锡凸块下的焊锡垫，并且一线段与一径向方向之间的夹角是大于450度，其中该线段是从该晶片中心至该焊锡凸块中心，而该径向方向是从该焊锡凸块中心至该曲折的导电层图案离开该焊锡凸块的方向。
由于该第一与第二弹性介电层本身的功效与该第一、第二弹性介电层与该导电层之间较差的附著力，当该基底的热膨胀比该晶片的热膨胀还高时，该焊锡凸块被提起而不会裂开。
本发明一种封装的导电凸块的配置，其特征在于，包含：
复数个焊垫，形成于一晶粒之上；以及
复数个金属凸块，形成于该晶粒之上并且由导线而连接该复数个焊垫；
其中一线段与一径向方向之间的夹角是大于450度，该线段是从该晶粒中心至该金属凸块中心，而该径向方向是从该金属凸块中心至该导线离开该金属凸块的方向。
其中该导线是从该焊垫延伸至该金属凸块下的垫。
附图说明
由以下详细的描述结合附图所示，将可轻易的了解上述内容及此项创作的诸多优点，其中：
图1为传统的晶圆型态封装结构的示意图。
图2为根据本发明的一封装结构的示意图。
图3为根据本发明的一晶圆型态封装结构的一晶片的导电层图案与焊锡凸块(solder bumps)之上视图。
图4为根据本发明的一复晶球阵列封装结构的示意图。
图5为根据本发明的一复晶球阵列封装结构的示意图。
实施方法：
本发明揭露一种封装的后段(backend)结构。本发明详细说明如下，所述的较佳实施例只做一说明非用以限定本发明。本发明揭露一种复晶球阵列封装结构，一图案化弹性介电层复盖一底层的部分区域，一导电层形成于上述图案化弹性介电层之上，结果基于上述图案化弹性介电层的图案而产生曲折的导电层图案以用来吸收拉力。上述弹性介电层的材料包括BCB、硅胶(SINR)、环氧化物(Epoxy)、聚乙醯(polyimides)或树脂(Resin)。上述导电层的材质为一金属合金。
请参阅图2，其为本发明的结构示意图。其中以一封装做一说明，非用以限定本发明。本发明包含一图案化弹性介电层203复盖一元件200的保护层(passivation layer)202的部分区域，上述弹性介电层203的材质可以为介电材质所形成，例如：BCB、硅胶(SINR)、环氧化物(Epoxy)、聚乙醯(polyimides)或树脂(Resin)等介电材质。上述图案化弹性介电层203具有复数个开孔以曝露底层的保护层(passivation)202。上述图案化弹性介电层203及保护层202区域所形成的受力区207将遭受(suffer)外力的影响，如图2所示区域。而上述保护层(passivation layer)202的材质可以包含聚乙醯(polyimides)以及氮化硅材质。
重布导电层(RDL：redistribution layer)204形成于图案化弹性介电层203之上，基于上述图案化弹性介电层203而产生至少一曲折或弯曲的导电层图案。在一实施例中，上述导电层204的材质可以为导电材质所形成，例如可以为厚度15微米(micron)的钛铜(Ti/Cu)合金或铜镍金(Cu/Ni/Au)合金。上述钛铜(Ti/Cu)合金可以利用溅镀方式形成，而铜镍金(Cu/Ni/Au)合金则可以利用电镀方式形成。焊垫201的材质可以为导电材质所形成，例如铝(Al)或铜(Cu)。
另外，一图案化弹性介电层205形成于导电层204之上，上述图案化弹性介电层205具有复数个开口，其中每一开口上具有一接触金属球206以利于与一印刷电路板(PCB)或外部装置(未图示)电性连接。上述接触金属球206可以为导电球，例如为焊锡球(solder ball)206。上述图案化弹性介电层205的材质可以为BCB、硅胶(SINR)、环氧化物(Epoxy)、聚乙醯(polyimides)或树脂(Resin)等介电材质。
由本发明所揭露的设计，因为上述保护层202紧紧抓住(catches)导电层204，所以邻接上述封装结构的固定区域210中的导电层204不会直接受力到上述集成电路元件200内连线(inter-connector)的焊垫201之上。当焊锡球206附著到印刷电路板时可能引发热应力(termal stress)，但是由于上述导电层204直接邻接保护层202因此温度的影响将被降低。
另外，在上述封装结构的缓冲区209中，上述导电层204部分附著于保护层202之上与部分附著于弹性介电层203之上，使得上述导电层204形成弯曲的图案。由于上述导电层的图案以及弯曲的结构，使得上述导电层可以作为一缓冲物以释放(release)热应力，结果由温度变化所产生的应力将被分散掉。因为上述导电层204与弹性介电层203之间的结合度不佳，当受到外力作用时，导电层204会从弹性介电层203的表面轻微的剥离(peel)。由于具有曲折设计的弯曲导电层图案，使得上述导电层的延展性(extension)增加，结果透过轻微的剥离(peel)可以吸收上述热应力。因此，上述结构可以延长其使用寿命(life cycle)，尤其是对于远离焊垫的焊锡球206而言。
再者，上述导电层204的曲折结构是从上述焊垫(bonding pad)201延伸至焊锡球206下的焊锡垫。举一实施例而言，在本结构中，一线段与一径向方向(radius orientation)之间的夹角ψ是大于450(度)，上述线段是从上述晶片中心C1至焊锡球206中心C2，而上述径向方向是从焊锡球206中心C2至上述曲折结构的导电层204离开焊锡球206的方向，如图3所示。由于上述第一与第二弹性介电层203、205本身的功效(performance)以及第一、第二弹性介电层203、205与导电层204之间较差的附著力，当基底(substrate)的热膨胀比上述复晶的热膨胀还高时，上述焊锡球206可以被提起(lifted)而不会裂开(broken)。因此，由上述焊锡球206开始之上述导线所延伸的角度与其配置的形状，上述填充物质(under-fill material)可以被省略。因此，由上述设计可以节省成本以及简化制程。举例而言，图3中显示了上述焊锡球之上视图。上述焊垫(bonding pad)延伸至焊锡垫(solder pad)的焊锡球A13，在X/Y方向(纸面)的导线已经被修正，一但基底(substrate)的热膨胀比上述复晶的热膨胀还高时，由于上述弹性介电层材料的弹性与高延展性的功效(performance)以及金属与硅胶(SINR)之间较差的附著力，使得上述焊锡球A13可以被提起(lifted)而不会于接合处裂开(broken)。
本发明亦包含一图案化的弹性介电层208形成于弹性介电层203与导电层204之间，以增加上述焊锡球的下的导电层的曲折程度(也就是增加上述曲折形状的数量)。上述弹性介电层208的材质可以为BCB、硅胶(SINR)、环氧化物(Epoxy)、聚乙醯(polyimides)或树脂(Resin)等介电材质。
如图4所示，其为根据本发明的一复晶球阵列封装结构的示意图。上述的复晶球阵列封装结构与图2的封装结构相同。一填充物质(under-fill material)404是形成以填满晶片400上的复数个焊锡凸块402之间。重布导电层(RDL：redistribution layer)401是为一具有弯曲或曲折的导电层图案以与上述焊锡凸块402电性耦合。一弹性介电层403是形成以隔绝上述重布导电层(RDL：redistribution layer)401。一基底405的导线408与接触垫407是形成以分别电性耦合上述焊锡凸块402与焊锡球406。此外，形成于上述基底405上的焊锡球406可以电性耦接一印刷电路板或外部装置。
如图5所示，其为根据本发明的一复晶球阵列封装结构的示意图。上述的复晶球阵列封装结构与图2的封装结构相同。在本实施例中，上述填充物质(under-fill material)被省略，也就是说，其不需填满晶片500上的复数个焊锡凸块502之间。重布导电层(RDL：redistribution layer)501是为一具有弯曲或曲折的导电层图案以与上述焊锡凸块502电性耦合。一基底503的接触(contacts)504、505是形成以分别电性耦合上述焊锡凸块502与焊锡球506。此外，形成于上述基底503上的焊锡球506可以透过焊锡球506耦接接触508而电性耦接一印刷电路板(PCB)507。
因此，根据本发明，上述封装的结构的主要优点如下：本发明的复晶球阵列(Flip Chip Ball Grid Array：FCBGA)封装结构可以避免焊锡球与印刷电路板结合后，因为温度变化产生位移拉力加大造成焊锡球龟裂而开路(open circuit)的情形；此外，不需另外使用额外的材料来加强固定焊锡球。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张的专利权利范围。其专利保护范围当视后附的申请专利范围及其等同领域而定。凡熟悉此领域技术的人士，在不脱离本专利精神或范围内，所作的更动或润饰，均属于本发明所揭示精神下所完成的等效改变或设计，且应包含在下述的申请专利范围内。

Claims (19)

1.一种复晶球阵列封装的结构，其特征在于，包含：
一基底，具有复数个导线；
复数个焊锡凸块，电性耦合该复数个导线；
一图案化第一弹性介电层，复盖晶片上的保护层的部分区域；
一导电层，形成于该图案化第一弹性介电层之上，基于该图案化第一弹性介电层的图案而产生曲折的导电层图案，其中该曲折导电层图案是部分附著于该保护层之上与部分附著于该图案化第一弹性介电层之上；以及
一第二弹性介电层，复盖该导电层，该第二弹性介电层具有复数个开口，每一该开口上具有该复数个焊锡凸块的一以利于与该复数个导线之一耦合。
2.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中还包含一印刷电路版，具有复数个焊锡球电性耦接该复数个导线。
3.如权利要求2所述的复晶球阵列封装的结构，其特征在于，其中还包含一填充物质形成于该复数个焊锡凸块之间。
4.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中当该焊锡凸块置于该基底之上时，该封装结构的固定区中的该导电层不会直接受力到该晶片的焊垫上，该曲折的导电层图案作为该封装结构的缓冲物以用来吸收拉力。
5.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中还包含一图案化的第三绝缘层形成于该图案化第一弹性介电层与该导电层之间。
6.如权利要求5所述的复晶球阵列封装的结构，其特征在于，其中该第三绝缘层的材质为BCB、硅胶、环氧化物、聚乙醯或树脂。
7.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中该第一弹性介电层的材质为BCB、硅胶、环氧化物、聚乙醯或树脂。
8.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中该保护层的材质为聚乙醯。
9.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中该导电层的材质为一金属合金。
10.如权利要求9所述的复晶球阵列封装的结构，其特征在于，其中该金属合金为钛铜合金或铜镍金合金；该钛铜合金是利用溅镀方式形成，而该铜镍金合金是利用电镀方式形成。
11.如权利要求10所述的复晶球阵列封装的结构，其特征在于，其中该钛铜合金是利用溅镀方式形成。
12.如权利要求10所述的复晶球阵列封装的结构，其特征在于，其中该铜镍金合金是利用电镀方式形成。
13.如权利要求10所述的复晶球阵列封装的结构，其特征在于，其中该金属合金的厚度为10微米到20微米之间。
14.如权利要求4所述的复晶球阵列封装的结构，其特征在于，其中该焊垫的材质为铝或铜。
15.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中该第二弹性介电层的材质为BCB、硅胶、环氧化物、聚乙醯或树脂。
16.如权利要求1所述的复晶球阵列封装的结构，其特征在于，其中该曲折的导电层图案是从该焊垫延伸至该焊锡凸块下的焊锡垫，并且一线段与一径向方向之间的夹角是大于450度，其中该线段是从该晶片中心至该焊锡凸块中心，而该径向方向是从该焊锡凸块中心至该曲折的导电层图案离开该焊锡凸块的方向。
17.如权利要求16所述的复晶球阵列封装的结构，其特征在于，由于该第一与第二弹性介电层本身的功效与该第一、第二弹性介电层与该导电层之间较差的附著力，当该基底的热膨胀比该晶片的热膨胀还高时，该焊锡凸块被提起而不会裂开。
18.一种封装的导电凸块的配置，其特征在于，包含：
复数个焊垫，形成于一晶粒之上；以及
复数个金属凸块，形成于该晶粒之上并且由导线而连接该复数个焊垫；
其中一线段与一径向方向之间的夹角是大于450度，该线段是从该晶粒中心至该金属凸块中心，而该径向方向是从该金属凸块中心至该导线离开该金属凸块的方向。
19.如权利要求18的封装的导电凸块的配置，其特征在于，其中该导线是从该焊垫延伸至该金属凸块下的垫。
CNA2005100042255A 2004-11-24 2005-01-07 复晶球阵列封装的结构 Pending CN1779958A (zh)

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KR100752665B1 (ko) * 2006-06-23 2007-08-29 삼성전자주식회사 도전성 접착층을 이용한 반도체 소자 및 그 제조 방법
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TWI392068B (zh) * 2008-11-11 2013-04-01 Unimicron Technology Corp 封裝基板及其製法
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Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5203076A (en) * 1991-12-23 1993-04-20 Motorola, Inc. Vacuum infiltration of underfill material for flip-chip devices
US5391397A (en) * 1994-04-05 1995-02-21 Motorola, Inc. Method of adhesion to a polyimide surface by formation of covalent bonds
JP2773660B2 (ja) 1994-10-27 1998-07-09 日本電気株式会社 半導体装置
TW571373B (en) * 1996-12-04 2004-01-11 Seiko Epson Corp Semiconductor device, circuit substrate, and electronic machine
KR20010031602A (ko) * 1997-10-30 2001-04-16 가나이 쓰토무 반도체 장치 및 그 제조 방법
US6333565B1 (en) * 1998-03-23 2001-12-25 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US6539624B1 (en) * 1999-03-27 2003-04-01 Industrial Technology Research Institute Method for forming wafer level package
JP2001024085A (ja) * 1999-07-12 2001-01-26 Nec Corp 半導体装置
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
US6528349B1 (en) * 1999-10-26 2003-03-04 Georgia Tech Research Corporation Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability
JP3596864B2 (ja) * 2000-05-25 2004-12-02 シャープ株式会社 半導体装置
JP4068801B2 (ja) * 2000-11-30 2008-03-26 株式会社ルネサステクノロジ 半導体装置
JP2004104103A (ja) * 2002-08-21 2004-04-02 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004140116A (ja) * 2002-10-16 2004-05-13 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US7259468B2 (en) * 2004-04-30 2007-08-21 Advanced Chip Engineering Technology Inc. Structure of package

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