SG142144A1 - Fcbga package structure - Google Patents

Fcbga package structure

Info

Publication number
SG142144A1
SG142144A1 SG200407707-9A SG2004077079A SG142144A1 SG 142144 A1 SG142144 A1 SG 142144A1 SG 2004077079 A SG2004077079 A SG 2004077079A SG 142144 A1 SG142144 A1 SG 142144A1
Authority
SG
Singapore
Prior art keywords
package structure
solder
fcbga package
conductive lines
electrically coupling
Prior art date
Application number
SG200407707-9A
Inventor
Wen Kun Yang
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/997,343 external-priority patent/US20050242427A1/en
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of SG142144A1 publication Critical patent/SG142144A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

FCBGA Package Structure The present invention discloses a structure of package. The structure comprises a flip chip solder bumping structure having a plurality of solder bumps. A substrate has a plurality of conductive lines electrically coupling with the plurality of solder bumps. A print circuit board has a plurality of solder balls electrically coupling with the plurality of conductive lines.
SG200407707-9A 2004-11-24 2004-12-15 Fcbga package structure SG142144A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/997,343 US20050242427A1 (en) 2004-04-30 2004-11-24 FCBGA package structure

Publications (1)

Publication Number Publication Date
SG142144A1 true SG142144A1 (en) 2008-05-28

Family

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KR100901241B1 (en) * 2007-06-11 2009-06-08 주식회사 네패스 Semiconductor device with sacrificial layer and fabricating method thereof
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KR101111429B1 (en) * 2010-04-26 2012-02-16 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same

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