TWI392068B - Package substrate and fabrication method thereof - Google Patents

Description

Package substrate and its preparation method

The present invention relates to a package substrate and a method for fabricating the same, and more particularly to a package substrate for improving electrical connection quality and a method for fabricating the same.

At present, the Flip Chip packaging technology in the semiconductor packaging technology is directly electrically connected to the electrode pads on the active surface of the semiconductor wafer on the electrical contact pads of the package substrate, and between the semiconductor wafer and the package substrate. An underfill material can be used to ensure the reliability of bonding between the semiconductor wafer and the package substrate; and in order to effectively place the semiconductor wafer on the package substrate, it is usually formed on the electrical contact pads of the package substrate. Solder bumps are then soldered, and the electrical contact pads are formed by solder bumps to form contacts with the electrode pads of the semiconductor wafer.

1A to 1C are schematic views showing a conventional package substrate; as shown in FIG. 1A, a board body 10 having inner layer lines 101, 102 is provided, and the inner layer lines 101, 102 have a plurality of electrical connection pads. (Land) 101a, 101b, a dielectric layer 11, 12 is formed on the surface of the board 10, and circuit layers 14, 15 are formed on the dielectric layers 11, 12, and the circuit layers 14, 15 are formed. The conductive vias 141, 151 in the dielectric layers 11, 12 are electrically connected to the electrical connection pads 101a, 101b of the inner layer lines 101, 102. The electrical connection pads 101a can be disposed on the board body 10 by a plurality. The conductive via or the conductive via (not shown) is electrically connected to the electrical connection pad 101b on the other side of the board 10, and the circuit layer 14, 15 having a plurality of lines 142, 152 on the dielectric layers 11, 12, and a plurality of electrical contact pads 143, 153; as shown in Figure 1B, formed on the dielectric layers 11, 12 and the circuit layers 14, 15, The solder resist layers 17, 18, and the plurality of openings 170, 180 are formed in the solder resist layers 17, 18 to correspondingly expose the respective electrical contact pads 143, 153; as shown in FIG. 1C, formed on each of the electrical contact pads 143 Solder bumps 19 are electrically connected to a semiconductor wafer (not shown).

However, as shown in FIG. 1C', the electrical contact pad 143 of the conventional package substrate forms a corner of approximately ninety degrees with the opening 170, so that the solder bump 19 is not easily filled in the corner, so that the solder A hole a is formed between the bump 19 and the solder resist layer 17, which causes a problem of peeling off the solder bump of the subsequent process; further, since the solder bump 19 fails to fill the opening 170, the solder bump 19 and the solder bump 19 The contact area of the electrical contact pads 143 is reduced, which affects the electrical connection quality of the package structure.

Therefore, in view of the above problems, how to avoid the problem of voids between the solder bumps and the solder resist layer in the prior art, and to improve the electrical connection quality of the package substrate has become a problem to be solved at present.

In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a package substrate for improving electrical connection quality and a method of manufacturing the same.

To achieve the above and other objects, the present invention discloses a package substrate comprising: a plate body having opposite first and second surfaces; and first and second dielectric layers respectively disposed on the plate body On the first and second surfaces; the first and second circuit layers are respectively embedded and exposed to the first and second dielectric layers And a plurality of first and second electrical contact pads respectively disposed on the surface of the layer; and a plurality of metal bumps disposed on each of the first electrical contact pads.

According to the above structure, the foregoing plate body may be a ceramic plate, a metal plate, or an organic plate, or the plate body is a core plate having a line on the surface, a multi-layer plate having a core, a single-layer plate without a core, or a coreless layer. And the first and second circuit layers respectively have first and second conductive blind holes for electrically connecting to the circuit.

According to the above structure, the metal bumps may be copper, and the metal bumps have a surface treatment layer, and the surface treatment layer may be tin (Sn), lead (Pb), silver (Ag), copper ( It is made of one of the group of Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd) and gold (Au).

In addition, the package substrate may include first and second solder resist layers respectively disposed on the first and second dielectric layers, and having a plurality of first and second openings to correspondingly expose the metal a bump and the second electrical contact pad; the first solder resist layer may be slightly lower, slightly higher or slightly flush with each of the metal bumps, and the first opening may be greater than or equal to each of the metal bumps Piece.

The invention provides a method for manufacturing a package substrate, comprising: providing a plate body having opposite first and second surfaces; forming first and second dielectrics on the first and second surfaces of the plate body, respectively Forming a plurality of first and second slots on the surface of the first and second dielectric layers; forming a conductive layer on the surfaces of the first and second trenches and the first and second dielectric layers Forming a metal layer on the conductive layer to form first and second circuit layers in each of the first and second trenches, and the first and second circuit layers have a plurality of first and second electrical properties Contact pad; and removing part of the metal layer and covering it And a conductive layer for forming metal bumps on the first electrical contact pads and exposing the first and second circuit layers.

In the foregoing method, the plate body may be a ceramic plate, a metal plate, or an organic plate; or the plate body may be a core plate having a line on the surface, a multi-layer plate having a core, a single-layer plate without a core, or a coreless The multilayer board, and the first and second circuit layers respectively have first and second conductive blind holes for electrically connecting to the circuit.

According to the above method, the first and second conductive blind vias are formed by forming a plurality of first and second blind vias on the first and second dielectric layers, and correspondingly exposing portions of the traces to serve as The first and second electrical connection pads, and the first and second slotted portions respectively connect the first and second blind holes; on the first and second dielectric layers, each of the first and second Forming the conductive layer on the sidewalls of the second blind via, the sidewalls of the first and second trenches, and the first and second electrical connection pads; and forming the metal layer on the conductive layer for each Forming first and second conductive blind holes in the first and second blind holes, and electrically connecting the first and second circuit layers to the first and second electrical connection pads; wherein the blind holes and the slots It can be formed by laser.

In the above method, the metal layer and the metal bumps may be copper, and the metal bumps may be formed with a surface treatment layer, and the surface treatment layer may be tin (Sn) or lead (Pb). One of a group of silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), and gold (Au).

In addition, the foregoing method may include forming first and second solder resist layers on the surfaces of the first and second dielectric layers and the first and second circuit layers, and the first and second solder resist layers Forming a plurality of first and second openings to respectively Correspondingly exposing each of the metal bumps and the second electrical contact pads; and the first solder resist layer may be slightly higher, slightly lower than or slightly flush with each of the metal bumps, and the first openings are Greater than or equal to each of the metal bumps.

It can be seen that the package substrate of the present invention and the manufacturing method thereof are integrally formed on the electrical contact pad by the metal bump, so that the metal bump is completely bonded to the electrical contact pad to improve the quality of the electrical connection. The purpose is to form a metal bump on the electrical contact pad to reduce the opening depth of the solder resist layer, so as to improve the uniformity of the solder bump and improve the quality of the electrical connection.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

Please refer to FIGS. 2A to 2J for providing the package substrate of the present invention and a method of manufacturing the same.

As shown in FIG. 2A, a plate body 20 is provided, and the plate body 20 can be one of a ceramic plate, a metal plate, and an organic plate; or the plate body 20 can be a core plate having a line on the surface and having a core. One of a multi-layer board, a coreless single-layer board, and a coreless multi-layer board. In this embodiment, the board body 20 is a coreless single layer board and has opposite first and second surfaces 20a, 20b, and has a line 201 formed on the first and second surfaces 20a, 20b, or The line 201 is embedded and exposed on the first and second surfaces 20a, 20b, and the line 201 has a plurality of first and second electrical connection pads 201a, 201b.

As shown in FIG. 2B, first and second dielectric layers 21 are formed on the first and second surfaces 20a, 20b of the board 20 and the first and second electrical connection pads 201a, 201b, respectively. 22; as shown in FIG. 2B', a metal is formed on the outer surface of the first and second surfaces 20a, 20b of the board 20 and the first and second electrical connection pads 201a, 201b, respectively. The first and second dielectric layers 21', 22' of the films 21a, 22a are, for example, a resin coated copper (RCC), and the metal films 21a, 22a are removed to reveal the first And a second dielectric layer 21', 22'.

As shown in FIG. 2C, a plurality of first and second blind vias 211, 221 are formed on the first and second dielectric layers 21, 22 to expose the first and second electrical connection pads 201a, 201b, respectively. And forming first and second slots 212, 222 of the first and second blind holes 211, 221 of the first and second dielectric layers 21, 22; wherein the first and second blind holes 211, 221, And the first and second slots 212, 222 are formed in a laser manner.

As shown in FIG. 2D, the first and second dielectric layers 21, 22, the first and second blind vias 211, 221, the sidewalls of the first and second slots 212, 222, and the first and second A conductive layer 23 is formed on the electrical connection pads 201a, 201b, and the conductive layer 23 is mainly used as a current conduction path required for plating a metal material, which may be composed of metal or a plurality of deposited metal layers, such as copper, tin, and the like. A single layer or a multilayer structure such as nickel, chromium, titanium or copper-chromium, or a conductive polymer material such as polyacetylene, polyaniline or organic sulfur polymer can be used.

As shown in FIG. 2E, a copper-based metal layer 24 is formed on the conductive layer 23 by electroplating for the first and second slots 212, 222. Forming first and second circuit layers 242, 252, and the first and second circuit layers 242, 252 have a plurality of first and second electrical contact pads 243, 253; and forming first and first in each of the first and second blind vias 211, 221 The second conductive vias 241, 251 are electrically connected to the first and second electrical connection pads 201a, 201b.

As shown in FIG. 2F, a resist layer 27 is formed on the metal layer 24 on the first dielectric layer 21, and a plurality of open regions 270 are formed in the resist layer 27 to expose a portion of the metal layer 24, and each The first electrical contact pad 243 on the first dielectric layer 21 and the metal layer 24 on the first conductive via 241 are correspondingly provided with a resist layer 27.

As shown in FIG. 2G, the metal layer 24 exposed in the opening region 270 and the first and second circuit layers 242, 252 and the conductive layer 23 covered thereon are removed by etching to facilitate the first dielectric. Copper-based metal bumps 244 are formed on each of the first electrical contact pads 243 and the first conductive vias 241 on the layer 21.

As shown in FIG. 2H, the resist layer 27 is removed to expose the surface of each of the metal bumps 244, the first and second circuit layers 242, 252, and a portion of the first conductive vias 241 are electrically connected to the surface. Metal bumps 244.

The metal layer 24 is simultaneously formed on the first electrical contact pad 243 and the first conductive via 241, and the metal layer 24 is etched to form the first electrical contact pad 243 and the first conductive via hole. The metal bump 244 is integrally formed on the first electrical contact pad 243 and the first conductive blind via 241; and the first wiring layer 242 is formed on the first dielectric layer. 21, the first electrical contact pad 243 is embedded And exposing the surface of the first dielectric layer 21 so that there is no gap between the first opening 212 and the first electrical contact pad 243, so that the metal bump 244 is completely bonded to the first electrical contact pad 243. The metal bumps 244 are also completely bonded to the first conductive vias 241.

As shown in FIG. 2I, first and second solder resist layers 27, 28 are formed on the first and second dielectric layers 21, 22, and a plurality of first and second solder resist layers 27, 28 are formed. The first opening 270a, 270b and the second opening 280 are oppositely exposed to expose the metal bump 244 and the second electrical contact pad 253, and a portion of the first opening 270a is larger than each of the metal protrusions Block 244, and other portions of the first opening 270b are equal in size to each of the metal bumps 244; in this embodiment, the first solder resist layer 27 is slightly flush with each of the metal bumps 244, however, in other embodiments The first solder resist layer 27 may also be slightly lower or slightly higher than each of the metal bumps 244 (not shown).

As shown in FIG. 2I', the structure is similar to that of FIG. 2I, but each of the first openings 270a, 270b is equal in size to each of the metal bumps 244.

As shown in FIG. 2I, the structure is similar to that of FIG. 2I, but each of the first openings 270a, 270b is larger in size than each of the metal bumps 244.

As shown in FIG. 2J, a surface treatment layer 30 is formed on each of the metal bumps 244 for bonding the solder bumps 29, and the material of the surface treatment layer 30 is tin (Sn), lead (Pb), silver ( One of a group of Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), and gold (Au).

The metal bumps 244 of the present invention are completely bonded to the first electrical contact pads 243 and the first conductive vias 241, and solder bumps 29 are formed in the first openings 270a, 270b of the first solder resist layer 27. When the solder bump The solder bumps 29 are electrically connected to the first electrical contact pads 243 and the first conductive blind vias 241; that is, the electrical contact pads and the conductive blinds are only required to be bonded to the metal bumps 244. The formation of the holes is done at the same time, without the need for an additional plating process, which saves costs.

Moreover, the solder resist layer 27 is slightly flush, slightly lower than or slightly higher than each of the metal bumps 244 to facilitate the formation of the surface treatment layer 30 on the metal bumps 244, and the solder bumps 29 are easily formed. In the first openings 270a, 270b, the germanium is used to avoid the occurrence of voids, so as to effectively improve the electrical connection quality, and the solder bumps 29 can be formed on the fine pitch metal bumps 244 for subsequent packaging. Semiconductor wafers are placed with better reliability.

The present invention discloses a package substrate, as shown in FIG. 2H, comprising: a board body 20 having a line 201 having opposite first and second surfaces 20a, 20b; first and second dielectric layers 21, 22, respectively disposed on the first and second surfaces 20a, 20b of the board 20; the first and second circuit layers 242, 252 are respectively embedded and exposed on the surfaces of the first and second dielectric layers 21, 22 The first and second circuit layers 242, 252 have a plurality of first and second electrical contact pads 243, 253, and a plurality of metal bumps 244 corresponding to the first electrical contact pads 243 disposed on the first surface 20a. The first and second conductive vias 241, 251 are electrically connected to the circuit 201, and the first and second conductive vias 241, 251 are electrically connected to the first and second circuit layers 242, 252, and other portions The first and second conductive vias 241, 251 are electrically connected to the metal bumps 244.

In addition, the material of the metal bump 244 is copper, and the surface of the metal bump 244 is provided with a surface treatment layer 30 for bonding the solder bumps 29, The material of the surface treatment layer 30 is tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd) and One of the groups of gold (Au).

Moreover, the package substrate further includes first and second solder resist layers 27, 28, as shown in FIG. 2I, disposed on the first and second dielectric layers 21, 22, the first and second circuit layers 242, 252, and the first and second solder resist layers 27, 28 have a plurality of first and second openings 270a, 270b, 280, to expose each of the metal bumps 244 and the second electrical contact pads 253; Wherein, the first solder resist layer 27 is slightly lower than, slightly higher than (not shown) or slightly flush (as shown in FIG. 2I) each of the metal bumps 244, the first opening 270a, The dimension of 270b is greater than each of the metal bumps 244, as shown in FIG. 2I", or the first openings 270a, 270b are sized to be equal to each of the metal bumps 244, as shown in FIG. 2I'.

In summary, the package substrate of the present invention and the manufacturing method thereof are integrally formed on the electrical contact pad by the metal bump, so that the metal bump is completely bonded to the electrical contact pad to avoid the hole phenomenon.俾 can effectively improve the electrical connection quality; and the metal contact pads are formed on the electrical contact pad, which can reduce the opening depth of the solder resist layer, so as to form solder bumps on the fine pitch metal bumps for Subsequent to the packaging, it facilitates the connection of the semiconductor wafer and has better reliability.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as follows. Listed around.

10,20‧‧‧ board

101,102‧‧‧ Inner line

101a, 101b‧‧‧Electrical connection pads

11,12‧‧‧ dielectric layer

14,15‧‧‧ circuit layer

141,151‧‧‧ conductive blind holes

142,152,201‧‧‧ lines

143,153‧‧‧Electrical contact pads

17,18‧‧‧ solder mask

170,180‧‧‧ openings

19,29‧‧‧ solder bumps

20a‧‧‧ first surface

20b‧‧‧second surface

201a‧‧‧First electrical connection pad

201b‧‧‧Second electrical connection pad

21,21’‧‧‧First dielectric layer

21a, 22a‧‧‧Metal film

211‧‧‧ first blind hole

212‧‧‧First slotting

22,22’‧‧‧second dielectric layer

221‧‧‧ second blind hole

222‧‧‧Second slotting

23‧‧‧ Conductive layer

24‧‧‧metal layer

241‧‧‧First conductive blind hole

242‧‧‧First line layer

243‧‧‧First electrical contact pads

244‧‧‧Metal bumps

251‧‧‧Second conductive blind hole

252‧‧‧Second circuit layer

253‧‧‧Second electrical contact pads

27‧‧‧resist

27‧‧‧First solder mask

270‧‧‧Open area

270a, 270b‧‧‧ first opening

28‧‧‧Second solder mask

280‧‧‧Second opening

30‧‧‧Surface treatment layer

A‧‧‧pores

1A to 1C are schematic views showing a method of manufacturing a conventional package substrate; wherein, FIG. 1C' is a partial enlarged view of FIG. 1C; and FIGS. 2A to 2J are schematic views showing a method of manufacturing a package substrate of the present invention; 2B' is another embodiment of FIG. 2B; FIG. 2I' is another embodiment of FIG. 2I, and FIG. 2I is a second embodiment of FIG.

20‧‧‧ board

20a‧‧‧ first surface

20b‧‧‧second surface

201‧‧‧ lines

201a‧‧‧First electrical connection pad

201b‧‧‧Second electrical connection pad

21‧‧‧First dielectric layer

22‧‧‧Second dielectric layer

241‧‧‧First conductive blind hole

251‧‧‧Second conductive blind hole

242‧‧‧First line layer

252‧‧‧Second circuit layer

243‧‧‧First electrical contact pads

253‧‧‧Second electrical contact pads

244‧‧‧Metal bumps

Claims (21)

A package substrate comprising: a plate body having opposite first and second surfaces; first and second dielectric layers respectively disposed on the first and second surfaces of the plate body; first and second The two circuit layers are respectively embedded and exposed in the first and second dielectric layers, and respectively have a plurality of first and second electrical contact pads; and a plurality of metal bumps are disposed on each of the first electrical properties On the contact pad. The package substrate of claim 1, wherein the plate body is a ceramic plate, a metal plate, or an organic plate. The package substrate of claim 1, wherein the board system is a core board having a line on the surface, a multi-layer board having a core, a single-layer board without a core, or a multi-layer board without a core. The package substrate of claim 3, wherein the first and second circuit layers respectively have first and second conductive blind holes for electrically connecting the wires. The package substrate of claim 1, wherein the material of the metal bump is copper. The package substrate of claim 1, further comprising a surface treatment layer formed on the metal bump for bonding the solder bumps. The package substrate of claim 6, wherein the material of the surface treatment layer is tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi). , nickel (Ni), palladium (Pd) and gold (Au) One of the groups. The package substrate of claim 1 , further comprising first and second solder resist layers respectively disposed on the first and second dielectric layers, the first and second circuit layers, and the first and The second solder mask has a plurality of first and second openings, respectively, to respectively expose the metal bumps and the second electrical contact pads. The package substrate of claim 8, wherein the first solder resist layer is slightly lower, slightly higher or slightly flush with each of the metal bumps. The package substrate of claim 8, wherein the first opening is greater than or equal to each of the metal bumps. A method for manufacturing a package substrate, comprising: providing a plate body having opposite first and second surfaces; forming first and second dielectric layers on the first and second surfaces of the plate body; Forming a plurality of first and second slots on the surface of the first and second dielectric layers; forming a conductive layer on the first and second trenches and the surfaces of the first and second dielectric layers; Forming a metal layer on the layer to form first and second circuit layers in each of the first and second slots, and the first and second circuit layers have a plurality of first and second electrical contact pads; A portion of the metal layer and the conductive layer thereof are removed to form metal bumps on the first electrical contact pads and to expose the first and second circuit layers. The method of manufacturing a package substrate according to claim 11, wherein the plate body is a ceramic plate, a metal plate, or an organic plate. The method for manufacturing a package substrate according to claim 11, wherein the board system is a core board having a line on the surface, a multi-layer board having a core, a single-layer board without a core, or a multi-layer board without a core. The method for manufacturing a package substrate according to claim 13 , wherein the first and second circuit layers respectively comprise first and second conductive blind holes to be electrically connected to the circuit. The method for manufacturing a package substrate according to claim 14, wherein the first and second conductive via holes are formed by forming a plurality of first and second blind holes on the first and second dielectric layers. And corresponding to the exposed portion of the line as the first and second electrical connection pads, and the first and second slotted portions of the first and second slotted portions; the first and second The conductive layer is formed on the dielectric layer, the sidewalls of each of the first and second blind vias, the sidewalls of the first and second trenches, and each of the first and second electrical connection pads; and the conductive layer Forming the metal layer on the layer to form first and second conductive via holes in each of the first and second blind vias, and electrically connecting the first and second circuit layers to the first and second electrical regions Connection pad. The method for manufacturing a package substrate according to claim 15 , wherein the blind holes and the grooves are formed by laser. The method for manufacturing a package substrate according to claim 11, wherein the metal layer and the material of the metal bumps are copper. The method for manufacturing a package substrate according to claim 11 is characterized in that a surface treatment layer is formed on the surface of the metal bumps. The method for manufacturing a package substrate according to claim 18, wherein the material of the surface treatment layer is tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth ( One of a group consisting of Bi), nickel (Ni), palladium (Pd), and gold (Au). The method for manufacturing a package substrate according to claim 11, further comprising forming first and second solder resist layers on the surfaces of the first and second dielectric layers and the first and second circuit layers, and A plurality of first and second openings are formed in the first and second solder resist layers to respectively expose the metal bumps and the second electrical contact pads. The method for manufacturing a package substrate according to claim 20, wherein the first solder resist layer is slightly higher, slightly lower than or slightly flush with each of the metal bumps, and the first opening systems are greater than or Equal to each of the metal bumps.