JP2006237151A - Wiring board and semiconductor apparatus - Google Patents

Wiring board and semiconductor apparatus Download PDF

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Publication number
JP2006237151A
JP2006237151A JP2005047492A JP2005047492A JP2006237151A JP 2006237151 A JP2006237151 A JP 2006237151A JP 2005047492 A JP2005047492 A JP 2005047492A JP 2005047492 A JP2005047492 A JP 2005047492A JP 2006237151 A JP2006237151 A JP 2006237151A
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Prior art keywords
semiconductor element
wiring board
wiring
wiring pattern
insulating film
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JP2005047492A
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Japanese (ja)
Inventor
Masahiro Haruhara
昌宏 春原
Hiroshi Murayama
啓 村山
Koji Yamano
孝治 山野
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2005047492A priority Critical patent/JP2006237151A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of reliably mounting a semiconductor device by flip-chip connection even if the clearance for filling an underfill material between the semiconductor device and the wiring board becomes narrow following a decrease in the pitch of the semiconductor device, and to provide a semiconductor apparatus using the wiring board. <P>SOLUTION: In the wiring board 10 on which the semiconductor device 60 is mounted by the flip-chip connection, a wiring pattern 20 having a connection terminal 30 electrically connected to the semiconductor device 60 is formed at a semiconductor device mounting region. In the wiring pattern 20, insulating film formation processing is performed for covering a surface with an insulating film 100, and the insulating film 100 is removed for a part in which the connection terminal 30 is formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、フリップチップ接続により半導体素子を搭載する配線基板および半導体装置に関する。   The present invention relates to a wiring board and a semiconductor device on which a semiconductor element is mounted by flip chip connection.

フリップチップ接続により半導体素子を搭載する半導体装置としては、例えば図５に示す構成のものが知られている。この半導体装置は、半導体素子６０の電極７０が、両面に配線パターン２０が形成された配線基板１０の接続端子３０と、はんだからなるバンプ８０を介してフリップチップ接続により接続され、半導体素子６０と配線基板１０との間隙（ギャップ）Ａは、接続信頼性および耐湿性を向上させるためアンダーフィル材９０によって樹脂封止されている。なお、半導体素子６０の電極形成面には、バンプ８０との接続部となる電極７０を除いて、パッシベーション膜６５が形成されている。また、配線パターン２０の上面を含む配線基板１０の両面には、バンプ８０との接続部となる接続端子３０を除いて、ソルダーレジスト層４０が形成され、配線パターン２０にはんだが付着することを防止すると共に、配線パターン２０を外気等から保護している。   As a semiconductor device on which a semiconductor element is mounted by flip chip connection, for example, a semiconductor device having the configuration shown in FIG. 5 is known. In this semiconductor device, an electrode 70 of a semiconductor element 60 is connected to a connection terminal 30 of a wiring board 10 having a wiring pattern 20 formed on both sides by a flip chip connection via a bump 80 made of solder. The gap (gap) A with the wiring substrate 10 is resin-sealed with an underfill material 90 in order to improve connection reliability and moisture resistance. A passivation film 65 is formed on the electrode formation surface of the semiconductor element 60 except for the electrodes 70 that are to be connected to the bumps 80. In addition, a solder resist layer 40 is formed on both surfaces of the wiring substrate 10 including the upper surface of the wiring pattern 20 except for the connection terminals 30 serving as connection portions with the bumps 80, and solder adheres to the wiring pattern 20. In addition to preventing, the wiring pattern 20 is protected from the outside air or the like.

半導体素子６０と配線基板１０との間隙（ギャップ）Ａをアンダーフィル材９０によって樹脂封止する際には、半導体素子６０の側面からアンダーフィル材９０を流入させ、間隙（ギャップ）Ａをアンダーフィル材９０で充填している（特許文献１参照）。
特開２０００−９１３８２号 When resin sealing the gap (gap) A between the semiconductor element 60 and the wiring substrate 10 with the underfill material 90, the underfill material 90 is introduced from the side surface of the semiconductor element 60, and the gap (gap) A is filled with the underfill. It is filled with the material 90 (refer patent document 1).
JP 2000-91382 A

図５に示す従来の半導体装置において、フリップチップ接続部を構成するバンプ８０の高さは、バンプ８０が接続される電極７０の大きさとほぼ同じであり、６０〜８０μｍ程度であるが、近年の半導体素子の小型化・高密度化に伴い縮小される傾向にあり、３０〜５０μｍ程度のものが登場している。
一方、配線基板１０の半導体素子搭載面には、接続端子３０を除くほぼ全面にソルダーレジスト層４０が形成されており、また、半導体素子６０の電極形成面には、電極７０を除くほぼ全面にパッシベーション膜６５が形成されている。したがって、アンダーフィル材９０を流入させる間隙Ａは、実質的にはソルダーレジスト層４０の表面とパッシベーション膜６５の表面との間隔となる。
ソルダーレジスト層４０の厚さは配線パターン２０の上で通常２０μｍ程度、パッシベーション膜６５の厚さは通常５μｍ程度であるから、電極７０の大きさが従来の６０〜８０μｍ程度の場合、上述の通り、間隙Ａは３５〜５５μｍ程度となる。電極７０の大きさが３０〜５０μｍ程度に縮小された場合、間隙Ａは５〜２５μｍ程度となる。 In the conventional semiconductor device shown in FIG. 5, the height of the bump 80 constituting the flip chip connecting portion is almost the same as the size of the electrode 70 to which the bump 80 is connected, and is about 60 to 80 μm. There is a tendency to shrink as semiconductor elements become smaller and higher in density, and those with a size of about 30 to 50 μm have appeared.
On the other hand, a solder resist layer 40 is formed on almost the entire surface excluding the connection terminals 30 on the semiconductor element mounting surface of the wiring substrate 10, and the electrode forming surface of the semiconductor element 60 is formed on almost the entire surface excluding the electrode 70. A passivation film 65 is formed. Accordingly, the gap A through which the underfill material 90 flows is substantially the distance between the surface of the solder resist layer 40 and the surface of the passivation film 65.
Since the thickness of the solder resist layer 40 is usually about 20 μm on the wiring pattern 20 and the thickness of the passivation film 65 is usually about 5 μm, when the size of the electrode 70 is about 60 to 80 μm, as described above, The gap A is about 35 to 55 μm. When the size of the electrode 70 is reduced to about 30 to 50 μm, the gap A is about 5 to 25 μm.

このように、間隙Ａが５〜２５μｍ程度と狭くなると、アンダーフィル材９０を間隙Ａに均一に流入させることが困難になって、ボイドが発生しやすくなり、半導体装置の信頼性が低下するという問題が生じる。   Thus, when the gap A becomes as narrow as about 5 to 25 μm, it becomes difficult to uniformly flow the underfill material 90 into the gap A, voids are likely to occur, and the reliability of the semiconductor device is reduced. Problems arise.

また、製造工程上の何らかの影響で配線基板１０が反ってしまった場合には、間隙Ａが不均一となり、フリップチップ接続部のオープン不良が発生しやすくなる。この問題も間隙Ａが３０μｍ以下になると顕著にあらわれる。   Further, when the wiring substrate 10 is warped due to some influence on the manufacturing process, the gap A becomes non-uniform, and an open defect of the flip chip connection portion is likely to occur. This problem is also prominent when the gap A is 30 μm or less.

なお、ソルダーレジスト層４０を形成しないようにすれば、ソルダーレジスト層４０の厚さの分だけ間隙Ａを広くすることができるが、ソルダーレジスト層４０を設けないと配線パターン２０のみならず隣接する配線パターンとの間にも、フリップチップ接続するためのバンプ８０のはんだが流れ出し、配線パターンのショート不良を引き起こすおそれがある。   If the solder resist layer 40 is not formed, the gap A can be widened by the thickness of the solder resist layer 40. However, if the solder resist layer 40 is not provided, not only the wiring pattern 20 but also adjacent to it. The solder of the bump 80 for flip chip connection also flows out between the wiring patterns, which may cause a short circuit failure of the wiring pattern.

そこで、本発明においては、半導体素子の狭ピッチ化とともに電極の大きさが小さくなり、バンプの高さが低くなるに伴い、半導体素子と配線基板との間のアンダーフィル材を流入させる間隙が狭くなっても、フリップチップ接続により好適に半導体素子を搭載できる配線基板およびこの配線基板を用いた半導体装置を提供することを目的としている。   Therefore, in the present invention, as the pitch of the semiconductor element is reduced and the size of the electrode is reduced and the height of the bump is reduced, the gap for inflow of the underfill material between the semiconductor element and the wiring board is narrowed. Even if it becomes, it aims at providing the wiring board which can mount a semiconductor element suitably by flip chip connection, and the semiconductor device using this wiring board.

上記目的を達成するために、本発明の配線基板および半導体装置は次の構成を備える。 すなわち、フリップチップ接続により半導体素子を搭載する配線基板において、半導体素子搭載領域に、前記半導体素子と電気的に接続される接続端子を備えた配線パターンが形成され、該配線パターンは、絶縁膜形成処理が施されて表面に絶縁膜が被覆されるとともに、前記接続端子が形成された部位については前記絶縁膜が除去されて形成されていることを特徴とする。なお、前記絶縁膜形成処理とは、配線パターンの基材に対して化学的な処理、たとえば熱酸化処理、黒化処理、硫化処理等を施し、配線パターンの表面に酸化膜、硫化膜等の電気的な絶縁膜を形成することをいう。   In order to achieve the above object, a wiring board and a semiconductor device of the present invention have the following configuration. That is, in a wiring substrate on which a semiconductor element is mounted by flip-chip connection, a wiring pattern having a connection terminal electrically connected to the semiconductor element is formed in the semiconductor element mounting region, and the wiring pattern is formed by forming an insulating film. The surface is coated with an insulating film, and the insulating film is removed from the portion where the connection terminal is formed. The insulating film forming process is a chemical process such as a thermal oxidation process, a blackening process, a sulfidation process, or the like performed on the substrate of the wiring pattern, and an oxide film, a sulfide film, etc. It means forming an electrical insulating film.

また、前記配線パターンが、銅からなり、前記絶縁膜形成処理として熱酸化処理が施されて、前記配線パターンの表面に酸化膜が形成されていること、また、前記配線パターンが、銅からなり、前記絶縁膜形成処理として黒化処理が施されて、前記配線パターンの表面に酸化膜が形成されていることにより、酸化膜が電気的な絶縁膜として有効に作用するとともに、配線パターン上におけるはんだ等の接合金属の流れ性を抑制して配線パターン間のショート不良を防止する。
また、前記配線パターンの接続端子に、前記半導体素子の電極と接続端子とを接合するはんだ層が被着形成されていることにより、半導体素子を容易に配線基板に搭載することが可能になる。 Further, the wiring pattern is made of copper, a thermal oxidation process is performed as the insulating film forming process, and an oxide film is formed on the surface of the wiring pattern, and the wiring pattern is made of copper. Since the blackening process is performed as the insulating film forming process and the oxide film is formed on the surface of the wiring pattern, the oxide film effectively acts as an electrical insulating film, and on the wiring pattern. Suppresses the flowability of bonding metal such as solder and prevents short circuit defects between wiring patterns.
In addition, since the solder layer for bonding the electrode of the semiconductor element and the connection terminal is formed on the connection terminal of the wiring pattern, the semiconductor element can be easily mounted on the wiring board.

また、前記配線基板の両面に、基板を貫通して形成された導体層を介して電気的に接続された配線パターンが各々形成され、前記配線基板の一方の面に半導体素子搭載領域が形成され、前記配線基板の他方の面のみに、前記配線パターンを被覆するソルダーレジスト層が設けられていることを特徴とする。
また、前記配線基板の他方の面に形成された配線パターンに、絶縁膜形成処理が施されていることにより、配線パターンとソルダーレジスト層との密着性を向上させることができる。 Further, wiring patterns electrically connected via a conductor layer formed through the substrate are formed on both surfaces of the wiring substrate, respectively, and a semiconductor element mounting region is formed on one surface of the wiring substrate. A solder resist layer that covers the wiring pattern is provided only on the other surface of the wiring board.
In addition, since the insulating film forming process is performed on the wiring pattern formed on the other surface of the wiring substrate, the adhesion between the wiring pattern and the solder resist layer can be improved.

また、前記配線基板にフリップチップ接続により半導体素子が搭載された半導体装置であって、前記半導体素子と前記配線パターンの接続端子とが、バンプを介して電気的に接続され、前記半導体素子と前記配線基板との間にアンダーフィル材が充填されて、前記半導体素子と配線基板とが一体に接合されていることを特徴とする。
また、前記半導体素子が、金からなるスタッドバンプが電極に形成されたものであり、該スタッドバンプを介して前記半導体素子と前記接続端子とが電気的に接続されていることを特徴とする。スタッドバンプを介して接続することにより、はんだの流れ出しを防止し、より確実に半導体素子を実装することが可能となる。 Further, in the semiconductor device in which a semiconductor element is mounted on the wiring board by flip chip connection, the semiconductor element and a connection terminal of the wiring pattern are electrically connected via a bump, and the semiconductor element and the An underfill material is filled between the wiring substrate and the semiconductor element and the wiring substrate are integrally bonded.
Further, the semiconductor element is characterized in that a stud bump made of gold is formed on an electrode, and the semiconductor element and the connection terminal are electrically connected through the stud bump. By connecting via the stud bumps, the solder can be prevented from flowing out and the semiconductor element can be more reliably mounted.

本発明に係る配線基板およびこの配線基板を用いた半導体装置によれば、半導体素子搭載領域に形成される配線パターンに絶縁膜形成処理が施され、配線パターンの表面に絶縁膜が形成されて、配線パターンの表面にはソルダーレジスト層が被着形成されていないことにより、アンダーフィル材が充填される半導体素子と配線基板との間隙を十分に確保することができ、ボイド等を生じさせずに均一にかつ容易にアンダーフィル材を充填することが可能になる。これによって、半導体素子の電極の大きさがより小さくなっても、半導体素子を確実に配線基板に実装することが可能になる。   According to the wiring board according to the present invention and the semiconductor device using the wiring board, an insulating film forming process is performed on the wiring pattern formed in the semiconductor element mounting region, and an insulating film is formed on the surface of the wiring pattern. Since the solder resist layer is not formed on the surface of the wiring pattern, a sufficient gap between the semiconductor element filled with the underfill material and the wiring board can be secured without causing voids or the like. It becomes possible to fill the underfill material uniformly and easily. As a result, the semiconductor element can be reliably mounted on the wiring board even if the size of the electrode of the semiconductor element becomes smaller.

以下、本発明の好適な実施の形態について添付図面にしたがって詳細に説明する。
図1は、本発明に係る半導体装置の一実施形態の構成を示す断面図である。この半導体装置は、半導体素子６０の電極７０が、両面に配線パターン２０が形成された配線基板１０の接続端子３０と、バンプ８０を介してフリップチップ接続により接続され、半導体素子６０と配線基板１０との間隙部分は、アンダーフィル材９０によって樹脂封止されている。 DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing a configuration of an embodiment of a semiconductor device according to the present invention. In this semiconductor device, the electrode 70 of the semiconductor element 60 is connected to the connection terminal 30 of the wiring board 10 having the wiring pattern 20 formed on both surfaces thereof by flip chip connection via the bumps 80, and the semiconductor element 60 and the wiring board 10 are connected. The gap portion is sealed with resin by an underfill material 90.

本実施形態の配線基板１０において特徴的な構成は、配線基板１０の半導体素子搭載面に形成されている銅からなる配線パターン２０の表面に銅の酸化膜１００が形成されていること、配線パターン２０の表面を被覆する酸化膜１００のうち、バンプ８０が接合される接続端子３０部位が配線パターン２０の基材である銅が露出して形成されていることにある。これによって、配線基板１０の半導体素子搭載面についてはソルダーレジスト層４０を設けることなく、半導体素子６０と配線基板１０との間隙部分にアンダーフィル材９０が充填される。   A characteristic configuration of the wiring board 10 of the present embodiment is that the copper oxide film 100 is formed on the surface of the wiring pattern 20 made of copper formed on the semiconductor element mounting surface of the wiring board 10, and the wiring pattern. In the oxide film 100 that covers the surface of 20, the connection terminal 30 portion to which the bump 80 is bonded is formed by exposing copper as a base material of the wiring pattern 20. Thus, the underfill material 90 is filled in the gap between the semiconductor element 60 and the wiring board 10 without providing the solder resist layer 40 on the semiconductor element mounting surface of the wiring board 10.

本実施形態の半導体装置では、配線基板１０の半導体素子搭載面とは反対側の面に形成される配線パターン２０についても、配線パターン２０の表面に銅の酸化膜１００を形成し、銅の酸化膜１００が形成された配線パターン２０を覆うようにソルダーレジスト層４０を設けている。なお、配線基板１０の半導体素子搭載面とは反対側の面に形成する配線パターン２０については、その表面に酸化膜１００を形成しないことも可能である。ただし、配線パターン２０の表面に酸化膜１００を形成した場合は、ソルダーレジスト層４０との密着性が良好になるという利点がある。   In the semiconductor device of this embodiment, the copper oxide film 100 is formed on the surface of the wiring pattern 20 on the surface of the wiring substrate 10 opposite to the surface on which the semiconductor element is mounted, and the copper oxide film 100 is oxidized. A solder resist layer 40 is provided so as to cover the wiring pattern 20 on which the film 100 is formed. Note that the oxide film 100 may not be formed on the surface of the wiring pattern 20 formed on the surface opposite to the semiconductor element mounting surface of the wiring substrate 10. However, when the oxide film 100 is formed on the surface of the wiring pattern 20, there is an advantage that the adhesion with the solder resist layer 40 is improved.

図２は、図１に示す半導体装置に搭載されている半導体素子６０の構成を示す断面図である。半導体素子６０の電極７０には、フリップチップ接続を容易かつ確実に行うため、金からなるスタッドバンプ１１０が形成されている。図１は、スタッドバンプ１１０が形成された半導体素子６０を配線基板１０に配置し、接続端子３０に被着されたはんだを溶融してスタッドバンプ１１０にはんだがはい上がり、球形状のバンプ８０が形成された状態を示す。なお、半導体素子６０の電極７０に形成するバンプとしては、金めっきからなるバンプ、はんだボールを用いたバンプを使用することもできる。   FIG. 2 is a cross-sectional view showing the configuration of the semiconductor element 60 mounted on the semiconductor device shown in FIG. A stud bump 110 made of gold is formed on the electrode 70 of the semiconductor element 60 for easy and reliable flip chip connection. In FIG. 1, the semiconductor element 60 on which the stud bump 110 is formed is disposed on the wiring board 10, the solder applied to the connection terminal 30 is melted, and the solder bumps up to the stud bump 110, so that the spherical bump 80 is formed. The formed state is shown. In addition, as a bump formed on the electrode 70 of the semiconductor element 60, a bump made of gold plating or a bump using a solder ball can be used.

図３および図４は、本発明に係る配線基板および半導体装置の製造方法の工程説明図、図５は製造工程のフロー図である。以下にこの製造方法を順を追って説明する。
図３（ａ）は、配線基板１０の両面に配線パターン２０を形成した状態を示す。配線パターン２０は、ウェットエッチング法等、公知の方法を用いて形成することができる。また、配線基板１０にスルーホール５０を形成し、スルーホール５０の内側面に導体層５５を形成することにより、配線基板１０の両面の配線パターン２０が電気的に接続される。 3 and 4 are process explanatory views of a method for manufacturing a wiring board and a semiconductor device according to the present invention, and FIG. 5 is a flowchart of the manufacturing process. This manufacturing method will be described below step by step.
FIG. 3A shows a state in which the wiring pattern 20 is formed on both surfaces of the wiring substrate 10. The wiring pattern 20 can be formed using a known method such as a wet etching method. Further, by forming the through hole 50 in the wiring substrate 10 and forming the conductor layer 55 on the inner side surface of the through hole 50, the wiring patterns 20 on both surfaces of the wiring substrate 10 are electrically connected.

次に、図３（ｂ）に示すように、配線基板１０の両面に形成された配線パターン２０の表面全体に、銅の酸化膜１００を形成する。銅の酸化膜は、詳細には酸化第二銅、または酸化第二銅および酸化第一銅からなり、配線基板１０を約２００°Ｃに加熱すること（熱酸化）により形成できる。あるいは、配線基板１０を亜塩素酸ナトリウムと水酸化ナトリウムの混合液等のアルカリ性の液に浸漬しても良い（黒化処理）。酸化第二銅および酸化第一銅ははんだに濡れない性質を持っているため、銅の酸化膜１００の厚さは、０．１μｍ以下で十分である。   Next, as shown in FIG. 3B, a copper oxide film 100 is formed on the entire surface of the wiring pattern 20 formed on both surfaces of the wiring substrate 10. Specifically, the copper oxide film is made of cupric oxide, or cupric oxide and cuprous oxide, and can be formed by heating the wiring substrate 10 to about 200 ° C. (thermal oxidation). Alternatively, the wiring board 10 may be immersed in an alkaline solution such as a mixed solution of sodium chlorite and sodium hydroxide (blackening treatment). Since cupric oxide and cuprous oxide do not get wet with solder, the thickness of the copper oxide film 100 is sufficient to be 0.1 μm or less.

次に、図３(c)に示すように、配線基板１０の半導体素子非搭載面（図の下面）のみにソルダーレジスト層４０を形成する。配線パターン２０の表面に酸化膜１００を形成したことにより、配線パターン２０の表面が粗面に形成され、配線パターン２０とソルダーレジスト層４０との密着性が良好になる。なお、配線パターン２０の表面に酸化膜１００を形成する前工程で、配線基板１０の半導体素子非搭載面をソルダーレジスト層４０によって被覆し、配線基板１０の半導体素子搭載面に設けられた配線パターン２０のみに酸化膜１００を形成する製造工程とすることもできる。配線基板１０の一方の面のみにソルダーレジスト層４０を形成することで、ソルダーレジスト層４０を形成する一工程が省略できるという利点がある。   Next, as shown in FIG. 3C, the solder resist layer 40 is formed only on the surface of the wiring board 10 where the semiconductor element is not mounted (the lower surface in the drawing). By forming the oxide film 100 on the surface of the wiring pattern 20, the surface of the wiring pattern 20 is formed to be rough, and the adhesion between the wiring pattern 20 and the solder resist layer 40 is improved. The wiring pattern provided on the semiconductor element mounting surface of the wiring substrate 10 by covering the semiconductor element non-mounting surface of the wiring substrate 10 with the solder resist layer 40 in the previous step of forming the oxide film 100 on the surface of the wiring pattern 20. A manufacturing process for forming the oxide film 100 only on the substrate 20 can also be adopted. By forming the solder resist layer 40 only on one surface of the wiring substrate 10, there is an advantage that one step of forming the solder resist layer 40 can be omitted.

次に、図３(d)に示すように、配線基板１０の半導体素子搭載面の全面にレジスト層１２０を被着形成し、フォトリソグラフィ法を用いてレジスト層１２０に開口部１３０を形成し、開口部１３０に露出した銅の酸化膜１００をエッチングして除去することにより、接続端子３０を形成する。レジスト層１２０の厚さは通常１０〜４０μｍ、好ましくは約３０μｍである。   Next, as shown in FIG. 3D, a resist layer 120 is deposited over the entire surface of the semiconductor element mounting surface of the wiring substrate 10, and an opening 130 is formed in the resist layer 120 using a photolithography method. The connection terminal 30 is formed by etching away the copper oxide film 100 exposed in the opening 130. The thickness of the resist layer 120 is usually 10 to 40 μm, preferably about 30 μm.

次に、図３(d)の状態で、配線基板１０の半導体素子搭載面の全面に、バリア層（図示せず）となるＮｉ層を無電解めっきにより、厚さ１〜７μｍ好ましくは約５μｍ形成し、更にその上に、前記Ｎｉ層を給電層とする電解めっきにより、はんだ層１５０を、上面がレジスト層１２０より若干低くなる程度に形成した後、外部に露出しているＮｉ層、次いでレジスト層１２０を除去する。これにより、はんだ層１５０が銅の酸化膜１００から突出して盛り上がるように形成された配線基板１０が完成する（図３(e)）。
なお、バリア層は銅および金の拡散を防止するためのものであり、Ｎｉの代わりにＣｒ、Ｔｉ、ＴｉＷ、ＴｉＮのいずれかを用いても良い。また、バリア層は、めっきのみならず、スパッタリング等によって形成しても良い。 Next, in the state of FIG. 3 (d), a Ni layer serving as a barrier layer (not shown) is deposited on the entire surface of the semiconductor element mounting surface of the wiring board 10 by electroless plating to a thickness of 1 to 7 μm, preferably about 5 μm. After forming the solder layer 150 thereon by electrolytic plating using the Ni layer as a power feeding layer so that the upper surface is slightly lower than the resist layer 120, the Ni layer exposed to the outside, The resist layer 120 is removed. As a result, the wiring substrate 10 formed so that the solder layer 150 protrudes from the copper oxide film 100 and rises is completed (FIG. 3E).
The barrier layer is for preventing diffusion of copper and gold, and instead of Ni, any of Cr, Ti, TiW, and TiN may be used. The barrier layer may be formed not only by plating but also by sputtering or the like.

次に、図４（ａ）に示すように、電極７０に金からなるスタッドバンプ１１０が形成された半導体素子６０を、配線基板１０に搭載する。この際に、スタッドバンプ１１０とはんだ層１５０の位置合わせを行って、半導体素子６０を配線基板１０の所定の位置に搭載する。半導体素子６０を配線基板１０に実装する際には、はんだの流れ性を抑制するためフラックスを使用しないようにするのがよい。
なお、金からなるスタッドバンプ１１０は、ワイアーボンダーを用いて、金ワイアーを電極７０にボンディングして電極７０上に小球部を形成し、そのまま引き上げ引きちぎるようにして形成することができる。 Next, as shown in FIG. 4A, the semiconductor element 60 in which the stud bump 110 made of gold is formed on the electrode 70 is mounted on the wiring substrate 10. At this time, the stud bump 110 and the solder layer 150 are aligned, and the semiconductor element 60 is mounted at a predetermined position on the wiring board 10. When the semiconductor element 60 is mounted on the wiring board 10, it is preferable not to use flux in order to suppress the flowability of solder.
The stud bump 110 made of gold can be formed by using a wire bonder to bond a gold wire to the electrode 70 to form a small sphere on the electrode 70 and pull it up as it is.

次に、図４（ｂ）に示すように、リフロー法等を用いてはんだ層１５０を溶融させ、はんだによりバンプ８０を形成し、半導体素子６０の電極７０と配線基板の接続端子３０とをバンプ８０を介して一体に接合させる。スタッドバンプ１１０による場合は、溶融したはんだがスタッドバンプ１１０にはい上がり球状に被着するから、接続端子３０から外側にはんだが流れ出さず、ショート不良になりにくいという利点がある。
次いで、半導体素子６０と配線基板１０との間隙部分にアンダーフィル材９０を流入させ、間隙Ａをアンダーフィル材９０で充填して、半導体装置が完成する。 Next, as shown in FIG. 4B, the solder layer 150 is melted by using a reflow method or the like, bumps 80 are formed by solder, and the electrodes 70 of the semiconductor element 60 and the connection terminals 30 of the wiring board are bumped. 80 and are joined together. In the case of the stud bump 110, the melted solder rises onto the stud bump 110 and adheres in a spherical shape. Therefore, there is an advantage that the solder does not flow out from the connection terminal 30 and a short circuit failure is unlikely to occur.
Next, the underfill material 90 is caused to flow into the gap portion between the semiconductor element 60 and the wiring substrate 10, and the gap A is filled with the underfill material 90 to complete the semiconductor device.

本発明に係る配線基板では、半導体素子搭載領域に形成される配線パターン２０をソルダーレジスト層４０によって被覆せず、配線パターン２０の表面にはソルダーレジスト層４０と比較してはるかに薄い銅の酸化膜１００を形成して半導体素子６０をフリップチップ接続によって搭載する構成としたことにより、電極７０の大きさが小さくなりバンプの高さが低くなってきた場合でも、半導体素子６０と配線基板１０との間隙Ａを十分に確保することが可能となり、アンダーフィル部に均一に、ボイド等を発生させることなくアンダーフィル材９０を充填することが容易に可能になる。また、基板が反っているような場合でも、間隙Ａを広く確保できることからオープン不良を防止することが可能となる。   In the wiring board according to the present invention, the wiring pattern 20 formed in the semiconductor element mounting region is not covered with the solder resist layer 40, and the surface of the wiring pattern 20 is oxidized with much thinner copper than the solder resist layer 40. By forming the film 100 and mounting the semiconductor element 60 by flip chip connection, even when the size of the electrode 70 is reduced and the bump height is reduced, the semiconductor element 60 and the wiring substrate 10 The gap A can be sufficiently secured, and the underfill material 90 can be easily filled uniformly in the underfill portion without generating voids or the like. Further, even when the substrate is warped, the gap A can be secured widely, so that open defects can be prevented.

また、配線基板１０の半導体素子搭載面は、アンダーフィル材９０によってほぼ全面が覆われるため、ソルダーレジスト層と同様に、配線パターン２０を外気等から保護することができる。
また、配線パターン２０の表面に形成される銅の酸化膜１００が粗面に形成されることから、酸化膜１００が配線パターン２０とアンダーフィル材９０との密着性を向上させるという作用もある。 In addition, since the semiconductor element mounting surface of the wiring substrate 10 is almost entirely covered with the underfill material 90, the wiring pattern 20 can be protected from the outside air as in the case of the solder resist layer.
In addition, since the copper oxide film 100 formed on the surface of the wiring pattern 20 is formed on a rough surface, the oxide film 100 also has an effect of improving the adhesion between the wiring pattern 20 and the underfill material 90.

また、本発明に係る配線基板によれば、配線パターン２０の表面に形成した銅の酸化膜１００がはんだの流れ性を抑制する作用を有することから、半導体素子６０を接続端子３０にはんだ接合する際に、配線パターン２０上にはんだが流れ出すことを防止し、配線間のショート不良を防止して半導体素子を搭載することができる。   Further, according to the wiring board according to the present invention, the copper oxide film 100 formed on the surface of the wiring pattern 20 has an action of suppressing the flowability of the solder, so that the semiconductor element 60 is soldered to the connection terminal 30. At this time, it is possible to prevent the solder from flowing on the wiring pattern 20 and to prevent a short circuit between the wirings and to mount the semiconductor element.

なお、上述した実施形態において配線パターン２０の表面に酸化膜１００を形成しているのは、配線パターン２０の基材に対して化学的な処理を施すことによって、きわめて薄い電気的な絶縁膜を形成し、酸化膜によって配線パターン２０上におけるはんだの流れ性を抑制させるようにするためである。したがって、酸化膜１００を形成するかわりに、他の化学的処理（絶縁膜形成処理）を配線パターン２０に施すことによって、配線パターン２０の表面に絶縁膜を形成することが可能である。たとえば、銅からなる配線パターン２０にプラズマ処理を利用して配線パターン２０の表面に硫化膜を形成するといったことも可能である。また、配線基板１０に形成する配線パターン２０を構成する金属についても銅以外にアルミニウム等の他の導体金属を利用することができる。   In the above-described embodiment, the oxide film 100 is formed on the surface of the wiring pattern 20 because the substrate of the wiring pattern 20 is chemically treated to form an extremely thin electrical insulating film. This is for forming and suppressing the flowability of the solder on the wiring pattern 20 by the oxide film. Therefore, it is possible to form an insulating film on the surface of the wiring pattern 20 by performing another chemical process (insulating film forming process) on the wiring pattern 20 instead of forming the oxide film 100. For example, it is possible to form a sulfide film on the surface of the wiring pattern 20 by using plasma treatment on the wiring pattern 20 made of copper. Further, as for the metal constituting the wiring pattern 20 formed on the wiring board 10, other conductive metals such as aluminum can be used in addition to copper.

また、上述した実施形態においては、両面に配線パターンが形成された２層の配線基板１０に半導体素子６０を搭載する例について説明したが、３層以上の多層配線基板に半導体素子６０を搭載する場合にも、まったく同様に適用できる。この場合は、多層配線基板で半導体素子６０を搭載する最外層の配線パターンに上述した処理を適用すればよい。また、多層配線基板の形成方法も積層法やビルドアップ法を用いることが可能である。
更に、配線基板の半導体素子非搭載面にも外部接続用の接続端子および外部接続端子等を形成することが可能であり、マザーボード等の他の配線基板等に搭載することも可能である。
また、上記実施形態の半導体装置は、いわゆるチップサイズパッケージとして構成した例を示すが、半導体素子搭載領域の外側に配線パターンを引き出した形式の製品（ファンアウト型）についても同様に適用することができる。 In the above-described embodiment, the example in which the semiconductor element 60 is mounted on the two-layer wiring board 10 having the wiring patterns formed on both sides has been described. However, the semiconductor element 60 is mounted on the multilayer wiring board having three or more layers. The same applies to the case. In this case, the processing described above may be applied to the outermost wiring pattern on which the semiconductor element 60 is mounted on the multilayer wiring board. In addition, the multilayer wiring board can be formed by a lamination method or a build-up method.
Further, a connection terminal for external connection, an external connection terminal, and the like can be formed on the surface of the wiring board on which no semiconductor element is mounted, and can be mounted on another wiring board such as a mother board.
Moreover, although the semiconductor device of the said embodiment shows the example comprised as what is called a chip size package, it can apply similarly also to the product (fan out type) of the type which pulled out the wiring pattern outside the semiconductor element mounting area. it can.

本発明の配線基板および半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the wiring board and semiconductor device of this invention. 本発明に用いる半導体素子の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor element used for this invention. 本発明の配線基板の製造方法の工程説明図である。It is process explanatory drawing of the manufacturing method of the wiring board of this invention. 本発明の半導体装置の製造方法の工程説明図である。It is process explanatory drawing of the manufacturing method of the semiconductor device of this invention. 従来の配線基板および半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional wiring board and semiconductor device.

符号の説明Explanation of symbols

１０ 配線基板
２０ 配線パターン
３０ 接続端子
４０ ソルダーレジスト層
６０ 半導体素子
６５ パッシベーション膜
７０ 電極
８０ バンプ
９０ アンダーフィル材
１００ 銅の酸化膜
１１０ スタッドバンプ
１５０ はんだ層 DESCRIPTION OF SYMBOLS 10 Wiring board 20 Wiring pattern 30 Connection terminal 40 Solder resist layer 60 Semiconductor element 65 Passivation film 70 Electrode 80 Bump 90 Underfill material 100 Copper oxide film 110 Stud bump 150 Solder layer

Claims (8)

フリップチップ接続により半導体素子を搭載する配線基板において、
半導体素子搭載領域に、前記半導体素子と電気的に接続される接続端子を備えた配線パターンが形成され、
該配線パターンは、絶縁膜形成処理が施されて表面に絶縁膜が被覆されるとともに、
前記接続端子が形成された部位については前記絶縁膜が除去されて形成されていることを特徴とする配線基板。 In a wiring board on which a semiconductor element is mounted by flip chip connection,
In the semiconductor element mounting region, a wiring pattern including a connection terminal electrically connected to the semiconductor element is formed,
The wiring pattern is subjected to an insulating film forming process and the surface is covered with an insulating film,
The wiring board characterized in that the insulating film is removed from the portion where the connection terminal is formed. 前記配線パターンが、銅からなり、
前記絶縁膜形成処理として熱酸化処理が施されて、前記配線パターンの表面に酸化膜が形成されていることを特徴とする請求項１記載の配線基板。 The wiring pattern is made of copper,
The wiring substrate according to claim 1, wherein a thermal oxidation process is performed as the insulating film forming process, and an oxide film is formed on a surface of the wiring pattern. 前記配線パターンが、銅からなり、
前記絶縁膜形成処理として黒化処理が施されて、前記配線パターンの表面に酸化膜が形成されていることを特徴とする請求項１記載の配線基板。 The wiring pattern is made of copper,
2. The wiring board according to claim 1, wherein a blackening process is performed as the insulating film forming process, and an oxide film is formed on a surface of the wiring pattern. 前記配線パターンの接続端子に、前記半導体素子の電極と接続端子とを接合するはんだ層が被着形成されていることを特徴とする請求項１〜３のいずれか一項記載の配線基板。   The wiring board according to claim 1, wherein a solder layer for bonding the electrode of the semiconductor element and the connection terminal is formed on the connection terminal of the wiring pattern. 前記配線基板の両面に、基板を貫通して形成された導体層を介して電気的に接続された配線パターンが各々形成され、
前記配線基板の一方の面に半導体素子搭載領域が形成され、
前記配線基板の他方の面のみに、前記配線パターンを被覆するソルダーレジスト層が設けられていることを特徴とする請求項１〜４のいずれか一項記載の配線基板。 A wiring pattern electrically connected via a conductor layer formed through the substrate is formed on both surfaces of the wiring substrate,
A semiconductor element mounting region is formed on one surface of the wiring board,
The wiring board according to claim 1, wherein a solder resist layer that covers the wiring pattern is provided only on the other surface of the wiring board. 前記配線基板の他方の面に形成された配線パターンに、絶縁膜形成処理が施されていることを特徴とする請求項５記載の配線基板。   6. The wiring board according to claim 5, wherein an insulating film forming process is performed on the wiring pattern formed on the other surface of the wiring board. 請求項１〜６のいずれか一項記載の配線基板にフリップチップ接続により半導体素子が搭載された半導体装置であって、
前記半導体素子と前記配線パターンの接続端子とが、バンプを介して電気的に接続され、
前記半導体素子と前記配線基板との間にアンダーフィル材が充填されて、前記半導体素子と配線基板とが一体に接合されていることを特徴とする半導体装置。 A semiconductor device in which a semiconductor element is mounted by flip chip connection on the wiring board according to claim 1,
The semiconductor element and the connection terminal of the wiring pattern are electrically connected via bumps,
An underfill material is filled between the semiconductor element and the wiring board, and the semiconductor element and the wiring board are integrally bonded. 前記半導体素子が、金からなるスタッドバンプが電極に形成されたものであり、該スタッドバンプを介して前記半導体素子と前記接続端子とが電気的に接続されていることを特徴とする請求項７記載の半導体装置。   8. The semiconductor element according to claim 7, wherein a stud bump made of gold is formed on an electrode, and the semiconductor element and the connection terminal are electrically connected via the stud bump. The semiconductor device described.
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JP2015056657A (en) * 2013-09-12 2015-03-23 サムソン エレクトロ−メカニックス カンパニーリミテッド． Printed circuit board and method of manufacturing the same
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