JP2003133357A - Semiconductor device, semiconductor device mounting structure, and connection member for mounting - Google Patents

Semiconductor device, semiconductor device mounting structure, and connection member for mounting

Info

Publication number
JP2003133357A
JP2003133357A JP2001325878A JP2001325878A JP2003133357A JP 2003133357 A JP2003133357 A JP 2003133357A JP 2001325878 A JP2001325878 A JP 2001325878A JP 2001325878 A JP2001325878 A JP 2001325878A JP 2003133357 A JP2003133357 A JP 2003133357A
Authority
JP
Japan
Prior art keywords
mounting
semiconductor device
electrode pattern
pattern portion
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001325878A
Other languages
Japanese (ja)
Inventor
Manabu Kondo
学 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2001325878A priority Critical patent/JP2003133357A/en
Publication of JP2003133357A publication Critical patent/JP2003133357A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29499Shape or distribution of the fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a semiconductor device mounting structure, and a connection member for mounting, which have less damages due to heat or stress for improvement in reliability. SOLUTION: An IC chip 12, having a plurality of protruding electrode sections or bumps 13, is installed on a substrate 11 by flip-chip mounting. The bumps 13 and conductive pattern sections 111 are electrically connected through a connection member 14 intended for flip-chip mounting. In this embodiment, the conductive pattern sections 111 have sharp points on the side of mounting, each having a conical shape. The parts of the bumps 13 on the side of the IC chip 12 are deformed, in matching with the pointed shapes, and have an interlocked connection structure.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、特にフリップチッ
プ実装に係り、接合部の信頼性改善を図る半導体装置、
半導体装置の実装構造、及び実装用接続部材に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to flip chip mounting, and a semiconductor device for improving the reliability of a joint portion,
The present invention relates to a mounting structure of a semiconductor device and a mounting connection member.

【0002】[0002]

【従来の技術】半導体装置の実装は、リードフレームを
利用した製品の実装の他、バンプ等の外部接続端子を利
用して回路基板に接続する製品も多用されている。その
中でも、CSP(Chip Size Package )は、半導体ベア
チップ表面のパッドにバンプを形成し、基板に実装する
構造を有する。従ってCSPは、実装面積が最小限に抑
えられ、実装面の限られた製品、あるいは携帯機器等、
小型化が要求される製品に使用される。
2. Description of the Related Art Semiconductor devices are often mounted by mounting a product using a lead frame or by mounting a product on a circuit board by using external connection terminals such as bumps. Among them, a CSP (Chip Size Package) has a structure in which bumps are formed on pads on the surface of a semiconductor bare chip and are mounted on a substrate. Therefore, the CSP has a small mounting area, and has a limited mounting surface, such as a portable device.
Used for products that require miniaturization.

【0003】図10は、CSPに適用される従来の実装
形態を示す断面図である。実装側となる基板101にI
Cチップ102がフリップチップ実装されている。すな
わち、ICチップ102は複数のバンプを有し、その一
つがバンプ103として示されている。
FIG. 10 is a sectional view showing a conventional mounting mode applied to a CSP. I on the substrate 101 that is the mounting side
The C chip 102 is flip-chip mounted. That is, the IC chip 102 has a plurality of bumps, one of which is shown as the bump 103.

【0004】バンプ103と実装基板101上の導電パ
ターン101pは、例えばACF(異方性導電フィルム
(Anisotropic Conductive Film))が用いられ接合さ
れている。この場合、実装基板101としてはガラスエ
ポキシ等の有機材料のものを用いる場合が多い。
The bump 103 and the conductive pattern 101p on the mounting substrate 101 are joined by using, for example, ACF (Anisotropic Conductive Film). In this case, an organic material such as glass epoxy is often used as the mounting substrate 101.

【0005】[0005]

【発明が解決しようとする課題】上記のようにCSP構
成のICチップ102を実装基板101に搭載する場
合、エポキシ材料等の実装基板101とICチップ10
2を構成するシリコンとの熱膨張率は異なる。矢印F
1,F2は、それぞれ実装基板101とICチップ10
2の熱膨張による応力の大きさの相違を矢印の長さで簡
略的に表している。
When the IC chip 102 having the CSP structure is mounted on the mounting board 101 as described above, the mounting board 101 made of an epoxy material or the like and the IC chip 10 are mounted.
The coefficient of thermal expansion is different from that of silicon that constitutes No. 2. Arrow F
1 and F2 are a mounting substrate 101 and an IC chip 10, respectively.
The difference in the magnitude of stress due to thermal expansion of No. 2 is simply represented by the length of the arrow.

【0006】外部端子(はんだバンプ)103の接続部
は、上述のような応力の影響によって、クラックCRK
を起こす恐れがある。クラックCRKが発生すると、電
気抵抗は増加し、最悪の場合、剥離されオープンになる
などの不具合を招くという問題がある。
The connection portion of the external terminal (solder bump) 103 is cracked by the crack CRK due to the influence of the stress as described above.
May cause When the crack CRK occurs, there is a problem that the electric resistance increases, and in the worst case, a defect such as peeling and opening occurs.

【0007】本発明は上記のような事情を考慮してなさ
れたもので、熱膨張率の違いにより応力が加わるなどし
ても、熱的、応力的なダメージの少ない信頼性を向上さ
せる半導体装置、半導体装置の実装構造、及び実装用接
続部材を提供しようとするものである。
The present invention has been made in consideration of the above circumstances, and is a semiconductor device that improves reliability with little thermal or stress damage even if stress is applied due to a difference in coefficient of thermal expansion. A mounting structure for a semiconductor device and a mounting connection member are provided.

【0008】[0008]

【課題を解決するための手段】本発明の[請求項1]に
係る半導体装置は、半導体集積回路チップ主表面上の突
起電極部と、実装側の電極パターン部とが電気的に接続
される実装形態を含み、前記実装形態に設けられた少な
くとも接着に関する部材と、前記実装側の電極パターン
部が尖鋭形状を有し少なくとも前記チップ側の突起電極
部が尖鋭形状に対し変形され噛合った接続構造と、を具
備したことを特徴とする。
In the semiconductor device according to [Claim 1] of the present invention, the protruding electrode portion on the main surface of the semiconductor integrated circuit chip and the electrode pattern portion on the mounting side are electrically connected. Including a mounting mode, a connection provided at least in the mounting mode and related to bonding, and the electrode pattern section on the mounting side has a sharp shape and at least the protruding electrode section on the chip side is deformed and meshed with the sharp shape. And a structure.

【0009】上記本発明に係る半導体装置によれば、実
装側の電極パターン部が尖鋭形状を有しているので、接
続面積は大きく、かつ噛合いにより接続は強化される。
これにより、応力に対して変形し難い構成となる。
According to the above semiconductor device of the present invention, since the electrode pattern portion on the mounting side has a sharp shape, the connection area is large and the connection is strengthened by the engagement.
As a result, the structure is less likely to be deformed by stress.

【0010】なお、上記電極パターン部における尖鋭形
状は凹凸の繰り返し表面で構成されていてもよい。ま
た、上記接着に関する部材は、異方性導電フィルム、異
方性導電ペースト、絶縁樹脂ペーストのうちから選ばれ
ることを特徴とする。
The sharp shape of the electrode pattern portion may be formed by a surface having repeated irregularities. Further, the member relating to the adhesion is characterized by being selected from an anisotropic conductive film, an anisotropic conductive paste, and an insulating resin paste.

【0011】本発明の[請求項4]に係る半導体装置
は、半導体集積回路チップ主表面上の突起電極部と、実
装側の電極パターン部とが電気的に接続される実装形態
を含み、前記実装形態に設けられた少なくとも接着に関
する部材と、前記接着に関する部材に添加され、前記実
装側の電極パターン部と前記チップ側の突起電極部両者
に噛合う尖鋭形状を有する導電性粒子と、を具備したこ
とを特徴とする。
A semiconductor device according to [Claim 4] of the present invention includes a mounting form in which a protruding electrode portion on a main surface of a semiconductor integrated circuit chip and an electrode pattern portion on a mounting side are electrically connected, At least a member related to adhesion provided in the mounting form, and conductive particles having a sharp shape that is added to the member related to adhesion and meshes with both the electrode pattern portion on the mounting side and the protruding electrode portion on the chip side. It is characterized by having done.

【0012】上記本発明に係る半導体装置によれば、尖
鋭形状を有する導電性粒子が互いの接続部表面に食い込
まれた形態となる。噛合いにより接続は強化される。こ
れにより、応力に対して変形し難い構成となる。なお、
上記接着に関する部材は、異方性導電フィルム、異方性
導電ペーストのうちから選ばれることを特徴とする。
According to the above-mentioned semiconductor device of the present invention, the conductive particles having a sharp shape are bited into the surfaces of the connecting portions. The engagement strengthens the connection. As a result, the structure is less likely to be deformed by stress. In addition,
The member relating to the adhesion is characterized by being selected from an anisotropic conductive film and an anisotropic conductive paste.

【0013】本発明の[請求項6]に係る半導体装置
は、半導体集積回路チップ主表面上の突起電極部と、実
装側の電極パターン部とが電気的に接続される実装形態
を含み、前記実装形態に設けられた少なくとも接着に関
する部材と、前記実装側の電極パターン部と前記チップ
側の突起電極部両者間に設けられた弾性導電ゴムと、を
具備したことを特徴とする。
A semiconductor device according to [Claim 6] of the present invention includes a mounting form in which a protruding electrode portion on a main surface of a semiconductor integrated circuit chip and an electrode pattern portion on a mounting side are electrically connected, It is characterized by comprising at least a member relating to adhesion provided in the mounting form, and an elastic conductive rubber provided between both the electrode pattern section on the mounting side and the protruding electrode section on the chip side.

【0014】上記本発明に係る半導体装置によれば、弾
性導電ゴムによって、応力による接続部のある程度の歪
みには追従する形で、剥離し難く、接合の信頼性向上に
寄与する。なお、上記接着に関する部材は、絶縁樹脂ペ
ーストであることを特徴とする。さらに、上記した発明
に係る半導体装置において、前記電極パターン部のある
実装側は、外部電極を備えたパッケージ用基板であるこ
とを特徴とする。
According to the above-described semiconductor device of the present invention, the elastic conductive rubber follows a certain degree of strain of the connection portion due to stress, is hard to peel off, and contributes to the improvement of reliability of bonding. The member relating to the adhesion is characterized by being an insulating resin paste. Further, in the semiconductor device according to the above-mentioned invention, the mounting side having the electrode pattern portion is a package substrate provided with an external electrode.

【0015】本発明の[請求項9]に係る半導体装置の
実装構造は、半導体集積回路チップ主表面上の突起電極
部と、実装側の電極パターン部との接続を担う部材を設
け、前記突起電極部と電極パターン部とが両者またはい
ずれかの変形を伴ない電気的に接続されることを特徴と
する。
According to a ninth aspect of the present invention, there is provided a semiconductor device mounting structure, wherein a member for connecting a protruding electrode portion on a main surface of a semiconductor integrated circuit chip and an electrode pattern portion on a mounting side is provided, and the protruding portion is provided. It is characterized in that the electrode portion and the electrode pattern portion are electrically connected to each other without any deformation.

【0016】上記変形を伴なわせるため、少なくとも上
記実装側の電極パターン部は円錐形状を有することを特
徴とする。また、少なくとも上記実装側の電極パターン
部が荒れた凹凸の繰り返し表面であることを特徴とす
る。
In order to accompany the above deformation, at least the electrode pattern portion on the mounting side has a conical shape. In addition, at least the electrode pattern portion on the mounting side has a repeating surface of rough irregularities.

【0017】また、上記半導体集積回路チップ主表面上
の突起電極部と、実装側の電極パターン部との接続を担
う部材として、異方性導電フィルム、異方性導電ペース
ト、絶縁樹脂ペースト、弾性導電ゴム、のうちのいずれ
かが用いられていることを特徴とする。
An anisotropic conductive film, an anisotropic conductive paste, an insulating resin paste, an elastic material is used as a member for connecting the protruding electrode portion on the main surface of the semiconductor integrated circuit chip and the electrode pattern portion on the mounting side. One of the conductive rubbers is used.

【0018】本発明の[請求項13]に係る実装用接続
部材は、前記半導体集積回路チップ主表面上の突起電極
部と、実装側の電極パターン部との接続を担う導電性粒
子が添加された部材に関し、前記導電性粒子が任意の尖
鋭形状を有していることを特徴とする。
The mounting connecting member according to [Claim 13] of the present invention is added with conductive particles for connecting the protruding electrode portion on the main surface of the semiconductor integrated circuit chip and the electrode pattern portion on the mounting side. In the above member, the conductive particles have an arbitrary sharp shape.

【0019】上記本発明に係る実装用接続部材によれ
ば、尖鋭形状を有する導電性粒子が互いの接続部表面に
食い込み、噛合うことによって接続は強化される。これ
により、応力に対して変形し難い構成となる。
According to the above-mentioned mounting connecting member of the present invention, the conductive particles having a pointed shape bite into the surfaces of the connecting portions and mesh with each other to strengthen the connection. As a result, the structure is less likely to be deformed by stress.

【0020】[0020]

【発明の実施の形態】図1は、本発明の第1実施形態に
係るCSP(Chip Size Package )に適用される半導体
装置を示す断面図である。実装側となる基板11にIC
チップ12がフリップチップ実装されている。すなわ
ち、ICチップ12は複数の突起電極部つまりバンプ1
3を有する。バンプ13と基板11上の導電パターン部
111とはフリップチップ実装用の接続部材14を介し
て電気的に接続されている。
1 is a sectional view showing a semiconductor device applied to a CSP (Chip Size Package) according to a first embodiment of the present invention. IC on the substrate 11 that is the mounting side
The chip 12 is flip-chip mounted. That is, the IC chip 12 has a plurality of protruding electrode portions, that is, bumps 1.
Have three. The bumps 13 and the conductive pattern portions 111 on the substrate 11 are electrically connected to each other via the connecting members 14 for flip chip mounting.

【0021】この実施形態では、実装側の電極パターン
部111が尖鋭形状を有している。ここでの尖鋭形状は
単独の円錐形状となっている。円錐形状は後付けによっ
て形成してもよい。この尖鋭形状により、少なくともI
Cチップ12側のバンプ13が変形され、噛合った接続
構造を有している。
In this embodiment, the electrode pattern portion 111 on the mounting side has a sharp shape. The sharp shape here is a single conical shape. The conical shape may be formed by retrofitting. Due to this sharp shape, at least I
The bump 13 on the C chip 12 side is deformed to have a meshed connection structure.

【0022】図2(a),(b)は、それぞれ上記図1
の接続構造を説明する要部を拡大した断面図である。例
えば、スタッド型のAuを主成分とするバンプ13と実
装側のCuを主成分とする尖鋭形状の電極パターン部1
11とが、NCP(絶縁樹脂ペースト(Non Conductive
Paste))を介して対向される(図2(a))。その
後、押圧力と熱が加えられ、少なくともバンプ13が、
尖鋭形状の電極パターン部111に対して変形され、噛
み合った接続構造が実現される(図2(b))。
2 (a) and 2 (b) are respectively the above-mentioned FIG.
FIG. 4 is an enlarged cross-sectional view of a main part for explaining the connection structure of FIG. For example, a stud-type bump 13 containing Au as a main component and a sharp electrode pattern portion 1 containing Cu on the mounting side as a main component
11 and NCP (insulating resin paste (Non Conductive
(Paste)) and is opposed (FIG. 2 (a)). After that, pressing force and heat are applied, and at least the bumps 13 are
It is deformed with respect to the electrode pattern portion 111 having a sharp shape, so that a meshed connection structure is realized (FIG. 2B).

【0023】上記フリップチップ実装用の接続部材14
ではNCPが用いられたが、その他の圧接ペーストとし
て、ACP(異方性導電ペースト(Anisotropic Conduc
tivePaste))の代用が考えられる。また、その他には
ACF(異方性導電フィルム(Anisotropic Conductive
Film ))を代用してもよい。
Connection member 14 for flip-chip mounting
NCP was used in, but as another pressure welding paste, ACP (anisotropic conductive paste (Anisotropic Conductor
tivePaste)) can be considered as a substitute. In addition, ACF (Anisotropic Conductive Film)
Film)) may be substituted.

【0024】上記第1実施形態の構成によれば、実装側
の電極パターン部111が尖鋭形状を有しているので、
接続面積は大きく、かつ噛合いにより接続は強化され
る。これにより、応力に対して変形し難い構成となる。
According to the configuration of the first embodiment, since the mounting-side electrode pattern portion 111 has a sharp shape,
The connection area is large and the connection is strengthened by meshing. As a result, the structure is less likely to be deformed by stress.

【0025】図3は、本発明の第2実施形態に係るCS
Pに適用される半導体装置を示す断面図である。前記第
1実施形態と同様の箇所には図1と同様の符号を付して
説明する。実装側となる基板11にICチップ12がフ
リップチップ実装されている。すなわち、ICチップ1
2は複数の突起電極部つまりバンプ13を有する。バン
プ13と基板21上の導電パターン部211とはフリッ
プチップ実装用の接続部材24を介して電気的に接続さ
れている。
FIG. 3 shows a CS according to the second embodiment of the present invention.
It is sectional drawing which shows the semiconductor device applied to P. The same parts as those in the first embodiment will be described with the same reference numerals as those in FIG. The IC chip 12 is flip-chip mounted on the substrate 11 that is the mounting side. That is, the IC chip 1
2 has a plurality of bump electrode portions, that is, bumps 13. The bumps 13 and the conductive pattern portions 211 on the substrate 21 are electrically connected via the connecting members 24 for flip-chip mounting.

【0026】この実施形態では、実装側の電極パターン
部211が凹凸の繰り返し表面で構成される尖鋭形状を
有している。この尖鋭形状は物理的なブラスト処理やホ
ーニング処理、スパッタ法による処理、その他の処理に
よって達成される。これにより、少なくともICチップ
12側のバンプ13がこの尖鋭形状に対し変形され、噛
合った接続構造を有している。
In this embodiment, the electrode pattern portion 211 on the mounting side has a sharp shape constituted by repeated surfaces of irregularities. This sharp shape is achieved by physical blasting, honing, sputtering, or other processing. As a result, at least the bumps 13 on the IC chip 12 side are deformed with respect to this sharp shape, and have a connection structure in which they mesh with each other.

【0027】図4(a),(b)は、それぞれ上記図3
の接続構造を説明する要部を拡大した断面図である。例
えば、スタッド型のAuを主成分とするバンプ13と実
装側のCuを主成分とする凹凸の繰り返しによる尖鋭形
状の電極パターン部211とが、ACF(異方性導電フ
ィルム)を介して対向される(図4(a))。その後、
押圧力と熱が加えられ、少なくともバンプ13が、尖鋭
形状の電極パターン部211に対して変形され、噛み合
った接続構造が実現される(図4(b))。
FIGS. 4 (a) and 4 (b) are respectively shown in FIG.
FIG. 4 is an enlarged cross-sectional view of a main part for explaining the connection structure of FIG. For example, the stud-type bump 13 containing Au as a main component and the electrode pattern portion 211 having a sharp shape formed by repeating the unevenness containing Cu as a main component on the mounting side are opposed to each other via an ACF (anisotropic conductive film). (FIG. 4 (a)). afterwards,
Pressing force and heat are applied, and at least the bump 13 is deformed with respect to the sharp electrode pattern portion 211, and a meshed connection structure is realized (FIG. 4B).

【0028】上記フリップチップ実装用の接続部材24
としてはACFが用いられたが、その他の圧接ペースト
として、ACP(異方性導電ペースト)の使用が考えら
れる。
Connection member 24 for flip-chip mounting
Although ACF was used as the above, it is conceivable to use ACP (anisotropic conductive paste) as another pressure-bonding paste.

【0029】上記第2実施形態の構成によれば、実装側
の電極パターン部111が凹凸の繰り返し表面で構成さ
れた複数の尖鋭形状を有している。これにより、接続面
積は大きく、かつ噛合いにより接続は強化され、応力に
対して変形し難い構成となる。また、導電粒子の捕捉率
が向上する利点もある。
According to the configuration of the second embodiment described above, the electrode pattern portion 111 on the mounting side has a plurality of sharpened shapes each having a repetitive uneven surface. As a result, the connection area is large, and the connection is strengthened by meshing, which makes it difficult to deform due to stress. There is also an advantage that the capture rate of the conductive particles is improved.

【0030】図5は、本発明の第3実施形態に係るCS
Pに適用される半導体装置を示す断面図である。前記第
1実施形態と同様の箇所には図1と同様の符号を付して
説明する。実装側となる基板11にICチップ12がフ
リップチップ実装されている。すなわち、ICチップ1
2は複数の突起電極部つまりバンプ13を有する。バン
プ13と基板31上の導電パターン部311とはフリッ
プチップ実装用の接続部材34を介して電気的に接続さ
れている。
FIG. 5 shows a CS according to the third embodiment of the present invention.
It is sectional drawing which shows the semiconductor device applied to P. The same parts as those in the first embodiment will be described with the same reference numerals as those in FIG. The IC chip 12 is flip-chip mounted on the substrate 11 that is the mounting side. That is, the IC chip 1
2 has a plurality of bump electrode portions, that is, bumps 13. The bumps 13 and the conductive pattern portions 311 on the substrate 31 are electrically connected via the flip-chip mounting connection members 34.

【0031】この実施形態では、接続部材34中の導電
粒子が任意の尖鋭形状を有している。これにより、IC
チップ12側のバンプ13、実装側の電極パターン部3
11両者の表面に導電粒子が食い込み、噛合った接続構
造を実現している。
In this embodiment, the conductive particles in the connecting member 34 have an arbitrary sharp shape. This allows the IC
The bump 13 on the chip 12 side, the electrode pattern portion 3 on the mounting side
11 Conductive particles dig into the surfaces of both to realize a meshed connection structure.

【0032】図6(a),(b)は、それぞれ上記図5
の接続構造を説明する要部を拡大した断面図である。例
えば、スタッド型のAuを主成分とするバンプ13と実
装側のCuを主成分とする電極パターン部311とが、
ACF(異方性導電フィルム)を介して対向される(図
6(a))。その後、押圧力と熱が加えられ、バンプ1
3と電極パターン部311両者の表面に導電粒子がくさ
びのように食い込み、噛合った接続構造が実現される
(図6(b))。
FIGS. 6 (a) and 6 (b) are respectively shown in FIG.
FIG. 4 is an enlarged cross-sectional view of a main part for explaining the connection structure of FIG. For example, the stud-type bump 13 mainly composed of Au and the electrode pattern portion 311 mainly composed of Cu on the mounting side are
It is opposed via an ACF (anisotropic conductive film) (FIG. 6A). After that, pressing force and heat are applied to the bump 1
3 and the electrode pattern portion 311 both have conductive particles that bite like a wedge, and a meshed connection structure is realized (FIG. 6B).

【0033】上記フリップチップ実装用の接続部材34
としては導電粒子を尖鋭形状としたACF用いられた
が、その他、圧接ペーストとしてACP(異方性導電ペ
ースト)の導電粒子を尖鋭形状とする仕様が考えられ
る。
Connection member 34 for flip-chip mounting
As the ACF, conductive particles having a sharpened shape were used as the above, but in addition, a specification in which the conductive particles of ACP (anisotropic conductive paste) as a pressure-bonding paste have a sharpened shape can be considered.

【0034】上記第3実施形態の構成によれば、フリッ
プチップ実装用の接続部材34中の導電粒子が尖鋭形状
を有しているので、バンプ13と電極パターン部311
両者の噛合いにより接続は強化される。これにより、応
力に対して変形し難い構成となる。
According to the structure of the third embodiment, since the conductive particles in the flip-chip mounting connection member 34 have a sharp shape, the bump 13 and the electrode pattern portion 311 are formed.
The connection is strengthened by the engagement of both. As a result, the structure is less likely to be deformed by stress.

【0035】なお、電極パターン部311の他、前記第
2実施形態で示した凹凸の繰り返しによる尖鋭形状の電
極パターン部211が用いられていてもよい。これによ
り、いっそうの導電粒子の捕捉率向上が期待できる。
In addition to the electrode pattern portion 311, an electrode pattern portion 211 having a sharp shape by repeating the unevenness shown in the second embodiment may be used. This can be expected to further improve the capture rate of the conductive particles.

【0036】図7は、本発明の第4実施形態に係るCS
Pに適用される半導体装置を示す断面図である。前記第
1実施形態と同様の箇所には図1と同様の符号を付して
説明する。実装側となる基板11にICチップ12がフ
リップチップ実装されている。すなわち、ICチップ1
2は複数の突起電極部つまりバンプ13を有する。バン
プ13と基板11上の導電パターン部411とはフリッ
プチップ実装用の弾性導電ゴム44を介して電気的に接
続されている。基板11上のフリップチップ実装間には
接着保護部材などが設けられていてもよい。
FIG. 7 shows a CS according to the fourth embodiment of the present invention.
It is sectional drawing which shows the semiconductor device applied to P. The same parts as those in the first embodiment will be described with the same reference numerals as those in FIG. The IC chip 12 is flip-chip mounted on the substrate 11 that is the mounting side. That is, the IC chip 1
2 has a plurality of bump electrode portions, that is, bumps 13. The bumps 13 and the conductive pattern portion 411 on the substrate 11 are electrically connected via the elastic conductive rubber 44 for flip-chip mounting. An adhesive protection member or the like may be provided between the flip chip mountings on the substrate 11.

【0037】この実施形態では、例えばカーボンの入っ
た弾性導電ゴム44を接続部材として用いる。これによ
り、ICチップ12側のバンプ13、実装側の電極パタ
ーン部411両者の表面に弾性導電ゴム44が接着し、
応力に強い接続構造を有している。つまり、弾性導電ゴ
ム44によって、応力による接続部のある程度の歪みに
は追従する形になっている。これにより、剥離し難く、
接合の信頼性向上に寄与する。
In this embodiment, the elastic conductive rubber 44 containing carbon, for example, is used as the connecting member. As a result, the elastic conductive rubber 44 adheres to the surfaces of both the bump 13 on the IC chip 12 side and the electrode pattern portion 411 on the mounting side,
It has a stress-resistant connection structure. That is, the elastic conductive rubber 44 is configured to follow a certain amount of strain of the connection portion due to stress. This makes it difficult to peel off,
It contributes to the improvement of the reliability of joining.

【0038】図8(a),(b)は、それぞれ上記図7
の接続構造を説明する要部を拡大した断面図である。例
えば、実装側のCuを主成分とする電極パターン部41
1の所定部(またはスタッド型のAuを主成分とするバ
ンプ13)に弾性導電ゴム44が付与される(図8
(a))。その後、押圧力と熱が加えられ、バンプ13
と電極パターン部311間に弾性導電ゴム44が定着さ
れ応力に追従する接続構造が実現される(図8
(b))。
FIGS. 8 (a) and 8 (b) are respectively shown in FIG.
FIG. 4 is an enlarged cross-sectional view of a main part for explaining the connection structure of FIG. For example, the electrode pattern portion 41 whose main component is Cu on the mounting side
Elastic conductive rubber 44 is applied to a predetermined portion of No. 1 (or bump 13 having stud type Au as a main component) (FIG. 8).
(A)). Then, pressing force and heat are applied to the bumps 13
The elastic conductive rubber 44 is fixed between the electrode and the electrode pattern portion 311 to realize a connection structure that follows the stress (FIG. 8).
(B)).

【0039】上記フリップチップ実装用の弾性導電ゴム
44と併用してNCP(絶縁性樹脂ペースト)を設ける
仕様が考えられる。また、電極パターン部411の他、
前記第2実施形態で示した凹凸の繰り返しによる尖鋭形
状の電極パターン部211が用いられていてもよい。こ
れにより、弾性導電ゴム44の接着率向上が期待でき
る。
It is conceivable to provide NCP (insulating resin paste) in combination with the elastic conductive rubber 44 for flip chip mounting. In addition to the electrode pattern portion 411,
The electrode pattern portion 211 having a sharp shape by repeating the unevenness shown in the second embodiment may be used. This can be expected to improve the adhesion rate of the elastic conductive rubber 44.

【0040】上記第4実施形態の構成によれば、ICチ
ップ12側のバンプ13、実装側の電極パターン部41
1両者の表面に弾性導電ゴム44が接着し、応力に強い
接続構造を有している。応力による接続部のある程度の
歪みに対して、弾性導電ゴム44は柔軟に追従し、剥離
し難く、接合の信頼性は向上する。
According to the configuration of the fourth embodiment, the bump 13 on the IC chip 12 side and the electrode pattern portion 41 on the mounting side are provided.
1. The elastic conductive rubber 44 is adhered to the surface of both of them and has a connection structure that is resistant to stress. The elastic conductive rubber 44 flexibly follows a certain amount of strain of the connection portion due to stress, is hard to be peeled off, and the reliability of bonding is improved.

【0041】上記各実施形態によれば、実装側の電極パ
ターン部(111または211)が尖鋭形状を有して、
接続面積を大きくし、かつ変形により接続部を噛合わせ
る。また、接続部材(34)に挟み込まれる導電粒子を
尖鋭形状とするなど噛合いにより接続は強化される。こ
れにより、応力に対して変形し難い構成が得られる。あ
るいは、接続部に弾性導電ゴム(44)を挟む込むこと
によって、応力による接続部のある程度の歪みには追従
する形で、剥離し難く、接合の信頼性向上に寄与する構
成が得られる。
According to each of the above embodiments, the electrode pattern portion (111 or 211) on the mounting side has a sharp shape,
The connection area is enlarged and the connection parts are meshed by deformation. In addition, the connection is strengthened by meshing such that the conductive particles sandwiched between the connection members (34) have a sharp shape. This makes it possible to obtain a structure that is unlikely to be deformed by stress. Alternatively, by sandwiching the elastic conductive rubber (44) in the connection portion, it is possible to obtain a structure in which peeling is less likely to occur and the joining reliability is improved by following a certain degree of distortion of the connection portion due to stress.

【0042】なお、各図において実装側となる基板11
〜41は、ガラスエポキシ系などの回路基板であった
り、CSPを構成するための、外部端子(例えばボール
電極)を有するベース基板であってもよい(図9参
照)。
The board 11 on the mounting side in each drawing
˜41 may be a glass epoxy type circuit board or a base board having external terminals (for example, ball electrodes) for forming a CSP (see FIG. 9).

【0043】[0043]

【発明の効果】以上説明したように本発明によれば、接
続部の噛合いを重視することにより、応力に対して変形
し難い構成を得る。あるいは、接続部の柔軟な追従性を
もって応力による接続部の歪みに対処し、剥離し難く、
接合の信頼性を向上させる構成を得る。この結果、熱膨
張率の違いにより応力が加わるなどしても、熱的、応力
的なダメージの少ない信頼性を向上させる半導体装置、
半導体装置の実装構造、及び実装用接続部材を提供する
ことができる。
As described above, according to the present invention, by emphasizing the meshing of the connecting portion, it is possible to obtain a structure which is not easily deformed by stress. Alternatively, the flexible followability of the connection part can handle the distortion of the connection part due to stress, making it difficult to peel off,
A structure that improves the reliability of bonding is obtained. As a result, even if stress is applied due to the difference in coefficient of thermal expansion, a semiconductor device that improves reliability with less thermal and stress damage,
A mounting structure for a semiconductor device and a mounting connection member can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施形態に係るCSP(Chip Siz
e Package )に適用される半導体装置を示す断面図であ
る。
FIG. 1 shows a CSP (Chip Siz) according to a first embodiment of the present invention.
It is sectional drawing which shows the semiconductor device applied to e Package.

【図2】(a),(b)は、それぞれ図1の接続構造を
説明する要部を拡大した断面図である。
2 (a) and 2 (b) are enlarged cross-sectional views each illustrating a connection structure of FIG.

【図3】本発明の第2実施形態に係るCSPに適用され
る半導体装置を示す断面図である。
FIG. 3 is a cross-sectional view showing a semiconductor device applied to a CSP according to a second exemplary embodiment of the present invention.

【図4】(a),(b)は、それぞれ図3の接続構造を
説明する要部を拡大した断面図である。
4 (a) and 4 (b) are enlarged cross-sectional views of main parts for explaining the connection structure of FIG.

【図5】本発明の第3実施形態に係るCSPに適用され
る半導体装置を示す断面図である。
FIG. 5 is a sectional view showing a semiconductor device applied to a CSP according to a third embodiment of the present invention.

【図6】(a),(b)は、それぞれ図5の接続構造を
説明する要部を拡大した断面図である。
6 (a) and 6 (b) are enlarged cross-sectional views each illustrating a connection structure of FIG.

【図7】本発明の第4実施形態に係るCSPに適用され
る半導体装置を示す断面図である。
FIG. 7 is a sectional view showing a semiconductor device applied to a CSP according to a fourth embodiment of the present invention.

【図8】(a),(b)は、それぞれ図7の接続構造を
説明する要部を拡大した断面図である。
8 (a) and 8 (b) are enlarged cross-sectional views each illustrating a connection structure of FIG. 7.

【図9】CSPに適用される従来の実装形態を示す断面
図である。
FIG. 9 is a cross-sectional view showing a conventional mounting mode applied to a CSP.

【図10】CSPに適用される従来の実装形態を示す断
面図である。
FIG. 10 is a cross-sectional view showing a conventional mounting mode applied to a CSP.

【符号の説明】[Explanation of symbols]

11,21,31,41…基板 111,211,311,411…導電パターン部(接
続ポイント) 12…ICチップ 13…バンプ 14,24,34…接続部材 44…弾性導電ゴム
11,21,31,41 ... Substrates 111, 211, 311, 411 ... Conductive pattern portion (connection point) 12 ... IC chip 13 ... Bumps 14, 24, 34 ... Connection member 44 ... Elastic conductive rubber

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路チップ主表面上の突起電
極部と、実装側の電極パターン部とが電気的に接続され
る実装形態を含み、 前記実装形態に設けられた少なくとも接着に関する部材
と、 前記実装側の電極パターン部が尖鋭形状を有し少なくと
も前記チップ側の突起電極部が尖鋭形状に対し変形され
噛合った接続構造と、を具備したことを特徴とする半導
体装置。
1. A mounting mode in which a protruding electrode section on a main surface of a semiconductor integrated circuit chip and an electrode pattern section on a mounting side are electrically connected to each other, and a member provided in the mounting mode and at least relating to adhesion, A semiconductor device comprising: a connection structure in which the electrode pattern portion on the mounting side has a sharp shape and at least the protruding electrode portion on the chip side is deformed and meshed with the sharp shape.
【請求項2】 前記電極パターン部における尖鋭形状は
凹凸の繰り返し表面で構成されていることを特徴とする
請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the pointed shape of the electrode pattern portion is formed by a repeating surface of irregularities.
【請求項3】 前記接着に関する部材は、異方性導電フ
ィルム、異方性導電ペースト、絶縁樹脂ペーストのうち
から選ばれることを特徴とする請求項1または2記載の
半導体装置。
3. The semiconductor device according to claim 1, wherein the member relating to adhesion is selected from an anisotropic conductive film, an anisotropic conductive paste, and an insulating resin paste.
【請求項4】 半導体集積回路チップ主表面上の突起電
極部と、実装側の電極パターン部とが電気的に接続され
る実装形態を含み、 前記実装形態に設けられた少なくとも接着に関する部材
と、 前記接着に関する部材に添加され、前記実装側の電極パ
ターン部と前記チップ側の突起電極部両者に噛合う尖鋭
形状を有する導電性粒子と、を具備したことを特徴とす
る半導体装置。
4. A mounting mode in which a protruding electrode section on a main surface of a semiconductor integrated circuit chip and an electrode pattern section on a mounting side are electrically connected to each other, and a member provided at least in the mounting mode and relating to adhesion, A semiconductor device, comprising: a conductive particle having a sharp shape, which is added to the member for adhesion and meshes with both the electrode pattern portion on the mounting side and the protruding electrode portion on the chip side.
【請求項5】 前記接着に関する部材は、異方性導電フ
ィルム、異方性導電ペーストのうちから選ばれることを
特徴とする請求項1または2記載の半導体装置。
5. The semiconductor device according to claim 1, wherein the member relating to adhesion is selected from an anisotropic conductive film and an anisotropic conductive paste.
【請求項6】 半導体集積回路チップ主表面上の突起電
極部と、実装側の電極パターン部とが電気的に接続され
る実装形態を含み、 前記実装形態に設けられた少なくとも接着に関する部材
と、前記実装側の電極パターン部と前記チップ側の突起
電極部両者間に設けられた弾性導電ゴムと、を具備した
ことを特徴とする半導体装置。
6. A mounting mode in which a protruding electrode section on a main surface of a semiconductor integrated circuit chip and an electrode pattern section on a mounting side are electrically connected to each other, and a member provided in the mounting mode and at least relating to adhesion, A semiconductor device comprising: an electrode pattern portion on the mounting side and an elastic conductive rubber provided between both the protruding electrode portions on the chip side.
【請求項7】 前記接着に関する部材は、絶縁樹脂ペー
ストであることを特徴とする請求項6記載の半導体装
置。
7. The semiconductor device according to claim 6, wherein the member relating to the adhesion is an insulating resin paste.
【請求項8】 前記電極パターン部のある実装側は、外
部電極を備えたパッケージ用基板であることを特徴とす
る請求項1〜7いずれか一つに記載の半導体装置。
8. The semiconductor device according to claim 1, wherein the mounting side having the electrode pattern portion is a package substrate including an external electrode.
【請求項9】 半導体集積回路チップ主表面上の突起電
極部と、実装側の電極パターン部との接続を担う部材を
設け、前記突起電極部と電極パターン部とが両者または
いずれかの変形を伴ない電気的に接続されることを特徴
とする半導体装置の実装構造。
9. A member for connecting a protruding electrode portion on a main surface of a semiconductor integrated circuit chip and an electrode pattern portion on a mounting side is provided, and the protruding electrode portion and the electrode pattern portion are deformed in both or one of them. A semiconductor device mounting structure, characterized in that they are electrically connected together.
【請求項10】 少なくとも前記実装側の電極パターン
部は円錐形状を有することを特徴とする請求項9記載の
半導体装置の実装構造。
10. The mounting structure for a semiconductor device according to claim 9, wherein at least the electrode pattern portion on the mounting side has a conical shape.
【請求項11】 少なくとも前記実装側の電極パターン
部が荒れた凹凸の繰り返し表面であることを特徴とする
請求項9記載の半導体装置。
11. The semiconductor device according to claim 9, wherein at least the electrode pattern portion on the mounting side has a repeating surface of rough irregularities.
【請求項12】 前記半導体集積回路チップ主表面上の
突起電極部と、実装側の電極パターン部との接続を担う
部材として、異方性導電フィルム、異方性導電ペース
ト、絶縁樹脂ペースト、弾性導電ゴム、のうちのいずれ
かが用いられていることを特徴とする請求項9〜11い
ずれか一つに記載の半導体装置の実装構造。
12. An anisotropic conductive film, an anisotropic conductive paste, an insulating resin paste, an elastic material, which serves as a member for connecting the bump electrode portion on the main surface of the semiconductor integrated circuit chip and the electrode pattern portion on the mounting side. 12. The mounting structure for a semiconductor device according to claim 9, wherein any one of conductive rubbers is used.
【請求項13】 前記半導体集積回路チップ主表面上の
突起電極部と、実装側の電極パターン部との接続を担う
導電性粒子が添加された部材に関し、前記導電性粒子が
任意の尖鋭形状を有していることを特徴とする実装用接
続部材。
13. A member to which conductive particles for connecting the protruding electrode portion on the main surface of the semiconductor integrated circuit chip and the electrode pattern portion on the mounting side are added, wherein the conductive particle has an arbitrary sharp shape. A mounting connection member having.
JP2001325878A 2001-10-24 2001-10-24 Semiconductor device, semiconductor device mounting structure, and connection member for mounting Withdrawn JP2003133357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001325878A JP2003133357A (en) 2001-10-24 2001-10-24 Semiconductor device, semiconductor device mounting structure, and connection member for mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001325878A JP2003133357A (en) 2001-10-24 2001-10-24 Semiconductor device, semiconductor device mounting structure, and connection member for mounting

Publications (1)

Publication Number Publication Date
JP2003133357A true JP2003133357A (en) 2003-05-09

Family

ID=19142355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001325878A Withdrawn JP2003133357A (en) 2001-10-24 2001-10-24 Semiconductor device, semiconductor device mounting structure, and connection member for mounting

Country Status (1)

Country Link
JP (1) JP2003133357A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005069364A1 (en) * 2004-01-13 2005-07-28 Matsushita Electric Industrial Co., Ltd. Mounted board, electronic component mounting method, electronic component, and wiring board
JP2006237151A (en) * 2005-02-23 2006-09-07 Shinko Electric Ind Co Ltd Wiring board and semiconductor apparatus
JP2010010586A (en) * 2008-06-30 2010-01-14 Dainippon Printing Co Ltd Flip-connection package and method of manufacturing flip-connection package
KR101225104B1 (en) 2011-05-27 2013-01-24 서울과학기술대학교 산학협력단 Bonding method for flip chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005069364A1 (en) * 2004-01-13 2005-07-28 Matsushita Electric Industrial Co., Ltd. Mounted board, electronic component mounting method, electronic component, and wiring board
JP2006237151A (en) * 2005-02-23 2006-09-07 Shinko Electric Ind Co Ltd Wiring board and semiconductor apparatus
JP2010010586A (en) * 2008-06-30 2010-01-14 Dainippon Printing Co Ltd Flip-connection package and method of manufacturing flip-connection package
KR101225104B1 (en) 2011-05-27 2013-01-24 서울과학기술대학교 산학협력단 Bonding method for flip chip

Similar Documents

Publication Publication Date Title
JP3603890B2 (en) Electronic device, method of manufacturing the same, and electronic apparatus
US7638876B2 (en) Bumpless semiconductor device
EP1011141A3 (en) Semiconductor device and process for producing it
JP2817704B2 (en) Tape carrier package and connection method
JP2001068621A (en) Semiconductor device and its manufacture
US6414397B1 (en) Anisotropic conductive film, method of mounting semiconductor chip, and semiconductor device
JPH0927516A (en) Connection structure of electronic component
EP3590133B1 (en) Flexible conductive bonding
JP2003133357A (en) Semiconductor device, semiconductor device mounting structure, and connection member for mounting
KR100366409B1 (en) conductor and flip chip structure having the same
JP2002026071A (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
JP3743716B2 (en) Flexible wiring board and semiconductor element mounting method
TW529137B (en) Semiconductor device
JPH0669278A (en) Connecting method for semiconductor element
JP2002261416A (en) Connection structure of electrode
JP2003152021A (en) Semiconductor device and method for manufacturing the same, circuit board, and electronic equipment
KR100833937B1 (en) Anisotropic conductive adhesive
JP3446608B2 (en) Semiconductor unit
JP2003243821A (en) Method of connecting wiring board and wiring board
JP2967560B2 (en) Connection structure of film carrier
JPH1116946A (en) Mounting method of semiconductor device
JP3598058B2 (en) Circuit board
JP2000012613A (en) Anisotropic conductive adhesive, and method of mounting electronic parts
JP2004214373A (en) Semiconductor device with bumps and its packaging method
JP2000208907A (en) Mounting method for electronic component

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20050104