JPH1116946A - Mounting method of semiconductor device - Google Patents
Mounting method of semiconductor deviceInfo
- Publication number
- JPH1116946A JPH1116946A JP9163736A JP16373697A JPH1116946A JP H1116946 A JPH1116946 A JP H1116946A JP 9163736 A JP9163736 A JP 9163736A JP 16373697 A JP16373697 A JP 16373697A JP H1116946 A JPH1116946 A JP H1116946A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- bump
- circuit board
- conductive particles
- pressing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置と回路
基板とを電気的機械的に接続する半導体装置の実装方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting method for electrically and mechanically connecting a semiconductor device and a circuit board.
【０００２】[0002]
【従来の技術】近年、ハンドヘルドＰＣ，携帯電話，Ｐ
ＨＳ，ＰＤＡ等の携帯情報端末機器、またムービ，カメ
ラなどの携帯映像機器などにおいて高密度実装が益々求
められている。これに対応するため、半導体装置の実装
は従来のパッケージ品を実装する方法から、半導体装置
を直接回路基板に実装する方式が主流になりつつある。2. Description of the Related Art In recent years, handheld PCs, mobile phones, P
High-density packaging is increasingly required for portable information terminal devices such as HS and PDA, and portable video devices such as movies and cameras. In order to cope with this, the method of mounting a semiconductor device directly on a circuit board is becoming the mainstream, instead of the method of mounting a conventional package product.
【０００３】回路基板上に半導体装置を直接実装する方
法として、接続材料に異方性導電膜を用いた実装方法が
ある。As a method of directly mounting a semiconductor device on a circuit board, there is a mounting method using an anisotropic conductive film as a connection material.
【０００４】図１に示すようにこの異方性導電膜９は、
熱硬化性または熱可塑性の絶縁性接着樹脂１０の中に、
直径５〜１０μmの導電粒子７を分散させたものであ
る。導電粒子７には外面に絶縁被膜が施されたものもあ
る。As shown in FIG. 1, this anisotropic conductive film 9
In the thermosetting or thermoplastic insulating adhesive resin 10,
It is obtained by dispersing conductive particles 7 having a diameter of 5 to 10 μm. Some conductive particles 7 have an outer surface coated with an insulating film.
【０００５】初めに、回路基板１２の電極１１上に異方
性導電膜９を貼り付ける。次に、半導体装置１のアルミ
電極２上に、公知のメッキ技術によりメッキバンプ１３
または公知のワイヤボンディング技術によりスタッドバ
ンプを形成し、次いで、前記バンプ１３を形成した半導
体装置１を前記回路基板１２上に位置合わせする。最後
に前記半導体装置１を前記回路基板１２に押圧し加熱し
て前記異方性導電膜９を硬化する。加圧により対向する
電極は導電粒子８を介して電気的に接続される。非電極
部には圧力が加えられないため導電粒子７は接触せず、
絶縁性が保たれる。[0005] First, the anisotropic conductive film 9 is attached on the electrode 11 of the circuit board 12. Next, a plating bump 13 is formed on the aluminum electrode 2 of the semiconductor device 1 by a known plating technique.
Alternatively, a stud bump is formed by a known wire bonding technique, and then the semiconductor device 1 on which the bump 13 is formed is positioned on the circuit board 12. Finally, the semiconductor device 1 is pressed against the circuit board 12 and heated to cure the anisotropic conductive film 9. The opposing electrodes are electrically connected via the conductive particles 8 by pressurization. Since no pressure is applied to the non-electrode portion, the conductive particles 7 do not contact,
Insulation is maintained.
【０００６】[0006]
【発明が解決しようとする課題】上記の従来例では、メ
ッキバンプ１３の角が図１に示すような曲面になってい
ること等により、絶縁性接着樹脂１０と導電粒子７と
が、メッキバンプ１３の平面部と回路基板１２上の電極
１１との間から流れ出てしまい、メッキバンプ１３の平
面部と回路基板１２上の電極１１との間には、僅かな導
電粒子７しか残らず、導電粒子密度が低い場合には導電
粒子７が全くない電極も発生する。このような場合、電
気的接続不良が発生するという問題がある。In the above conventional example, the corners of the plating bumps 13 are curved as shown in FIG. 13 flows out from between the flat portion of the circuit board 12 and the electrode 11 on the circuit board 12, and only a small amount of conductive particles 7 remain between the flat portion of the plating bump 13 and the electrode 11 on the circuit board 12. When the particle density is low, an electrode having no conductive particles 7 may be generated. In such a case, there is a problem that an electrical connection failure occurs.
【０００７】一方、導電粒子密度を大きくすると、隣接
電極間で短絡が発生するという問題がある。On the other hand, when the density of the conductive particles is increased, there is a problem that a short circuit occurs between adjacent electrodes.
【０００８】また図２に示すようにワイヤバンプ方式で
金バンプ１４を形成した場合にも、メッキバンプと同様
に粒子捕捉効率が悪い問題があると同時に、ワイヤバン
プ形成装置の精度の限界から、バンプ１個を形成する毎
に平坦化を行っても導電粒子７の直径以上の高さばらつ
きがある。このような高さばらつきの大きい金バンプ１
４が形成された半導体装置１を回路基板１２に実装して
も、全ての金バンプ１４を均一に接続することが困難と
なり、電気的接続不良が発生するという問題がある。Further, as shown in FIG. 2, when the gold bumps 14 are formed by the wire bump method, there is a problem that the particle trapping efficiency is low as in the case of the plated bumps, and at the same time, the bumps 1 are formed due to the limit of the accuracy of the wire bump forming apparatus. Even if flattening is performed each time a piece is formed, there is a height variation equal to or larger than the diameter of the conductive particles 7. Gold bump 1 having such a large height variation
Even if the semiconductor device 1 on which the semiconductor device 4 is formed is mounted on the circuit board 12, it is difficult to uniformly connect all the gold bumps 14, and there is a problem that an electrical connection failure occurs.
【０００９】本発明は上記の従来法における課題を解決
した半導体装置の実装方法を提供することにある。An object of the present invention is to provide a method of mounting a semiconductor device which solves the above-mentioned problems in the conventional method.
【００１０】[0010]
【課題を解決するための手段】上記従来の課題を解決す
る本発明の方法は、 （１）半導体装置にワイヤバンプ形成装置によりバンプ
を形成する。The method of the present invention for solving the above-mentioned conventional problems is as follows: (1) A bump is formed on a semiconductor device by a wire bump forming apparatus.
【００１１】（２）バンプよりも硬い材料よりなる平坦
な金属板（押圧用基板）に、異方性導電膜の導電粒子の
直径より少し小さい凹部又は凸部を形成しておく。(2) Concave portions or convex portions slightly smaller than the diameter of the conductive particles of the anisotropic conductive film are formed on a flat metal plate (pressing substrate) made of a material harder than the bumps.
【００１２】（３）半導体装置のバンプ先端面に前記金
属板の凹凸面を押しつけることによりバンプ先端面に均
一な凹凸部を形成する。(3) A uniform uneven portion is formed on the bump tip surface by pressing the uneven surface of the metal plate against the bump tip surface of the semiconductor device.
【００１３】（４）回路基板上に異方性導電膜を貼り付
け、半導体装置を回路基板に押圧し加熱して異方性導電
膜を硬化する。(4) An anisotropic conductive film is attached on the circuit board, and the semiconductor device is pressed against the circuit board and heated to cure the anisotropic conductive film.
【００１４】この方法は、バンプ先端面を押圧用基板で
平坦化しているので、半導体装置を回路基板に加圧した
場合に、従来方式の問題点であった、バンプ高さばらつ
きに起因する電気的接続不良発生の問題点を解決でき
る。In this method, since the tip end surface of the bump is flattened by the pressing substrate, when the semiconductor device is pressed against the circuit board, the electric current caused by the bump height variation, which is a problem of the conventional method, is obtained. Can solve the problem of poor connection.
【００１５】また押圧用基板によりバンプ先端面には、
異方性導電膜の導電粒子の直径より少し小さい均一な凹
凸部が形成されているので、半導体装置を回路基板に加
圧した場合に、導電粒子が凹部に確実に捕捉され、電気
的接合の信頼性が更に向上し、従来の問題点を解決でき
る。[0015] Further, the tip of the bump is pressed by the pressing substrate.
Since a uniform uneven portion slightly smaller than the diameter of the conductive particles of the anisotropic conductive film is formed, when the semiconductor device is pressed against the circuit board, the conductive particles are reliably trapped in the concave portions, and the electrical connection is reduced. Reliability is further improved, and the conventional problems can be solved.
【００１６】[0016]
【発明の実施の形態】本発明による一実施例を図を用い
て説明する。図３に示すように大きさが８．０×８．０
mmの半導体装置１のアルミ電極２（１０５×１０５μ
m，１３０μmピッチ）上に、線径３５μmの金線を用い
て、２００個の金バンプ３を形成した。ＦＲ４の回路基
板１２上に半導体装置１と同じピッチの電極１１を形成
し、回路基板１２の電極１１上に導電粒子７の粒径が５
μm、粒子密度が20000個／mm2の異方性導電膜９（図５
参照）を貼り付けた。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment according to the present invention will be described with reference to the drawings. The size is 8.0 × 8.0 as shown in FIG.
mm 2 of the semiconductor device 1 (105 × 105 μm)
m, 130 μm pitch), 200 gold bumps 3 were formed using a gold wire having a wire diameter of 35 μm. The electrodes 11 having the same pitch as the semiconductor device 1 are formed on the circuit board 12 of FR4, and the conductive particles 7 have a particle size of 5 on the electrodes 11 of the circuit board 12.
μm, anisotropic conductive film 9 having a particle density of 20,000 particles / mm 2 (FIG. 5).
See).
【００１７】半導体装置１と回路基板１２の配線は４端
子法で接続抵抗を測定できるように設計した。The wiring between the semiconductor device 1 and the circuit board 12 is designed so that the connection resistance can be measured by a four-terminal method.
【００１８】形成した金バンプ３の高さの平均は６６μ
mであった。一つの半導体装置１の中でバンプ高さの最
大値は７７μm、最小値は５９μmであった。The average height of the formed gold bumps 3 is 66 μm.
m. In one semiconductor device 1, the maximum value of the bump height was 77 μm, and the minimum value was 59 μm.
【００１９】次に図４に示すように、導電粒子７の粒径
より小さい凹凸部が形成された押圧用基板を半導体装置
１に１バンプ当たり５０ｇの加圧力で押し当て、金バン
プ３の先端面に均一な凹凸部を形成した。形成した金バ
ンプ３の高さの平均は５８μmであった。一つの半導体
装置の中でバンプ３高さの最大値は６０μm、最小値は
５７μmであった。Next, as shown in FIG. 4, the pressing substrate on which the irregularities smaller than the particle size of the conductive particles 7 are formed is pressed against the semiconductor device 1 with a pressing force of 50 g per bump. A uniform uneven portion was formed on the surface. The average height of the formed gold bumps 3 was 58 μm. In one semiconductor device, the maximum value of the height of the bump 3 was 60 μm, and the minimum value was 57 μm.
【００２０】次いで図５に示すように、前記半導体装置
１を前記異方性導電膜９を貼り付けた回路基板１２に位
置合わせして、摂氏１８０度，荷重６ｋｇｆで２０秒間
加熱圧着し、前記異方性導電膜９を硬化した。これによ
り１０mΩ以下の接続抵抗が得られた。また、凹凸部を
形成していない場合の接続部あたりの導電粒子数は平均
０〜５個であったが凹凸部を形成した場合の接続部あた
りの導電粒子数は平均６〜９個であった。Next, as shown in FIG. 5, the semiconductor device 1 is positioned on the circuit board 12 to which the anisotropic conductive film 9 is adhered, and is heated and pressed at 180 degrees Celsius under a load of 6 kgf for 20 seconds. The anisotropic conductive film 9 was cured. As a result, a connection resistance of 10 mΩ or less was obtained. In addition, the number of conductive particles per connection portion when the uneven portion was not formed was 0 to 5 on average, but the number of conductive particles per connection portion when the uneven portion was formed was 6 to 9 on average. Was.
【００２１】[0021]
【発明の効果】以上説明したように、本発明によれば、
前記バンプの先端面を前記押圧用基板で平坦化して、前
記異方性導電膜の導電粒子の直径より少し小さい凹凸部
が前記バンプ先端面に均一に形成されているので、前記
半導体装置を前記回路基板に加圧した場合に、前記導電
粒子が前記凹部に確実に捕捉され、電気的接合の信頼性
が更に向上する。As described above, according to the present invention,
The tip surface of the bump is flattened with the pressing substrate, and uneven portions slightly smaller than the diameter of the conductive particles of the anisotropic conductive film are uniformly formed on the bump tip surface. When pressure is applied to the circuit board, the conductive particles are reliably trapped in the recesses, and the reliability of electrical bonding is further improved.
【００２２】また、前記押圧用基板上の凹凸部は前記バ
ンプよりも硬い材料であるため、バンプ先端面に凹凸部
を形成する際、前記押圧用基板を繰り返し使用すること
ができる。よって、繰り返し使用できる前記押圧用基板
を前記バンプに押しつけるのみで、バンプ先端面に均一
な凹凸を容易に一括形成することができる。Since the uneven portion on the pressing substrate is made of a material harder than the bump, the pressing substrate can be used repeatedly when forming the uneven portion on the bump tip surface. Therefore, uniform bumps and bumps can be easily formed on the tip surface of the bump simply by pressing the reusable pressing substrate against the bump.
【図１】従来例の半導体装置の実装方法を使用して実装
された半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device mounted using a conventional semiconductor device mounting method.
【図２】従来例の半導体装置の実装方法を使用して実装
された半導体装置の断面図である。FIG. 2 is a cross-sectional view of a semiconductor device mounted using a conventional semiconductor device mounting method.
【図３】本発明の半導体装置の実装方法の金バンプの断
面図である。FIG. 3 is a cross-sectional view of a gold bump in the semiconductor device mounting method of the present invention.
【図４】本発明の半導体装置の実装方法の押圧工程を示
す断面図である。FIG. 4 is a cross-sectional view showing a pressing step of the semiconductor device mounting method of the present invention.
【図５】本発明の半導体装置の実装方法の第一実施例を
使用して実装された半導体装置の断面図である。FIG. 5 is a cross-sectional view of a semiconductor device mounted using the first embodiment of the semiconductor device mounting method of the present invention.
１…半導体装置、２…アルミ電極、３…金バンプ、４…
押圧用基板、５…凹部、６…凸部、７…導電粒子、８…
押しつぶされた導電粒子、９…異方性導電膜、１０…絶
縁性接着樹脂、１１…回路基板電極、１２…回路基板、
１３…メッキバンプ、１４…金バンプ。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Aluminum electrode, 3 ... Gold bump, 4 ...
Pressing substrate, 5 ... concave, 6 ... convex, 7 ... conductive particles, 8 ...
Crushed conductive particles, 9: anisotropic conductive film, 10: insulating adhesive resin, 11: circuit board electrode, 12: circuit board,
13: plating bump, 14: gold bump.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 藤田 祐治 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Fujita 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.
Claims (1)
工程と、回路基板上に異方性導電膜を貼り付ける工程
と、前記金バンプよりも硬い材料よりなり前記異方性導
電膜の導電粒子の径より小さい凹凸部が形成された押圧
用基板を、前記半導体装置の金バンプの先端面に押圧す
ることにより、前記金バンプの先端面に凹凸部を形成す
る工程と、前記金バンプと前記回路基板の電極とを位置
合わせした後、前記半導体装置を前記異方性導電膜を貼
り付けた前記回路基板に押圧し加熱する工程とを有する
ことを特徴とする半導体装置の実装方法。A step of forming a gold bump on an electrode of a semiconductor device; a step of attaching an anisotropic conductive film on a circuit board; Forming a concave and convex portion on the distal end surface of the gold bump by pressing a pressing substrate on which a concave and convex portion smaller than the diameter of the conductive particles is formed against the distal end surface of the gold bump of the semiconductor device; And positioning the semiconductor device and the electrodes of the circuit board, and then pressing the semiconductor device against the circuit board to which the anisotropic conductive film is attached and heating the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9163736A JPH1116946A (en) | 1997-06-20 | 1997-06-20 | Mounting method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9163736A JPH1116946A (en) | 1997-06-20 | 1997-06-20 | Mounting method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1116946A true JPH1116946A (en) | 1999-01-22 |
Family
ID=15779706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9163736A Pending JPH1116946A (en) | 1997-06-20 | 1997-06-20 | Mounting method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1116946A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100347762B1 (en) * | 1999-12-15 | 2002-08-09 | 엘지전자주식회사 | Direct attatch bonding process of bare chip and pwb |
| CN100416343C (en) * | 2004-01-21 | 2008-09-03 | 友达光电股份有限公司 | Structure for increasing reliability of metal connecting line |
| CN108476591A (en) * | 2015-06-16 | 2018-08-31 | 迪睿合株式会社 | Connector, the manufacturing method of connector, detection method |
| CN111799241A (en) * | 2020-06-24 | 2020-10-20 | 霸州市云谷电子科技有限公司 | Bonding structure, manufacturing method thereof and display panel |
-
1997
- 1997-06-20 JP JP9163736A patent/JPH1116946A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100347762B1 (en) * | 1999-12-15 | 2002-08-09 | 엘지전자주식회사 | Direct attatch bonding process of bare chip and pwb |
| CN100416343C (en) * | 2004-01-21 | 2008-09-03 | 友达光电股份有限公司 | Structure for increasing reliability of metal connecting line |
| CN108476591A (en) * | 2015-06-16 | 2018-08-31 | 迪睿合株式会社 | Connector, the manufacturing method of connector, detection method |
| CN108476591B (en) * | 2015-06-16 | 2021-01-01 | 迪睿合株式会社 | Connected body, method for producing connected body, and method for detecting connected body |
| CN111799241A (en) * | 2020-06-24 | 2020-10-20 | 霸州市云谷电子科技有限公司 | Bonding structure, manufacturing method thereof and display panel |
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