JPH0669278A - Connecting method for semiconductor element - Google Patents
Connecting method for semiconductor elementInfo
- Publication number
- JPH0669278A JPH0669278A JP21912492A JP21912492A JPH0669278A JP H0669278 A JPH0669278 A JP H0669278A JP 21912492 A JP21912492 A JP 21912492A JP 21912492 A JP21912492 A JP 21912492A JP H0669278 A JPH0669278 A JP H0669278A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- connection
- conductive particles
- bumps
- metal bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11332—Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子の接続方法に
係り、特にフェイスダウンボンディング方式の接続方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element connecting method, and more particularly to a face-down bonding method.
【0002】[0002]
【従来の技術】半導体素子の実装方法の一つとして、半
導体素子の接続電極上にバンプを形成し、このバンプを
配線基板に対面させるように半導体素子を配置し、この
バンプと配線基板上の接続電極とを接続する、いわゆる
フェイスダウンボンディング方式が、高密度実装の有力
な実装方式の一つとして知られている。2. Description of the Related Art As one of methods for mounting a semiconductor element, a bump is formed on a connection electrode of the semiconductor element, the semiconductor element is arranged so that the bump faces a wiring board, and the bump and the wiring board are arranged on the wiring board. A so-called face-down bonding method for connecting with a connection electrode is known as one of the leading mounting methods for high-density mounting.
【0003】特に、接続材料として異方性導電膜を用い
て半導体素子を配線基板上に電気的および機械的に接
続、実装する方法は、高密度実装を簡易かつ低コストに
実現する方法として知られている。Particularly, a method of electrically and mechanically connecting and mounting a semiconductor element on a wiring board by using an anisotropic conductive film as a connecting material is known as a method for realizing high-density mounting easily and at low cost. Has been.
【0004】例えば、図3にその構成を示すように、上
面に接続パッド301を有する基板303と、基板30
3の導体パターンを延長してなる接続パッド301を含
む領域上に配置される電気的絶縁性を有する接着剤30
5中に導電粒子307が混入分散され、厚み方向には押
圧により導電性を有するとともにその面方向には電気的
絶縁性を有する異方性導電接着剤309と、異方性導電
接着剤309上に配置され押圧されて異方性導電接着剤
309により基板303に機械的に接着され、かつ下面
の接続電極311が接続パッド301に接続される半導
体素子313とを組み合わせて、半導体素子313の接
続電極311の下面315にも、接続電極311が形成
されていない下面317、319にも、全域にわたって
異方性導電接着剤309が介在していることを特徴とす
る半導体素子の接続技術が、特公昭62−6652号公
報に開示されている。For example, as shown in the structure of FIG. 3, a substrate 303 having connection pads 301 on the upper surface, and a substrate 30.
An adhesive 30 having an electrically insulating property, which is disposed on a region including a connection pad 301 formed by extending the conductor pattern 3 of FIG.
5, the conductive particles 307 are mixed and dispersed, and the anisotropic conductive adhesive 309 has conductivity in the thickness direction by pressing and has electrical insulation in the surface direction, and on the anisotropic conductive adhesive 309. Connection with the semiconductor element 313, which is placed on the substrate and mechanically bonded to the substrate 303 by the anisotropic conductive adhesive 309, and the connection electrode 311 on the lower surface is connected to the connection pad 301. An anisotropic conductive adhesive 309 is interposed over the entire area of the lower surface 315 of the electrode 311 and the lower surfaces 317 and 319 where the connection electrode 311 is not formed. It is disclosed in Japanese Patent Publication No. 62-6652.
【0005】このような接続技術は、例えば図4(a)
に示すように、半導体素子313と予め基板303上に
エッチング等で半導体素子313の接続電極311に対
応する位置に形成した接続パッド301との間に、導電
異方性を持つ異方性導電膜、例えばシート状の異方性導
電接着剤309を配置し、ついで半導体素子313を基
板303上に押圧することによって、半導体素子313
の接続電極311と接続パッド301との導通をとると
いうものである。このとき導通を得るとともに、異方性
導電接着剤309の接着効果により半導体素子313は
基板303に機械的に固着される。このようにして半導
体素子313が基板303上に実装された状態を図4
(b)に示す。また、この図4に示すように、半導体素
子313の接続電極311上に金属バンプ321を形成
することも確実な接続を得るために有効である。Such a connection technique is shown, for example, in FIG.
As shown in FIG. 3, an anisotropic conductive film having a conductive anisotropy is provided between the semiconductor element 313 and the connection pad 301 formed in advance on the substrate 303 at a position corresponding to the connection electrode 311 of the semiconductor element 313 by etching or the like. , For example, a sheet-shaped anisotropic conductive adhesive 309 is arranged, and then the semiconductor element 313 is pressed onto the substrate 303, whereby the semiconductor element 313 is pressed.
The connection electrode 311 and the connection pad 301 are electrically connected. At this time, conductivity is obtained, and the semiconductor element 313 is mechanically fixed to the substrate 303 by the adhesive effect of the anisotropic conductive adhesive 309. FIG. 4 shows a state in which the semiconductor element 313 is thus mounted on the substrate 303.
It shows in (b). Further, as shown in FIG. 4, forming metal bumps 321 on the connection electrodes 311 of the semiconductor element 313 is also effective for obtaining a reliable connection.
【0006】しかしながら、このような異方性導電接着
剤309を用いる場合では、基板303に面する半導体
素子313の下面においては、図3に示す接続電極31
1の下面315にも、接続電極311が形成されてない
下面317、319にも、全域にわたって導電粒子30
7を含有した異方性導電接着剤309が介在している
が、その面方向での電気的絶縁性は実際には必ずしも十
分ではなく、導電粒子307の密度が高過ぎると隣り合
う接続電極311間の電気的絶縁性が低下し、例えば液
晶表示素子に用いられる半導体素子の接続の場合などで
は、液晶表示素子の画像に表示不良を引き起こす。一
方、そのような電気的絶縁性の低下の問題を避けようと
して導電粒子307の密度を低くすると、電気的接続に
関与する導電粒子の数が少なくなるために、接続工程で
の歩留りおよび接続後の信頼性がともに低下する。However, when such an anisotropic conductive adhesive 309 is used, on the lower surface of the semiconductor element 313 facing the substrate 303, the connection electrode 31 shown in FIG.
1 and the lower surfaces 317 and 319 on which the connection electrodes 311 are not formed, the conductive particles 30 are formed over the entire area.
Although the anisotropic conductive adhesive 309 containing 7 is interposed, the electrical insulating property in the plane direction is not always sufficient in practice, and when the density of the conductive particles 307 is too high, the adjacent connection electrodes 311 are not formed. The electrical insulation between them is deteriorated and, for example, in the case of connection of a semiconductor element used for a liquid crystal display element, a display defect is caused in an image of the liquid crystal display element. On the other hand, if the density of the conductive particles 307 is reduced in order to avoid such a problem of deterioration in electrical insulation, the number of conductive particles involved in the electrical connection is reduced, so that the yield in the connection step and after the connection are reduced. The reliability of both decreases.
【0007】このように、隣り合う接続電極311間が
ショートしないように、かつ全ての接続電極311で信
頼性の高い良好な接続が得られるように、導電粒子30
7の密度を設定しなければならないが、特に微細ピッチ
のバンプを有する半導体素子の接続に使用したときにそ
の密度の兼ね合いが難しく、隣り合う接続電極311間
のショートあるいは接続不良が頻発し、その結果、接続
工程の歩留りが低下し、また接続の信頼性が低下すると
いう問題がある。As described above, the conductive particles 30 are formed so that adjacent connection electrodes 311 are not short-circuited and that all connection electrodes 311 can be connected with good reliability.
However, it is difficult to balance the densities of the semiconductor elements, especially when used for connecting semiconductor elements having fine pitch bumps, and short circuits or connection failures between adjacent connection electrodes 311 occur frequently. As a result, there is a problem that the yield of the connection process is reduced and the reliability of the connection is reduced.
【0008】また、このような異方性導電接着剤を用い
るものの他に、表面に導電めっきを施した複数個の導電
樹脂ボールを半導体素子のバンプと基板上のパッドとの
間に挟まれるように配置し、上から押圧してこれらを電
気的に接続させ、また半導体素子と基板との間隙に絶縁
樹脂からなる接着剤を流し込んで半導体素子を基板上に
機械的に固定するという接続技術が開発されている。Besides using such an anisotropic conductive adhesive, a plurality of conductive resin balls having conductive plating on the surface may be sandwiched between the bumps of the semiconductor element and the pads on the substrate. The connection technology is to place the semiconductor element on the substrate mechanically on the substrate by pouring the adhesive from the insulating resin into the gap between the semiconductor element and the substrate by pressing from above to electrically connect them. Being developed.
【0009】あるいは、半導体素子のバンプとしてAu
(金)バンプを用い、このAu(金)バンプを直接基板
上のパッドに押圧してこれらを電気的に接続させるとい
う接続技術が開発されている。Alternatively, Au is used as a bump for a semiconductor element.
A connection technique has been developed in which a (gold) bump is used and the Au (gold) bump is directly pressed against a pad on a substrate to electrically connect them.
【0010】このような接続方法は、より具体的には図
5に示すように、あらかじめ基板303または半導体素
子313の接続電極311上に、導電樹脂ボール501
を精密なアライメント(位置合わせ)を行なって配置し
ておき、この導電樹脂ボール501の位置に接続電極3
11と接続パッド301とが合致するように半導体素子
313をフェイスダウンの状態で基板303に押し付け
て電気的な接続を得るとともに、このような導電樹脂ボ
ール501をある程度押し潰したような状態のまま半導
体素子313と基板303との間隙に絶縁性樹脂からな
る接着剤503を流し込んで半導体素子313を基板3
03上に機械的に固定するというものである。あるい
は、半導体素子313の接続電極311としてAuバン
プを用いて、このAuバンプを直接に接続パッド301
に押し当てて接続するというものである。More specifically, as shown in FIG. 5, such a connection method is performed by previously forming a conductive resin ball 501 on the connection electrode 311 of the substrate 303 or the semiconductor element 313 in advance.
Are arranged by performing precise alignment (positioning), and the connection electrode 3 is placed at the position of the conductive resin ball 501.
11, the semiconductor element 313 is pressed face down on the substrate 303 so that the connection pad 301 and the connection pad 301 coincide with each other to obtain an electrical connection, and the conductive resin ball 501 is crushed to a certain degree as it is. An adhesive 503 made of an insulating resin is poured into a gap between the semiconductor element 313 and the substrate 303 so that the semiconductor element 313 is attached to the substrate 3
It is to fix it mechanically on 03. Alternatively, an Au bump is used as the connection electrode 311 of the semiconductor element 313, and the Au bump is directly connected to the connection pad 301.
It is to press and connect to.
【0011】この接続方法では、半導体素子313の接
続電極311と基板303の接続パッド301との電気
的接続は導電樹脂ボール501(またはAuバンプ)で
行ない、半導体素子313と基板303との機械的な固
着は絶縁性樹脂からなる接着剤503で行なって、この
接着剤503の圧縮応力と導電樹脂ボール501(また
はAuバンプ)の復元力および圧着力との合力により電
気的接続を確実に行なうようにしている。In this connection method, the connection electrode 311 of the semiconductor element 313 and the connection pad 301 of the substrate 303 are electrically connected by the conductive resin balls 501 (or Au bumps), and the semiconductor element 313 and the substrate 303 are mechanically connected. Adhesion is performed with an adhesive 503 made of an insulating resin, and electrical connection is ensured by the combined force of the compressive stress of the adhesive 503 and the restoring force and pressure of the conductive resin balls 501 (or Au bumps). I have to.
【0012】しかしながら、このような接続方法の場合
では、前記の導電樹脂ボール501(あるいはAuバン
プ)を基板303上の接続パッド301あるいは半導体
素子313の接続電極311上に配置するためには、精
密なアライメント(位置合わせ)を行なわなければなら
ないが、近年ますます高密度、微細化の進む実装技術に
あっては、そのような精密なアライメントの工程は、ま
すます困難で煩雑なものとなってきており、接続工程の
歩留りが低下するという問題がある。However, in the case of such a connection method, in order to dispose the conductive resin ball 501 (or Au bump) on the connection pad 301 on the substrate 303 or the connection electrode 311 of the semiconductor element 313, it is necessary to precisely It is necessary to perform precise alignment (positioning), but in recent years, with mounting technology that is becoming more dense and miniaturized, such a precise alignment process becomes more and more difficult and complicated. Therefore, there is a problem that the yield of the connection process is reduced.
【0013】[0013]
【発明が解決しようとする課題】このように、従来のフ
ェイスダウンボンディング方式による半導体素子の接続
方法においては、バンプ間または接続パッド間の絶縁不
良によるショートの問題や、接続部材としての導電樹脂
ボール、あるいはAuバンプを配置するための精密なア
ライメントを行なう煩雑な工程の付加による歩留まりの
低下などの問題があった。As described above, in the conventional method of connecting semiconductor elements by the face-down bonding method, there is a problem of short circuit due to defective insulation between bumps or connection pads, and a conductive resin ball as a connecting member. Alternatively, there is a problem such as a decrease in yield due to the addition of a complicated process for performing precise alignment for arranging the Au bumps.
【0014】本発明はこのような問題を解決するために
成されたもので、その目的は、フェイスダウンボンディ
ング方式による半導体素子の接続方法において、バンプ
間の絶縁不良によるショートの問題や、接続部材として
の導電樹脂ボール、あるいはAuバンプを配置するため
の精密なアライメントを行なう煩雑な工程の付加による
歩留まりの低下などの問題を解消して、歩留りが高くか
つ信頼性の高い半導体素子の接続方法を提供することに
ある。The present invention has been made to solve such a problem, and an object thereof is a method of connecting a semiconductor element by a face-down bonding method, in which a problem of short circuit due to defective insulation between bumps and a connecting member. As a method for connecting a semiconductor element having a high yield and a high reliability, the problems such as a decrease in yield due to the addition of a complicated process for performing a precise alignment for arranging the conductive resin balls or Au bumps as described above are solved. To provide.
【0015】[0015]
【課題を解決するための手段】本発明の半導体素子の接
続方法は、平面上に複数の導電粒子を散布し、接続電極
上に金属バンプが設けられた半導体素子を前記平面に対
して平行に押圧して前記金属バンプに前記導電粒子を付
着させ、前記半導体素子の金属バンプに付着した前記導
電粒子を配線基板の接続パッドに圧接して、前記金属バ
ンプと前記接続パッドとを前記導電粒子を介して電気的
に接続し、前記半導体素子と前記配線基板との間隙に絶
縁性接着剤を介挿して前記半導体素子と前記配線基板と
を固着させることを特徴としている。According to a method of connecting a semiconductor element of the present invention, a plurality of conductive particles are dispersed on a plane, and a semiconductor element having metal bumps provided on connection electrodes is made parallel to the plane. The conductive particles are adhered to the metal bumps by pressing, and the conductive particles adhered to the metal bumps of the semiconductor element are pressed against the connection pads of the wiring board, and the metal bumps and the connection pads are connected to the conductive particles. It is characterized in that the semiconductor element and the wiring board are fixed to each other by electrically connecting the semiconductor element and the wiring board by inserting an insulating adhesive in a gap between the semiconductor element and the wiring board.
【0016】なお、前記の導電粒子は、半導体素子の隣
り合う金属バンプ間の間隙よりも小さな直径でかつ適度
な大きさを有するように設定されていることが望まし
く、その直径は複数の導電粒子でばらつきが少ないこと
が望ましい。また、その導電粒子の材質としては、導電
性を有するものであればよい。例えばNi(ニッケル)
のような金属の球でもよく、あるいは合成樹脂の表面に
金属被膜をコーティングした導電樹脂ボールでもよい。The conductive particles are preferably set to have a diameter smaller than the gap between the adjacent metal bumps of the semiconductor element and to have an appropriate size, and the diameter is plural. It is desirable that there is little variation. The material of the conductive particles may be any material that has conductivity. For example, Ni (nickel)
Such a metal ball may be used, or a conductive resin ball having a synthetic resin surface coated with a metal film may be used.
【0017】また、この導電粒子を平面上に散布する際
には、その平面的な分布密度はできるだけ均一であるこ
とが望ましい。Further, when the conductive particles are dispersed on a plane, it is desirable that the distribution density on the plane is as uniform as possible.
【0018】また、金属バンプに導電粒子を付着させる
際には、金属バンプに導電粒子が破壊しない程度に押し
込まれるような形で一旦定着するようにしてもよく、あ
るいは金属バンプに導電粒子を付着させた直後に、導電
粒子が団塊状態にならない程度の適度な粘性を有する接
着剤などを用いて導電粒子を金属バンプに一旦定着させ
ておくようにしてもよい。Further, when the conductive particles are attached to the metal bumps, the conductive particles may be once fixed so that the conductive particles are pushed into the metal bumps so as not to be destroyed, or the conductive particles are attached to the metal bumps. Immediately after this, the conductive particles may be once fixed to the metal bumps by using an adhesive or the like having an appropriate viscosity such that the conductive particles do not become a nodular state.
【0019】また、導電粒子を介して半導体素子の金属
バンプと配線基板の接続パッドとを押圧する際には、熱
を加えつつ半導体素子を配線基板に押圧して、これらを
導電粒子を介してやや溶かすような形で接合してもよ
い。When pressing the metal bumps of the semiconductor element and the connection pads of the wiring board through the conductive particles, the semiconductor element is pressed against the wiring board while applying heat, and these are pressed through the conductive particles. You may join in the form which melts a little.
【0020】また、半導体素子と配線基板との間隙に介
挿する接着剤は、半導体素子を配線基板に押圧する前に
あらかじめ配線基板上に配置しておいてもよく、あるい
はその押圧後に間隙部分に注入してもよい。The adhesive inserted in the gap between the semiconductor element and the wiring board may be placed on the wiring board in advance before the semiconductor element is pressed against the wiring board, or after the pressing, the gap portion is formed. May be injected into.
【0021】[0021]
【作用】本発明の接続方法によれば、半導体素子のバン
プ上にのみ導電粒子が配置され、隣り合うバンプ間には
導電粒子が配置されないため、隣り合うバンプ間などで
の良好な電気的絶縁性が得られる。According to the connection method of the present invention, the conductive particles are arranged only on the bumps of the semiconductor element, and the conductive particles are not arranged between the adjacent bumps. Therefore, good electrical insulation is provided between the adjacent bumps. Sex is obtained.
【0022】しかも、そのバンプが凸状になっているこ
とを利用してこのバンプ上だけに導電粒子を押し付ける
ようにして付着させるので、バンプや基板上の接続パッ
ド上への煩雑なアライメント作業を行なわずして導電粒
子を配置できる。これにより、導電粒子の配置工程が極
めて簡易なものとなり、高歩留りを実現できる。Moreover, since the bumps are convex, the conductive particles are pressed and adhered only onto the bumps, so that complicated alignment work on the bumps or the connection pads on the substrate can be performed. The conductive particles can be arranged without performing. As a result, the step of arranging the conductive particles becomes extremely simple, and a high yield can be realized.
【0023】また、異方性導電接着剤を使用した接続に
比べてバンプ上の導電に寄与する導電粒子数を多く取る
ことができるため、接続抵抗を低くすることができ、接
続の信頼性が向上する。Further, as compared with the connection using the anisotropic conductive adhesive, the number of conductive particles contributing to the conductivity on the bump can be increased, so that the connection resistance can be lowered and the connection reliability can be improved. improves.
【0024】その結果、半導体素子の信頼性の高い接続
を、高歩留りで実現することができる。As a result, highly reliable connection of semiconductor elements can be realized with high yield.
【0025】[0025]
【実施例】以下、本発明の半導体素子の接続方法の一実
施例を、図面に基づいて詳細に説明する。本発明に係る
接続方法の説明のためにこの実施例で用いた半導体素子
および配線基板は、液晶表示装置に用いられるものとし
た。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor element connecting method of the present invention will be described in detail below with reference to the drawings. The semiconductor element and the wiring board used in this example for explaining the connection method according to the present invention are used in a liquid crystal display device.
【0026】図1に示すように、液晶表示装置に用いら
れるようなガラス基板1上に、所定の箇所に接続パッド
3が形成されている。この接続パッド3は、例えば表面
層がAl(アルミ)またはAlを主体とする金属膜ある
いは金属多層膜からなる接続電極パターンであり、本実
施例ではCr膜、Al膜が下層からこの順に形成されて
いる。このCr膜、Al膜の膜厚は、それぞれ70nm、
400nmに設定されている。以下、このCr膜、Al膜
からなる金属多層膜をCr/Al膜と略称する。配線基
板4は、このように構成されている。As shown in FIG. 1, a connection pad 3 is formed at a predetermined position on a glass substrate 1 used in a liquid crystal display device. The connection pad 3 is, for example, a connection electrode pattern having a surface layer made of Al (aluminum) or a metal film or a metal multi-layer film mainly containing Al. In this embodiment, a Cr film and an Al film are formed in this order from the lower layer. ing. The thicknesses of the Cr film and the Al film are 70 nm,
It is set to 400 nm. Hereinafter, the metal multilayer film including the Cr film and the Al film will be simply referred to as a Cr / Al film. The wiring board 4 is configured in this way.
【0027】一方、半導体素子11である出力数 120の
液晶駆動用ICは、およそ 5mm×9mmの外形寸法を
有する。Alからなる接続電極5とパッシベーション膜
7が形成され、接続電極5上には、図示は省略するが、
例えばTi、Ni、Auがこの順序で構成されたバリア
メタル層が形成されている。このバリアメタル層を介し
て接続電極5の上に例えばAuからなる金属バンプ9が
めっき法などによって形成されている。その金属バンプ
9は、高さ約23μm、大きさ約 100μm平方である。ま
たその接続ピッチは 140μmである。そして液晶駆動用
ICである半導体素子11の金属バンプ9以外の表面
は、窒化シリコンなどからなる前述のパッシベーション
膜7によって保護されている。半導体素子11は、この
ように構成されている。On the other hand, the liquid crystal driving IC, which is the semiconductor element 11 and has 120 outputs, has an outer dimension of approximately 5 mm × 9 mm. A connection electrode 5 and a passivation film 7 made of Al are formed, and although not shown on the connection electrode 5,
For example, a barrier metal layer composed of Ti, Ni, and Au in this order is formed. Metal bumps 9 made of, for example, Au are formed on the connection electrodes 5 via the barrier metal layer by a plating method or the like. The metal bump 9 has a height of about 23 μm and a size of about 100 μm square. The connection pitch is 140 μm. The surface of the semiconductor element 11, which is a liquid crystal driving IC, other than the metal bumps 9 is protected by the passivation film 7 made of silicon nitride or the like. The semiconductor element 11 is configured in this way.
【0028】次に、本発明に係る導電粒子を半導体素子
に付着させる工程について、図2を参照して説明する。Next, the step of adhering the conductive particles according to the present invention to the semiconductor element will be described with reference to FIG.
【0029】まず、図2(a)に示すように、平坦なガ
ラスのような平面治具15上に、導電粒子17を平面的
に密度が均一となるように散布する。具体的には、一
旦、導電粒子17を平面治具15上にばらまき、スキー
ジ19を用いて平面治具15上にほぼ均一な厚さで均一
な平面的密度になるように拡げて分散させ、導電粒子層
21を形成する。この状態を図2(b)に示す。First, as shown in FIG. 2 (a), conductive particles 17 are sprayed on a flat jig 15 such as flat glass so that the density becomes uniform in a plane. Specifically, once the conductive particles 17 are scattered on the plane jig 15, and spread with a squeegee 19 on the plane jig 15 so as to have a substantially uniform thickness and a uniform planar density. The conductive particle layer 21 is formed. This state is shown in FIG.
【0030】この導電粒子層21の厚さは、半導体素子
11の金属バンプ9の高さ以下でありかつ隣り合う金属
バンプ9の間隙以下とする。The thickness of the conductive particle layer 21 is not more than the height of the metal bumps 9 of the semiconductor element 11 and not more than the gap between the adjacent metal bumps 9.
【0031】この導電粒子17としては、例えばNi
(ニッケル)からなる粒子を用いる。この導電粒子17
の形状は、完全な球形でなくてもよく、また球形の他に
も、例えばイガグリ状であってもよい。The conductive particles 17 are, for example, Ni.
Particles made of (nickel) are used. This conductive particle 17
The shape of does not have to be a perfect spherical shape, and may be, for example, a worm shape other than the spherical shape.
【0032】次に、接続電極5上に金属バンプ9を設け
た半導体素子11を、導電粒子層21を形成した平面治
具15上に対して平行に、例えば加圧治具23を用いて
押圧して、室温で約 9kgの荷重を 5秒間印加して、図
2(c)に示すように導電粒子17を金属バンプ9上に
ある程度押し込んで、部分的に埋没するような形に付着
させる。そして図2(d)に示すように、半導体素子1
1を平面治具15から引き離す。Next, the semiconductor element 11 provided with the metal bumps 9 on the connection electrodes 5 is pressed in parallel with the flat jig 15 on which the conductive particle layer 21 is formed by using, for example, a pressing jig 23. Then, at room temperature, a load of about 9 kg is applied for 5 seconds to push the conductive particles 17 onto the metal bumps 9 to some extent as shown in FIG. Then, as shown in FIG.
1 is separated from the flat jig 15.
【0033】導電粒子17を平面治具15上へ拡げる方
法としては、前述のような簡便な方法でもよいが、導電
粒子層21をできるだけ均一の高さに拡げれば導電粒子
17が金属バンプ9以外に付着させることなく金属バン
プ9上のみに付着させやすくなり、隣り合う金属バンプ
9間でのショートの発生などを避けることができ、接続
工程での歩留りが向上する。The conductive particles 17 can be spread on the flat jig 15 by the simple method as described above, but if the conductive particle layer 21 is spread to a uniform height as much as possible, the conductive particles 17 can be spread over the metal bumps 9. Besides, it becomes easy to adhere only on the metal bumps 9 without adhering, it is possible to avoid the occurrence of a short circuit between the adjacent metal bumps 9, and the yield in the connection process is improved.
【0034】そのように導電粒子17を平面治具15上
に均一な厚さで均一な平面的密度に拡げる方法として
は、例えばアセトンなどの有機溶剤のような揮発性の高
い液体を用いて、その粘性を導電粒子が団塊状にならな
いように調節し、この液体中に導電粒子17を分散させ
て平面治具15上に塗布する方法などを用いることがで
きる。As a method of spreading the conductive particles 17 on the flat jig 15 to have a uniform thickness and a uniform planar density, a highly volatile liquid such as an organic solvent such as acetone is used. A method may be used in which the viscosity is adjusted so that the conductive particles do not become agglomerate, and the conductive particles 17 are dispersed in this liquid and applied onto the flat jig 15.
【0035】また、例えば平面治具15上に導電粒子1
7を一旦散乱させ、これに超音波を印加してその導電粒
子層21の高さをならすようにすることもできる。この
場合、平面治具15上に、導電粒子17の径に近い大き
さの微細な凹凸のついた治具を用いると、さらに効果的
である。Further, for example, the conductive particles 1 are placed on the flat jig 15.
It is also possible to scatter 7 once and apply ultrasonic waves to this so as to level the height of the conductive particle layer 21. In this case, it is more effective to use a jig having fine irregularities having a size close to the diameter of the conductive particles 17 on the plane jig 15.
【0036】以上の方法は、導電粒子17が平面治具1
5上に固定されていないため、半導体素子11を平面治
具15に押圧して半導体素子11の金属バンプ9上に導
電粒子17を付着させる際に導電粒子17が飛散しやす
い。In the above method, the conductive particles 17 are used for the flat jig 1.
5, the conductive particles 17 are easily scattered when the semiconductor element 11 is pressed against the flat jig 15 to adhere the conductive particles 17 onto the metal bumps 9 of the semiconductor element 11.
【0037】そこで、揮発性の高い液体、例えばポリビ
ニルアルコール等の溶剤、あるいはこの付着工程の後工
程である熱圧着による接続工程時の熱で揮発しやすいよ
うな膜、例えばポリビニルアルコール等の膜を用いて、
導電粒子17をコーティングして、その膜の弱い力で導
電粒子17を平面治具15上に一旦定着させておくこと
も有効である。Therefore, a highly volatile liquid, for example, a solvent such as polyvinyl alcohol, or a film that easily volatilizes due to heat during the connection step by thermocompression bonding which is a step subsequent to this adhesion step, for example, a film such as polyvinyl alcohol is used. make use of,
It is also effective to coat the conductive particles 17 and once fix the conductive particles 17 on the flat jig 15 by the weak force of the film.
【0038】さて次に、半導体素子11を配線基板4上
にフェイスダウンボンディング方式で実装し、配線基板
4上のCr/Al膜からなる接続パッド3に半導体素子
11である液晶駆動用ICの金属バンプ9を電気的に接
続する工程を、主に図1を参照して説明する。Next, the semiconductor element 11 is mounted on the wiring board 4 by the face-down bonding method, and the metal of the liquid crystal driving IC, which is the semiconductor element 11, is connected to the connection pad 3 made of the Cr / Al film on the wiring board 4. The process of electrically connecting the bumps 9 will be described mainly with reference to FIG.
【0039】本実施例では、絶縁性接着剤として絶縁性
接着シート13を用いた。この絶縁性接着シート13
は、粘着性があり、しかも半導体素子11の金属バンプ
9が加熱押圧されたときに溶融し、押圧された金属バン
プ9の部分の樹脂が流れ出すような材質からなるもので
ある。これを配線基板4上の、外寸が半導体素子11よ
りやや大きな領域に貼設する。これを図1(a),
(b)に示す。In this embodiment, the insulating adhesive sheet 13 is used as the insulating adhesive. This insulating adhesive sheet 13
Is adhesive and is made of a material that melts when the metal bumps 9 of the semiconductor element 11 are heated and pressed, and the resin of the pressed metal bumps 9 flows out. This is attached to a region on the wiring board 4 whose outer size is slightly larger than that of the semiconductor element 11. This is shown in FIG.
It shows in (b).
【0040】次に、自動ボンディング装置で接続パッド
3と金属バンプ9との位置合わせを行ない、図1(c)
に示すように、ボンディングツール23で半導体素子1
1の裏面側から温度約 190℃に加熱しながら約 9kgの
圧力をかけて約30秒間保持する。Then, the connection pads 3 and the metal bumps 9 are aligned with each other by an automatic bonding apparatus, and then, as shown in FIG.
As shown in FIG.
While heating from the back side of 1 to a temperature of about 190 ° C, apply a pressure of about 9 kg and hold for about 30 seconds.
【0041】このとき、配線基板4を含む液晶表示素子
全体は、約60℃に加熱したステージ(いずれも図示省
略)上に載せてある。At this time, the entire liquid crystal display element including the wiring board 4 is placed on a stage (not shown) heated to about 60 ° C.
【0042】続いてボンディングツール23を半導体素
子11から離せば、図1(d)に示すように金属バンプ
9と接続パッド3とが導電粒子17を介して接続され
る。Subsequently, when the bonding tool 23 is separated from the semiconductor element 11, the metal bumps 9 and the connection pads 3 are connected via the conductive particles 17 as shown in FIG.
【0043】このようにして半導体素子11は配線基板
4上に固着されて実装され、その金属バンプ9と接続パ
ッド3とが導電粒子17を介して接続される。In this way, the semiconductor element 11 is fixedly mounted on the wiring board 4, and the metal bumps 9 thereof and the connection pads 3 are connected via the conductive particles 17.
【0044】本実施例で用いた絶縁性接着シート13
は、エポキシ系の熱硬化性樹脂であり、接続時に 190℃
に加熱して約30秒間保持することにより硬化が進み、液
晶駆動用ICである半導体素子11の表面保護層として
のパッシベーション膜7、配線基板4に強固に接着す
る。このように液晶駆動用ICである半導体素子11全
体が配線基板4上に強固に機械的に固着されるので、そ
の後にポッティングなどにより固着を補強することなど
も不要となる。Insulating adhesive sheet 13 used in this example
Is an epoxy-based thermosetting resin, and is 190 ° C when connected.
By heating and holding for about 30 seconds, the curing proceeds, and the liquid crystal driving IC is firmly bonded to the passivation film 7 as the surface protection layer of the semiconductor element 11 and the wiring board 4. Since the entire semiconductor element 11 which is a liquid crystal driving IC is firmly and mechanically fixed on the wiring board 4 in this manner, it is not necessary to reinforce the fixation by potting or the like thereafter.
【0045】このようにして接続された液晶表示装置の
液晶駆動用ICである半導体素子11の接続部分の接触
抵抗を実測して評価したところ、接続箇所 182か所に対
して、イニシャル値が平均 0.1Ω、最大値が 0.2Ωであ
り、オープンおよびショートは一か所も発生していない
という結果が確認された。When the contact resistance of the connection portion of the semiconductor element 11 which is the liquid crystal driving IC of the liquid crystal display device thus connected is measured and evaluated, the initial values are averaged for 182 connection points. It was 0.1Ω, the maximum value was 0.2Ω, and it was confirmed that there were no open or short circuits.
【0046】さらに、−30℃(30分間)/85℃(30分
間)を 500サイクル繰り返す熱衝撃試験と、65℃・RH
95%(相対湿度)で1000時間の高温高湿保存試験と、85
℃で1000時間の高温保存試験と、−10℃から65℃でRH
95%の 5サイクルの温湿度サイクル試験と、動作試験
と、振動試験および衝撃試験等の機械的耐久性試験など
の各種信頼性の試験をこの液晶表示装置に行なって、そ
の耐久信頼性を評価したところ、接続箇所のオープンお
よびショートなどの発生が皆無であるという結果を得
た。Further, a thermal shock test in which -30 ° C. (30 minutes) / 85 ° C. (30 minutes) is repeated 500 cycles, and 65 ° C. RH
95% (relative humidity) 1000 hours high temperature and high humidity storage test, 85
High temperature storage test at 1000 ℃ for 1000 hours and RH at -10 ℃ to 65 ℃
The liquid crystal display is subjected to various reliability tests such as a 95% 5-cycle temperature / humidity cycle test, an operation test, and a mechanical durability test such as a vibration test and an impact test, and the durability reliability is evaluated. As a result, the result was that there was no occurrence of open or short at the connection point.
【0047】このように、本発明の接続方法によれば、
半導体素子11の金属バンプ9上にのみ導電粒子17が
配置され、隣り合う金属バンプ9どうしの間隙には導電
粒子17が配置されないため、隣り合う金属バンプ9間
などでの良好な電気的絶縁性を得ることができる。Thus, according to the connection method of the present invention,
Since the conductive particles 17 are arranged only on the metal bumps 9 of the semiconductor element 11 and the conductive particles 17 are not arranged in the gaps between the adjacent metal bumps 9, good electrical insulation between adjacent metal bumps 9 is obtained. Can be obtained.
【0048】しかも、その金属バンプ9上または配線基
板4の接続パッド3上に、煩雑なアライメント作業を行
なわずして導電粒子17を配置できるので、その配置工
程が極めて簡易で、高歩留りを実現できる。Moreover, since the conductive particles 17 can be arranged on the metal bumps 9 or the connection pads 3 of the wiring board 4 without performing a complicated alignment work, the arrangement process is extremely simple and a high yield is realized. it can.
【0049】また、異方性導電接着剤を使用した接続に
比べて、金属バンプ9上の導電に寄与する導電粒子17
の数を多く取ることができるため、その接続抵抗を低く
することができ、接続の信頼性が向上する。Further, as compared with the connection using the anisotropic conductive adhesive, the conductive particles 17 contributing to the conductivity on the metal bumps 9 are formed.
Since a large number can be taken, the connection resistance can be reduced and the connection reliability is improved.
【0050】その結果、半導体素子の信頼性の高い接続
を、高歩留りで実現することができる。As a result, highly reliable connection of semiconductor elements can be realized with high yield.
【0051】なお、導電粒子17は、半導体素子11の
隣り合う金属バンプ9間の間隙および金属バンプ9の厚
さよりも小さな直径でかつ適度な大きさを有するように
設定されていることが望ましく、またその直径は複数の
導電粒子でばらつきが少ないことが望ましい。本実施例
では、半導体素子11の隣り合う金属バンプ9の幅が10
0μm、そのピッチが 140μmで、その間隙は40μmで
ある。またこの金属バンプ9の厚さは23μmである。そ
して導電粒子17の直径を 2〜 6μmとした。このよう
な組み合わせによって効果的な接続が実現されること
は、上述の通りである。It is desirable that the conductive particles 17 have a diameter smaller than the gap between the adjacent metal bumps 9 of the semiconductor element 11 and the thickness of the metal bumps 9 and have an appropriate size. Further, it is desirable that the diameter of the plurality of conductive particles has little variation. In this embodiment, the width of the adjacent metal bumps 9 of the semiconductor element 11 is 10
The pitch is 0 μm, the pitch is 140 μm, and the gap is 40 μm. The thickness of the metal bump 9 is 23 μm. The diameter of the conductive particles 17 is set to 2 to 6 μm. As described above, an effective connection is realized by such a combination.
【0052】また、導電粒子17の材質としては、導電
性を有するものであればよい。例えば本実施例のような
Ni(ニッケル)のような金属からなるものでもよく、
あるいは合成樹脂の表面に金属膜をコーティングした導
電樹脂ボールでもよい。The material of the conductive particles 17 may be any material having conductivity. For example, it may be made of a metal such as Ni (nickel) as in this embodiment,
Alternatively, a conductive resin ball having a surface of synthetic resin coated with a metal film may be used.
【0053】また、半導体素子11と配線基板4との間
隙に介挿する絶縁性接着シート13は、半導体素子11
を配線基板4に押圧する前にあらかじめ配線基板4上に
配置しておいてもよく、あるいはその押圧後にその間隙
部分に注入してもよい。The insulating adhesive sheet 13 inserted in the gap between the semiconductor element 11 and the wiring board 4 is
May be previously arranged on the wiring board 4 before being pressed against the wiring board 4, or may be injected into the gap portion after the pressing.
【0054】また、本実施例では、液晶駆動用ICとし
ての半導体素子11の金属バンプ9がAuの場合を例に
とり詳述したが、この金属バンプ9としては、この他に
も導電粒子17がよく食い込むような材質からなる金属
バンプ、例えばPb−Sn系、Pb−In系などのハン
ダバンプであってもよい。In the present embodiment, the case where the metal bumps 9 of the semiconductor element 11 as the liquid crystal driving IC is Au has been described in detail as an example. However, as the metal bumps 9, other conductive particles 17 are used. It may be a metal bump made of a material that bites well, for example, a Pb-Sn-based or Pb-In-based solder bump.
【0055】また、半導体素子11の接続電極5上にバ
リアメタルを形成し、メッキ法で形成された金属バンプ
付き半導体素子について詳述したが、このバリアメタル
の構成は、例えばPt/Ti膜であってもよい。さら
に、メッキ法以外にも、例えばディップ法やボールボン
ディング法により形成されたバンプを用いる場合にも本
発明の接続方法を適用することができる。Further, a semiconductor element with a metal bump formed by forming a barrier metal on the connection electrode 5 of the semiconductor element 11 and plating is described in detail. The structure of the barrier metal is, for example, a Pt / Ti film. It may be. In addition to the plating method, the connection method of the present invention can be applied to the case where bumps formed by the dip method or the ball bonding method are used.
【0056】また、本実施例においてはガラス基板1上
に形成された接続パッド3がCr/Al膜からなる場合
を例にとって説明したが、接続パッド3が金属または金
属多層膜でその表面層の材料がAl,Al合金である場
合以外にも、例えばAl、Al合金の上にその他の薄い
金属が形成されている場合などでも、この発明が適用で
きる。このような例としては、ガラス基板1上にMo、
Al、Moがこの順に形成された接続パッド3(それぞ
れの膜厚は、例えば70nm、 400nm、 500nmなど)
を用いた場合にも適用できる。In the present embodiment, the case where the connection pad 3 formed on the glass substrate 1 is made of a Cr / Al film has been described as an example. However, the connection pad 3 is a metal or a metal multi-layer film and its surface layer is The present invention can be applied not only when the material is Al or Al alloy, but also when other thin metal is formed on Al or Al alloy, for example. As such an example, Mo on the glass substrate 1,
Connection pad 3 in which Al and Mo are formed in this order (thicknesses are 70 nm, 400 nm, 500 nm, etc.)
It is also applicable when using.
【0057】また、上記各実施例では、液晶表示装置を
例にとり説明したが、本発明の接続方法は液晶表示装置
の半導体素子への適用のみには限定しない。基板上にフ
ェイスダウンで実装されるような半導体素子の全てに適
用することができる。In each of the above embodiments, the liquid crystal display device has been described as an example, but the connection method of the present invention is not limited to application to the semiconductor element of the liquid crystal display device. It can be applied to all semiconductor devices mounted face down on a substrate.
【0058】また、本発明の接続方法をその液晶駆動用
ICに用いた液晶表示装置などでは、その液晶駆動用I
Cの接続は信頼性が十分に高いので、その裏面もしくは
側面から樹脂で覆って封止せずともよいが、さらにその
ように封止樹脂で覆ってもよいことはいうまでもない。In a liquid crystal display device using the connection method of the present invention for its liquid crystal driving IC, the liquid crystal driving IC
Since the connection of C has sufficiently high reliability, it is not necessary to cover it from the back surface or the side surface with resin for sealing, but it goes without saying that it may be covered with sealing resin in such a manner.
【0059】[0059]
【発明の効果】以上、詳細な説明で明示したように、本
発明の接続方法は、フェイスダウン方式による半導体素
子の接続方法において、バンプ間の絶縁不良によるショ
ートの問題や、接続部材としての導電樹脂ボール、ある
いはAuバンプを配置するための精密なアライメントを
行なう煩雑な工程の付加による歩留まりの低下などの問
題を解消して、歩留りが高くかつ信頼性の高い半導体素
子の接続を実現することができる。As described above in detail, the connection method of the present invention is a face-down type semiconductor element connection method, in which the problem of short circuit due to defective insulation between bumps and the conductivity as a connection member. It is possible to solve a problem such as a decrease in yield due to the addition of a complicated process for performing a precise alignment for arranging a resin ball or Au bump, and realize a highly reliable and highly reliable connection of semiconductor elements. it can.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明に係る半導体素子の接続プロセスを示す
図。FIG. 1 is a diagram showing a process of connecting a semiconductor device according to the present invention.
【図2】実施例に係る導電粒子を、半導体素子の金属バ
ンプ上に付着させるプロセスを示す図。FIG. 2 is a diagram showing a process of attaching conductive particles according to an example onto metal bumps of a semiconductor element.
【図3】異方性導電接着剤を用いた従来の半導体素子の
接続技術の一例を示す図。FIG. 3 is a diagram showing an example of a conventional semiconductor element connection technique using an anisotropic conductive adhesive.
【図4】異方性導電接着剤を用いた従来の半導体素子の
接続プロセスの一例を示す図。FIG. 4 is a diagram showing an example of a conventional semiconductor element connection process using an anisotropic conductive adhesive.
【図5】導電樹脂ボールを用いた従来の半導体素子の接
続技術の一例を示す図。FIG. 5 is a diagram showing an example of a conventional semiconductor element connection technique using conductive resin balls.
1…ガラス基板、3…接続パッド、4…配線基板、5…
接続電極、7…パッシベーション膜、9…金属バンプ、
11…半導体素子、13…絶縁性接着シート、15…平
面治具、17…導電粒子、19…スキージ、21…導電
粒子層、23…加圧治具1 ... Glass substrate, 3 ... Connection pad, 4 ... Wiring substrate, 5 ...
Connection electrode, 7 ... passivation film, 9 ... metal bump,
11 ... Semiconductor element, 13 ... Insulating adhesive sheet, 15 ... Planar jig, 17 ... Conductive particles, 19 ... Squeegee, 21 ... Conductive particle layer, 23 ... Pressing jig
Claims (1)
平面に対して平行に押圧して前記金属バンプに前記導電
粒子を付着させ、 前記半導体素子の金属バンプに付着した前記導電粒子を
配線基板の接続パッドに圧接して、前記金属バンプと前
記接続パッドとを前記導電粒子を介して電気的に接続
し、 前記半導体素子と前記配線基板との間隙に絶縁性接着剤
を介挿して前記半導体素子と前記配線基板とを固着させ
ることを特徴とする半導体素子の接続方法。1. A plurality of conductive particles are scattered on a plane, and a semiconductor element having metal bumps on connection electrodes is pressed in parallel with the plane to attach the conductive particles to the metal bumps. The conductive particles attached to the metal bumps of the semiconductor element are pressed against the connection pads of the wiring board to electrically connect the metal bumps and the connection pads through the conductive particles, and the semiconductor element and the wiring. A method of connecting a semiconductor element, wherein the semiconductor element and the wiring board are fixed to each other by interposing an insulating adhesive in a gap between the board and the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21912492A JPH0669278A (en) | 1992-08-18 | 1992-08-18 | Connecting method for semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21912492A JPH0669278A (en) | 1992-08-18 | 1992-08-18 | Connecting method for semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0669278A true JPH0669278A (en) | 1994-03-11 |
Family
ID=16730619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21912492A Withdrawn JPH0669278A (en) | 1992-08-18 | 1992-08-18 | Connecting method for semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0669278A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997047031A1 (en) * | 1996-06-07 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for mounting semiconductor chip |
WO1999010928A1 (en) * | 1997-08-21 | 1999-03-04 | Citizen Watch Co., Ltd. | Semiconductor device and method of fabricating the same |
US6189208B1 (en) | 1998-09-11 | 2001-02-20 | Polymer Flip Chip Corp. | Flip chip mounting technique |
US6219911B1 (en) | 1998-03-23 | 2001-04-24 | Polymer Flip Chip Corp. | Flip chip mounting technique |
US6410415B1 (en) | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
US6514796B2 (en) | 1995-05-18 | 2003-02-04 | Hitachi, Ltd. | Method for mounting a thin semiconductor device |
JP2007036236A (en) * | 2005-07-27 | 2007-02-08 | Palo Alto Research Center Inc | Method of forming self-assembled electrical contact structure, self-assembled electrical contact structure, and electrical contact structure |
CN1307704C (en) * | 2003-03-26 | 2007-03-28 | 精工爱普生株式会社 | Method for producing electronic part, electronic part, mounting method for electronic part and electronic device |
-
1992
- 1992-08-18 JP JP21912492A patent/JPH0669278A/en not_active Withdrawn
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6514796B2 (en) | 1995-05-18 | 2003-02-04 | Hitachi, Ltd. | Method for mounting a thin semiconductor device |
US6589818B2 (en) | 1995-05-18 | 2003-07-08 | Hitachi. Ltd. | Method for mounting a thin semiconductor device |
US6531022B1 (en) | 1996-06-07 | 2003-03-11 | Matsushita Electric Industrial Co., Ltd. | Mounting method of semiconductor element |
EP0844657A4 (en) * | 1996-06-07 | 1999-04-14 | Matsushita Electric Ind Co Ltd | Method for mounting semiconductor chip |
US6051093A (en) * | 1996-06-07 | 2000-04-18 | Matsushita Electric Industrial Co., Ltd. | Mounting method of semiconductor element |
WO1997047031A1 (en) * | 1996-06-07 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for mounting semiconductor chip |
EP0844657A1 (en) * | 1996-06-07 | 1998-05-27 | Matsushita Electric Industrial Co., Ltd. | Method for mounting semiconductor chip |
KR100457609B1 (en) * | 1996-06-07 | 2005-01-15 | 마쯔시다덴기산교 가부시키가이샤 | Method for mounting semiconductor chip |
WO1999010928A1 (en) * | 1997-08-21 | 1999-03-04 | Citizen Watch Co., Ltd. | Semiconductor device and method of fabricating the same |
US6219911B1 (en) | 1998-03-23 | 2001-04-24 | Polymer Flip Chip Corp. | Flip chip mounting technique |
US6189208B1 (en) | 1998-09-11 | 2001-02-20 | Polymer Flip Chip Corp. | Flip chip mounting technique |
US6410415B1 (en) | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
CN1307704C (en) * | 2003-03-26 | 2007-03-28 | 精工爱普生株式会社 | Method for producing electronic part, electronic part, mounting method for electronic part and electronic device |
JP2007036236A (en) * | 2005-07-27 | 2007-02-08 | Palo Alto Research Center Inc | Method of forming self-assembled electrical contact structure, self-assembled electrical contact structure, and electrical contact structure |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100384314B1 (en) | Method and device for mounting electronic component on circuit board | |
US6537854B1 (en) | Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed | |
JPH11191569A (en) | Flip chip-mounting method and semiconductor device | |
US20030178132A1 (en) | Method for manufacturing connection structure | |
JP2000113919A (en) | Electrical connection device and electrically connecting method | |
US6528889B1 (en) | Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip | |
JPH0669278A (en) | Connecting method for semiconductor element | |
JPH1126922A (en) | Method for mounting chip | |
US20010053564A1 (en) | Method of manufacturing semiconductor device | |
JP3743716B2 (en) | Flexible wiring board and semiconductor element mounting method | |
JPH0432171A (en) | Electronic device | |
JP2002026071A (en) | Semiconductor device and its manufacturing method, circuit board, and electronic equipment | |
KR100614564B1 (en) | A junction method of a chip bump and a substrate pad using underfill resin and supersonic | |
JPH11135561A (en) | Anisotropic conductive adhesive film, its manufacture, flip-chip mounting method, and flip-chip packaging board | |
JPS6347943A (en) | Method for connecting electronic component | |
JP2000058597A (en) | Method of mounting electronic component | |
KR980013552A (en) | A connection sheet for mutually connecting the electrodes facing each other, and an electrode connection structure and a connection method using the connection sheet | |
JP2000174066A (en) | Method of mounting semiconductor device | |
JP3027171B2 (en) | Electric circuit members | |
JP3337922B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2009032948A (en) | Ic chip, and method of mounting ic chip | |
JPH0636613A (en) | Joint material for electronic parts and electronic equipment using the material | |
JP3494048B2 (en) | Mounting structure and mounting method of electronic component with bump | |
JPH1116946A (en) | Mounting method of semiconductor device | |
JPH0992651A (en) | Semiconductor element and connection method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991102 |