KR100457609B1 - Method for mounting semiconductor chip - Google Patents

Method for mounting semiconductor chip Download PDF

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Publication number
KR100457609B1
KR100457609B1 KR10-1998-0700903A KR19980700903A KR100457609B1 KR 100457609 B1 KR100457609 B1 KR 100457609B1 KR 19980700903 A KR19980700903 A KR 19980700903A KR 100457609 B1 KR100457609 B1 KR 100457609B1
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KR
South Korea
Prior art keywords
semiconductor element
circuit board
bump
conductive paste
electrode
Prior art date
Application number
KR10-1998-0700903A
Other languages
Korean (ko)
Other versions
KR19990036235A (en
Inventor
노리히토 츠카하라
Original Assignee
마쯔시다덴기산교 가부시키가이샤
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Publication date
Application filed by 마쯔시다덴기산교 가부시키가이샤 filed Critical 마쯔시다덴기산교 가부시키가이샤
Publication of KR19990036235A publication Critical patent/KR19990036235A/en
Application granted granted Critical
Publication of KR100457609B1 publication Critical patent/KR100457609B1/en

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract

반도체 소자의 전극과 회로 기판의 회로를 고신뢰성을 가지고 접합하는 것을 가능하게 하는 반도체 소자의 실장 방법을 제공한다.Provided is a method of mounting a semiconductor device, which enables joining a circuit of an electrode of a semiconductor device and a circuit of a circuit board with high reliability.

회로 기판(4)에 형성된 구멍부(8)에 도전성 페이스트(7)를 충전하여 외부 전극 단자(33)를 형성하는 공정과, 외부 전극 단자(33)와 반도체 소자(1)의 전극(2)에 형성된 돌기 범프(3)를 위치 결정하는 공정과, 반도체 소자(1)를 가압하여 구멍부(8)내의 도전성 페이스트(7)와 돌기 범프(3)를 접촉시킴으로써 반도체 소자(1)의 전극(2)과 회로 기판(4)의 외부 전극 단자(33)를 전기적으로 접속하는 공정을 갖는다.Filling the hole 8 formed in the circuit board 4 with the conductive paste 7 to form the external electrode terminal 33, and the external electrode terminal 33 and the electrode 2 of the semiconductor element 1. Positioning the protrusion bumps 3 formed in the electrode, and pressing the semiconductor element 1 to contact the conductive paste 7 and the protrusion bump 3 in the hole 8 to make the electrodes of the semiconductor element 1 ( 2) and the external electrode terminal 33 of the circuit board 4 are electrically connected.

Description

반도체 소자의 실장 방법{METHOD FOR MOUNTING SEMICONDUCTOR CHIP}Method of mounting semiconductor device {METHOD FOR MOUNTING SEMICONDUCTOR CHIP}

종래의 반도체 소자의 실장 방법을 도면에 근거하여 설명한다.A conventional method for mounting a semiconductor element will be described with reference to the drawings.

(종래예 1)(Conventional example 1)

도 16에 종래예 1에 있어서의 반도체 소자를 회로 기판에 실장한 단면도를 도시한다.FIG. 16 is a cross-sectional view of the semiconductor element in the conventional example 1 mounted on a circuit board.

도 16에 있어서, 참조 부호 (1)은 반도체 소자로서, 반도체 소자(1)상에 전극(2)이 형성되고, 전극(2)상에 와이어 본딩법에 의해 금, 구리, 알루미늄, 땜납 등으로 이루어지는 돌기 범프(bump)(금속볼 범프)가 형성되어 있다.In Fig. 16, reference numeral 1 denotes a semiconductor element in which an electrode 2 is formed on the semiconductor element 1, and gold, copper, aluminum, solder, or the like is formed on the electrode 2 by a wire bonding method. Protruding bumps (metal ball bumps) are formed.

또한, 참조 부호 (4)는 절연성 기체(基體)로 이루어지는 회로 기판으로서, 이 회로 기판(4)상에 배선으로 되는 동박(銅箔)(5)이 형성되고, 또한 회로 기판(4)상에 구리 도금된 외부 전극 단자(6)가 형성되며, 회로 기판내를 도통시키기 위하여 회로 기판(4)내에 형성된 관통 구멍부(hole)(8)에 도전성 페이스트(7)가 충전되어 있다.Reference numeral 4 denotes a circuit board made of an insulating base, and copper foil 5 serving as a wiring is formed on the circuit board 4, and on the circuit board 4. Copper plated external electrode terminals 6 are formed, and conductive paste 7 is filled in through holes 8 formed in the circuit board 4 to conduct the circuit boards.

또한, 참조 부호 (22)는 페놀이나 에폭시계 수지에, 은, 금, 니켈, 카본 등의 도전 분말을 균일 분산한 도전성 페이스트(도전성 접착제)로서, 회로 기판(4)의 외부 전극 단자(6)와 반도체 소자(1)의 전극(2)을 돌기 범프(15)를 거쳐 전기적으로 접속하고 있으며, 또한 회로 기판(4) 위와 반도체 소자(1) 사이에는 에폭시계 수지(20)가 충전되어 있다.In addition, reference numeral 22 denotes an electrically conductive paste (conductive adhesive) in which conductive powders such as silver, gold, nickel, and carbon are uniformly dispersed in phenol or epoxy resin, and the external electrode terminal 6 of the circuit board 4 is represented. And the electrode 2 of the semiconductor element 1 are electrically connected via the bump bumps 15, and an epoxy resin 20 is filled between the circuit board 4 and the semiconductor element 1.

이상과 같이 구성된 반도체 소자의 실장 방법을 설명한다.The mounting method of the semiconductor element comprised as mentioned above is demonstrated.

반도체 소자(1)의 각 전극(2)상에 형성된 돌기 범프(15)에, 전사법에 의해 도전성 페이스트(22)를 전사한 후, 실장해야 할 회로 기판(4)의 외부 전극 단자(6)에 합치되도록 적재하고, 그 후 가열하여 도전성 페이스트(22)를 경화시켜, 반도체 소자(1)의 전극(2)과 회로 기판(4)의 외부 전극 단자(6)를 전기적으로 접속하고 있다. 그리고, 접속 후에 반도체 소자(1)와 회로 기판(4) 사이의 간격에 에폭시계 수지(20)를 충전하고, 그 경화 수축력을 이용하여 도전성 페이스트(22)의 도전 분말이 연속적으로 접촉될 수 있도록 하여, 전기적, 기계적 신뢰성을 확보하고 있다.After transferring the conductive paste 22 to the projection bumps 15 formed on the electrodes 2 of the semiconductor element 1 by the transfer method, the external electrode terminals 6 of the circuit board 4 to be mounted. The conductive paste 22 is cured by heating so as to conform to the above, and the electrode 2 of the semiconductor element 1 and the external electrode terminal 6 of the circuit board 4 are electrically connected to each other. After the connection, the epoxy resin 20 is filled in the gap between the semiconductor element 1 and the circuit board 4 so that the conductive powder of the conductive paste 22 can be continuously contacted by using the curing shrinkage force. To ensure electrical and mechanical reliability.

(종래예 2)(Conventional example 2)

도 17에 종래예 2에 있어서의 반도체 소자를 회로 기판에 실장한 단면도를 도시한다. 상기 도 16의 구성과 동일한 구성에는 동일한 부호를 부여하고 그 설명을 생략한다.17 is a cross-sectional view of the semiconductor element mounted in a conventional example 2 mounted on a circuit board. The same code | symbol is attached | subjected to the structure same as the structure of FIG. 16, and the description is abbreviate | omitted.

도 17에 있어서, 참조 부호 (23)은 전극(2)상에 전기 도금법에 의해 형성된 금속 범프로서, 금속 범프(23)상에, 예를 들면 구리 도금이 실시되고, 그 위에 금 도금(24)이 되어 있다. 참조 부호 (25)는 외부 전극 단자, 참조 부호 (16)은 반도체 소자(1)의 활성(active)면을 보호하는 패시베이션(passivation)막이다.In Fig. 17, reference numeral 23 denotes a metal bump formed on the electrode 2 by electroplating, for example, copper plating is performed on the metal bump 23, and gold plating 24 is placed thereon. Has become. Reference numeral 25 denotes an external electrode terminal, and reference numeral 16 denotes a passivation film that protects the active surface of the semiconductor element 1.

이상과 같이 구성된 반도체 소자의 실장 방법을 설명한다.The mounting method of the semiconductor element comprised as mentioned above is demonstrated.

반도체 소자(1)의 각 전극(2)상에 형성된 금속 범프(23)에 전사법에 의해 도전성 페이스트(22)를 전사한 후, 실장해야 할 회로 기판(4)의 외부 전극 단자(25)에 합치되도록 적재하고, 그 후 가열하여 도전성 페이스트(22)를 경화시켜 반도체 소자(1)의 전극(2)과 회로 기판(4)의 외부 전극 단자(25)를 전기적으로 접속하고 있다. 그리고, 접속 후에 반도체 소자(1)와 회로 기판(4) 사이의 간격에 에폭시계 수지(20)를 충전하고, 그 경화 수축력을 이용하여 도전성 페이스트(22)의 도전 분말이 연속적으로 접촉될 수 있도록 하여, 전기적, 기계적 신뢰성을 확보하고 있다.After the conductive paste 22 is transferred to the metal bumps 23 formed on the electrodes 2 of the semiconductor element 1 by the transfer method, the conductive paste 22 is transferred to the external electrode terminals 25 of the circuit board 4 to be mounted. The conductive paste 22 is cured by being loaded so as to coincide therewith, and the electrode 2 of the semiconductor element 1 is electrically connected to the external electrode terminal 25 of the circuit board 4. After the connection, the epoxy resin 20 is filled in the gap between the semiconductor element 1 and the circuit board 4 so that the conductive powder of the conductive paste 22 can be continuously contacted by using the curing shrinkage force. To ensure electrical and mechanical reliability.

(종례예 3)(Example 3)

도 18에 종래예 3에 있어서의 반도체 소자를 회로 기판에 실장한 단면도를 도시한다. 상기 도 16, 도 17의 구성과 동일한 구성에는 동일한 부호를 부여하고 그 설명을 생략한다.18 is a cross-sectional view of the semiconductor element mounted in the conventional example 3 mounted on a circuit board. The same code | symbol is attached | subjected to the structure similar to the structure of FIG. 16, FIG. 17, and the description is abbreviate | omitted.

도 18에 있어서, 참조 부호 (3)은 전극(2) 위에, 도금법에 의해 형성된 돌기 범프(돌기 전극), 참조 부호 (26)은 절연성 접착제 필름으로서, 절연성 접착제 필름(26)내에는 니켈, 땜납, 카본 등으로 이루어지는 도전 입자(27)가 균일하게 분산되어 있다.In Fig. 18, reference numeral 3 denotes a projection bump (protrusion electrode) formed on the electrode 2 by the plating method, and reference numeral 26 denotes an insulating adhesive film, and nickel and solder are included in the insulating adhesive film 26. The conductive particles 27 made of carbon or the like are uniformly dispersed.

이상과 같이 구성된 반도체 소자의 실장 방법을 설명한다.The mounting method of the semiconductor element comprised as mentioned above is demonstrated.

절연성 접착제 필름(26)을 반도체 소자(1) 및 회로 기판(4)의 외부 전극 단자(25) 사이에 두고 위치 정렬한 후, 가열, 가압을 동시에 실행한다. 이에 따라, 접착제 필름(26)은 용융하여 전극(25)간의 공간에서 유동되고, 도전 입자(27)는 돌기 범프(3)와 외부 전극 단자(25)에 의해 고정 유지되어 도통한다. 한편, 공간에서는 도전 입자(27)가 접착제내에서 분산된 상태를 유지하기 때문에 절연성이 확보된다. 접착제 필름(26)은 냉각하면 경화하여, 반도체 소자(1)와 회로 기판(4)을 고정시켜 접속 신뢰성을 확보한다.After arrange | positioning the insulating adhesive film 26 between the semiconductor element 1 and the external electrode terminal 25 of the circuit board 4, heating and pressurization are performed simultaneously. Thereby, the adhesive film 26 melts and flows in the space between the electrodes 25, and the electrically-conductive particle 27 is fixed and conducted by the bump bump 3 and the external electrode terminal 25, and is electrically conductive. On the other hand, in the space, since the conductive particles 27 are kept dispersed in the adhesive, insulation is ensured. The adhesive film 26 hardens when cooled, and fixes the semiconductor element 1 and the circuit board 4, and ensures connection reliability.

그러나, 상기 종래예 1(또는 종래예 2)의 반도체 소자의 실장 방법에서는, 도 19에 도시하는 바와 같이, 전사법에 의해 도전성 페이스트막(28)을 돌기 범프(15)에 전사하여, 범프(15)를 회로 기판(4)의 외부 전극(6)에 접합할 때에, 전사 도전성 페이스트(22)량의 제어가 곤란하여, 조금이라도 많으면 전극(2)간이 도전성 페이스트(22)에 의해 접속되어 단락 회로(30)가 형성되어 버린다고 하는 문제가 있었다. 또한, 회로 기판(4)이 조금이라도 휘어져 있으면, 반도체 소자(1)의 전극(2)과 회로 기판(4)의 외부 전극 단자(6)가 도전성 페이스트(22)를 거쳐 접촉하지 않아, 전기적으로 개방 상태가 된다고 하는 문제가 있었다.However, in the method of mounting the semiconductor element of the conventional example 1 (or conventional example 2), as shown in FIG. 19, the conductive paste film 28 is transferred to the projection bump 15 by the transfer method, and the bump ( When bonding 15 to the external electrode 6 of the circuit board 4, it is difficult to control the amount of the transfer conductive paste 22, and if there is even a little, the electrodes 2 are connected by the conductive paste 22 and short-circuited. There is a problem that the circuit 30 is formed. In addition, if the circuit board 4 is bent at least slightly, the electrode 2 of the semiconductor element 1 and the external electrode terminal 6 of the circuit board 4 do not come into contact with each other via the conductive paste 22, and electrically There was a problem of being in an open state.

또한, 도 20에 도시하는 바와 같이, 에폭시계 수지(20)를 반도체 소자(1)와 회로 기판(4)의 간극에 충전할 때에, 시린지(syringe)(31)에 봉입된 에폭시계 수지(20)를 반도체 소자(1)의 주변부에서부터 주입해 가기 때문에, 주입 시간이 약 10분 이상 걸려, 반도체 소자(1)의 생산 라인의 택트 타임(tact time) 단축에 장해 요인으로 된다고 하는 문제가 있었다.As shown in FIG. 20, when the epoxy resin 20 is filled in the gap between the semiconductor element 1 and the circuit board 4, the epoxy resin 20 encapsulated in the syringe 31. ) Is injected from the periphery of the semiconductor element 1, so that the injection time takes about 10 minutes or more, which causes a problem of shortening the tact time of the production line of the semiconductor element 1.

또한, 상기 종래예 3의 반도체 소자의 실장 방법에서는, 도전 입자(27)를 반도체 소자(1)의 전극(2)과 회로 기판(4)의 전극(25) 사이에 고정 유지함으로써 도통되기 때문에, 도 21에 도시하는 바와 같이, 회로 기판(4)에 조금이라도 휘어짐·굴곡(A)이 있으면, 도전 입자(27)가 접착제(26)내에 분산된 상태 그대로 반도체 소자(1)의 돌기 범프(3)와 회로 기판(4)의 전극(25)에 접촉하지 않아, 전기적으로 개방 상태가 된다고 하는 문제점이 있었다. 또, 종래예 3의 실장 방법은, 휘어짐·굴곡이 적은 유리 기판을 대상으로 하여 이용되고 있으며, 수지 기판에는 이용하고 있지 않는 것이 현재 실정이다.In addition, in the method of mounting the semiconductor device according to the conventional example 3, since the conductive particles 27 are conductively held between the electrode 2 of the semiconductor device 1 and the electrode 25 of the circuit board 4, the conductive particles 27 are conducted. As shown in FIG. 21, if there is any bending and bending A in the circuit board 4, the projection bumps 3 of the semiconductor element 1 are in a state in which the conductive particles 27 are dispersed in the adhesive 26. ) And the electrode 25 of the circuit board 4 do not come into contact with each other, so that there is a problem of being electrically open. Moreover, the mounting method of the prior art example 3 is used for the glass substrate with few curvature and curvature, and it is the present situation that it is not used for a resin substrate.

그래서, 본 발명의 목적은, 전극간에 있어서의 단락이나 개방이라는 불량이 발생하지 않고, 전기적 신뢰성이 높은 실장이 실행되어 봉지 공정(sealing process)의 시간을 대폭적으로 삭감할 수 있고, 반도체 소자 생산 라인의 택트 타임(tact time)을 단축할 수 있도록 하는 반도체 소자의 실장 방법을 제공하는 데 있다.Therefore, the object of the present invention is that a short circuit or an opening between the electrodes does not occur, and mounting with high electrical reliability is performed, which can greatly reduce the time of the sealing process, and the semiconductor element production line The present invention provides a method for mounting a semiconductor device that can shorten the tact time.

발명의 개시Disclosure of the Invention

상기 목적을 달성하기 위하여 본 발명의 반도체 소자의 실장 방법은, 회로 기판의 회로와 반도체 소자의 전극을 접속하는 상기 회로 기판의 개소에 관통 구멍부를 형성하는 공정과, 상기 관통 구멍부에 도전성 페이스트를 충전하여 외부 전극단자를 형성하는 공정과, 상기 반도체 소자의 전극에 돌기 범프를 형성하는 공정과, 상기 외부 전극 단자와 반도체 소자의 전극에 형성된 돌기 범프를 위치 결정하는 공정과, 상기 반도체 소자를 가압하여, 상기 관통 구멍부의 상기 도전성 페이스트와 상기 돌기 범프를 접촉시켜, 상기 반도체 소자의 상기 전극과 상기 회로 기판의 상기 외부 전극 단자를 전기적으로 접속시키는 공정을 갖는 것을 특징으로 하는 것이다.In order to achieve the above object, a method of mounting a semiconductor device according to the present invention includes a step of forming a through hole in a portion of the circuit board connecting a circuit of a circuit board and an electrode of the semiconductor element, and a conductive paste in the through hole. Forming an external electrode terminal by charging, forming a bump on the electrode of the semiconductor element, positioning a bump on the electrode of the external electrode terminal and the semiconductor element, and pressurizing the semiconductor element And electrically connecting the electrode of the semiconductor element with the external electrode terminal of the circuit board by bringing the conductive paste and the protrusion bump into contact with each other.

상기 반도체 소자의 실장 방법에 의해, 회로 기판의 관통 구멍부내의 충전된 도전성 페이스트와 반도체 소자의 전극에 형성한 돌기 범프를 접촉시켜서, 상기 반도체 소자의 전극과 회로 기판의 외부 전극 단자를 전기적으로 접속함으로써, 전극간에서의 단락이나 개방이라고 하는 불량이 발생하지 않아, 전기적 신뢰성이 높은 실장을 실행할 수 있다.By the method of mounting the semiconductor element, the electrically conductive paste in the through hole of the circuit board is brought into contact with the protrusion bump formed on the electrode of the semiconductor element, thereby electrically connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board. As a result, a defect such as short circuit or opening between the electrodes does not occur, and mounting with high electrical reliability can be performed.

본 발명은 반도체 소자의 회로 기판에 고신뢰성, 고밀도를 유지하면서 플립 칩형 반도체 소자를 실장하는 반도체 소자의 실장 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting method for mounting a flip chip type semiconductor device while maintaining high reliability and high density on a circuit board of the semiconductor device.

도 1은 본 발명의 실시예 1에 있어서의 실장 후의 반도체 소자와 회로 기판의 접합 단면도,1 is a cross sectional view of a junction between a semiconductor element and a circuit board after mounting in Example 1 of the present invention;

도 2는 본 발명의 실시예 1에 있어서의 실장의 공정을 순서대로 도시한 도면,Fig. 2 is a diagram showing the process of mounting in Example 1 of the present invention in order;

도 3은 본 발명의 실시예 1에 있어서의 실장 후의 반도체 소자와 회로 기판의 접합 단면도,3 is a cross sectional view of a junction between a semiconductor element and a circuit board after mounting in Example 1 of the present invention;

도 4는 본 발명의 실시예 1에 있어서의 실장 후의 반도체 소자와 회로 기판의 접합 단면도,4 is a cross sectional view of a junction between a semiconductor element and a circuit board after mounting in Example 1 of the present invention;

도 5는 본 발명의 실시예 2에 있어서의 와이어 본딩법의 공정을 순서대로 도시한 도면,Fig. 5 is a view showing the steps of the wire bonding method in the second embodiment of the present invention in order;

도 6은 본 발명의 실시예 2에 있어서의 와이어 본딩법에 의해 형성된 돌기 범프의 측면도,6 is a side view of the bumps formed by the wire bonding method in the second embodiment of the present invention;

도 7은 본 발명의 실시예 2에 있어서의 와이어 본딩법에 의해 형성된 2단 돌기 형상 돌기 범프의 측면도,7 is a side view of a two-stage protrusion-shaped protrusion bump formed by the wire bonding method according to the second embodiment of the present invention;

도 8은 본 발명의 실시예 2에 있어서의 실장 공정을 순서대로 도시한 도면,Fig. 8 is a view showing the mounting process in Example 2 of the present invention in order;

도 9는 본 발명의 실시예 3에 있어서의 실장 공정을 도시한 도면,9 is a diagram showing a mounting process in a third embodiment of the present invention;

도 10은 본 발명의 실시예 4에 있어서의 실장 공정을 도시한 도면,10 is a diagram showing a mounting step in a fourth embodiment of the present invention;

도 11은 본 발명의 실시예 5에 있어서의 실장 공정을 도시한 도면,11 is a diagram showing a mounting step in a fifth embodiment of the present invention;

도 12는 본 발명의 실시예 6에 있어서의 실장 공정을 도시한 도면,12 is a diagram showing a mounting process in a sixth embodiment of the present invention;

도 13은 본 발명의 실시예 6에 있어서의 실장 후의 반도체 소자와 회로 기판의 접합 단면도,Fig. 13 is a cross sectional view of a junction between a semiconductor element and a circuit board after mounting in Example 6 of the present invention;

도 14는 본 발명의 실시예 7에 있어서의 실장 공정을 순서대로 도시한 도면,Fig. 14 is a view showing the mounting steps in the seventh embodiment of the present invention in order;

도 15는 본 발명의 실시예 8에 있어서의 실장 공정을 순서대로 도시한 도면,Fig. 15 is a view showing the mounting steps in the eighth embodiment of the present invention in order;

도 16은 종래의 반도체 소자의 실장 방법에 의한 실장 후의 반도체 소자와 회로 기판의 접합 단면도,16 is a cross sectional view of a junction between a semiconductor element and a circuit board after mounting by a conventional semiconductor element mounting method;

도 17은 종래의 반도체 소자의 실장 방법에 의한 실장 후의 반도체 소자와 회로 기판의 접합 단면도,17 is a cross sectional view of a junction between a semiconductor element and a circuit board after mounting by a conventional semiconductor element mounting method;

도 18은 종래의 반도체 소자의 실장 방법에 의한 실장 후의 반도체 소자와 회로 기판의 접합 단면도,18 is a cross sectional view of a junction between a semiconductor element and a circuit board after mounting by a conventional semiconductor element mounting method;

도 19는 종래의 실장 공정을 순서대로 도시한 도면,19 is a view showing a conventional mounting process in order;

도 20은 종래의 실장 방법의 과제를 설명하는 도면,20 is a view for explaining problems of the conventional mounting method;

도 21은 종래의 실장 방법의 과제를 설명하는 도면이다.It is a figure explaining the subject of the conventional mounting method.

발명을 실시하기 위한 최선의 형태Best Mode for Carrying Out the Invention

본 발명의 청구항 1에 기재된 발명은, 회로 기판의 회로와 반도체 소자의 전극을 접속하는 상기 회로 기판의 개소에 관통 구멍부를 형성하는 공정과, 상기 관통 구멍부에 도전성 페이스트를 충전하여 외부 전극 단자를 형성하는 공정과, 상기 반도체 소자의 전극에 돌기 범프를 형성하는 공정과, 상기 외부 전극 단자와 반도체 소자의 전극에 형성된 돌기 범프를 위치 결정하는 공정과, 상기 반도체 소자를 가압하여 상기 관통 구멍부내의 상기 도전성 페이스트와 상기 돌기 범프를 접촉시켜, 상기 반도체 소자의 상기 전극과 상기 회로 기판의 상기 외부 전극 단자를 전기적으로 접속하는 공정을 갖는 것을 특징으로 하는 반도체 소자의 실장 방법으로서, 돌기 범프가 회로 기판의 관통 구멍부내에서 도전성 페이스트와 접촉하여, 전기적으로 접속되기 때문에, 개방이나 단락의 발생이 없다고 하는 작용을 갖는다.According to the first aspect of the present invention, there is provided a step of forming a through hole in a portion of the circuit board connecting a circuit of a circuit board and an electrode of a semiconductor element, and filling the through hole in a conductive paste to form an external electrode terminal. Forming the projections, forming projection bumps on the electrodes of the semiconductor element, positioning the projection bumps formed on the external electrode terminals and the electrodes of the semiconductor element, and pressing the semiconductor elements in the through hole portion. A process for mounting a semiconductor element comprising the step of bringing the conductive paste into contact with the protrusion bump to electrically connect the electrode of the semiconductor element with the external electrode terminal of the circuit board. Is electrically connected in contact with the conductive paste in the through hole of the In, it has an effect of no occurrence of an open or short circuit.

청구항 2에 기재된 발명은, 청구항 1에 기재된 반도체 소자의 실장 방법에 있어서, 반도체 소자의 전극에 형성되어 있는 돌기 범프는, 와이어 본딩법에 의해 형성되는 금속볼 범프인 것을 특징으로 하는 반도체 소자의 실장 방법으로서, 돌기범프를 전기 도금법에 의해 형성한 경우, 최대라도 25㎛ 정도 높이의 낮은 범프밖에 형성할 수 없는데 반하여, 와이어 본딩법에 따르면 50㎛ 이상의 높이가 높은 범프를 형성할 수 있기 때문에, 회로 기판의 관통 구멍부의 도전성 페이스트에 매립되는 범프의 양이 많아져서, 보다 신뢰성이 높은 실장이 가능하다고 하는 작용을 갖는다.In the invention according to claim 2, in the method for mounting a semiconductor device according to claim 1, the bumps formed on the electrodes of the semiconductor elements are metal ball bumps formed by a wire bonding method. As a method, when the bumps are formed by the electroplating method, only bumps having a height of about 25 µm can be formed at most, whereas bumps having a height of 50 µm or more can be formed by the wire bonding method. The amount of bumps embedded in the conductive paste of the through-hole portion of the substrate increases, which has the effect of enabling more reliable mounting.

청구항 3에 기재된 발명은, 청구항 1 또는 2에 기재된 반도체 소자의 실장 방법에 있어서, 반도체 소자를 가압하여, 회로 기판 관통 구멍부의 도전성 페이스트와 반도체 소자 전극상의 돌기 범프를 접촉시킨 후, 가열 도구(tool)로 상기 반도체 소자 또는 회로 기판의 적어도 한쪽을 가열하여 상기 도전성 페이스트를 경화시키는 공정을 부가하는 것을 특징으로 하는 반도체 소자의 실장 방법으로서, 도전성 페이스트를 경화함으로써 반도체 소자와 회로 기판과의 고정이 보다 강고해져서 보다 신뢰성이 높은 접합이 가능하고, 또한 종래 도전성 페이스트의 경화는 모듈을 평로(open hearth)에 넣고 일괄(batch) 처리하고 있는 데 반하여, 접합과 동시에 동일 설비로 실행할 수 있기 때문에, 반도체 소자의 생산 라인의 택트 타임 단축으로 이어질 수 있다고 하는 작용을 갖는다.In the invention according to claim 3, in the method for mounting a semiconductor device according to claim 1 or 2, a heating tool (tool) is pressed after contacting the conductive paste of the circuit board through hole and the bump on the semiconductor element electrode. And a step of heating at least one of the semiconductor element or the circuit board to cure the conductive paste, wherein the mounting of the semiconductor element is more secured by curing the conductive paste. It is possible to bond more securely and to make more reliable bonding, and the conventional conductive paste is hardened by placing the module in an open hearth and batch processing. That can lead to shortening of tact time of production line Has the.

청구항 4에 기재된 발명은, 청구항 1 내지 청구항 3 중 어느 한 항에 기재된 반도체 소자의 실장 방법에 있어서, 반도체 소자의 전극과 회로 기판의 외부 전극 단자를 접속한 후, 상기 반도체 소자와 상기 회로 기판과의 간극에 에폭시계 수지를 유입하여 봉지하는 공정을 부가하는 것을 특징으로 하는 반도체 소자의 실장 방법으로서, 반도체 소자의 활성면 및 전극의 표면이 에폭시계 수지에 의해 보호되기때문에, 보다 접속 신뢰성이 증대된다고 하는 작용을 갖는다.The invention according to claim 4 is the semiconductor device mounting method according to any one of claims 1 to 3, wherein after connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board, A method of mounting a semiconductor device comprising adding an epoxy resin to the gap between and sealing the epoxy resin, wherein the active surface of the semiconductor element and the surface of the electrode are protected by an epoxy resin, thereby increasing connection reliability. It has the effect of becoming.

청구항 5에 기재된 발명은, 회로 기판의 회로와 반도체 소자의 전극을 접속하는 상기 회로 기판의 개소에 관통 구멍부를 형성하는 공정과, 상기 관통 구멍부에 도전성 페이스트를 충전하여 외부 전극 단자를 형성하는 공정과, 상기 반도체 소자의 전극에 돌기 범프를 형성하는 공정과, 상기 외부 전극 단자가 형성된 회로 기판 위, 또는 상기 반도체 소자의 돌기 범프 위에 열 경화계, 또는 열 가소계, 또는 열 경화와 열 가소의 혼합계 수지로 이루어지는 접착제 시트를 배치하는 공정과, 상기 외부 전극 단자와 반도체 소자의 전극에 형성된 돌기 범프를 위치 결정하는 공정과, 상기 반도체 소자를 가압하여, 상기 돌기 범프가 상기 접착제 시트를 뚫고 나와 상기 관통 구멍부내의 상기 도전성 페이스트와 상기 돌기 범프가 접촉됨으로써, 상기 반도체 소자의 상기 전극과 상기 회로 기판의 상기 외부 전극 단자를 전기적으로 접속하는 공정과, 가열 도구에 의해 상기 반도체 소자를 가열하여 상기 접착제 시트를 용융, 경화하는 공정을 갖는 것을 특징으로 하는 반도체 소자의 실장 방법으로서, 접착제 시트가 용융·경화된 후, 반도체 소자의 활성면 및 전극의 표면을 보호하기 때문에, 보다 접속의 신뢰성이 증대되고, 또한 접착제 시트의 경우, 가압·경화에 필요한 시간이 약 30초로서, 에폭시계 수지의 경화 시간인 약 4시간에 비해 대폭 짧아져, 반도체 소자 생산 라인의 택트 타임 단축으로 연결된다고 하는 작용을 갖는다.Invention of Claim 5 is a process of forming a through-hole part in the said circuit board which connects the circuit of a circuit board and the electrode of a semiconductor element, and the process of forming an external electrode terminal by filling an electrically conductive paste in the said through-hole part. And a step of forming a bump on the electrode of the semiconductor element, and a thermosetting system or a thermoplastic system on the circuit board on which the external electrode terminal is formed or on the bump of the semiconductor element, Arranging an adhesive sheet made of a mixed resin, positioning a protrusion bump formed on the external electrode terminal and an electrode of the semiconductor element, pressurizing the semiconductor element, and the protrusion bump penetrating the adhesive sheet. The semiconductor element is brought into contact with the conductive paste in the through hole by the protrusion bump. And a step of electrically connecting the electrode and the external electrode terminal of the circuit board, and a step of heating the semiconductor element with a heating tool to melt and cure the adhesive sheet. After the adhesive sheet is melted and cured, the active surface of the semiconductor element and the surface of the electrode are protected, so that the reliability of the connection is increased, and in the case of the adhesive sheet, the time required for pressing and curing is about 30 seconds. Compared with about 4 hours which is the hardening time of epoxy resin, it becomes much shorter and it has the effect of being connected by shortening the tact time of a semiconductor element production line.

이하, 본 발명의 실시예를 도면에 근거하여 설명한다. 또, 종래예의 도 16 내지 도 18의 구성과 동일한 구성에는 동일한 부호를 부여하고 그 설명을 생략한다.EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described based on drawing. In addition, the same code | symbol is attached | subjected to the structure similar to the structure of FIGS. 16-18 of a prior art example, and the description is abbreviate | omitted.

(실시예 1)(Example 1)

도 1은 본 발명의 실시예 1에 있어서의 반도체 소자를 실장한 회로 기판의 단면도이다.1 is a cross-sectional view of a circuit board mounted with a semiconductor element according to the first embodiment of the present invention.

도시하는 바와 같이, 반도체 소자(1)의 전극(2)상에 형성된 돌기 범프(3)는, 회로 기판(4)의 관통 구멍부(8)에 충전된 도전성 페이스트에 매립되는 형태로 접촉되어 있으며, 회로 기판(4)의 외부 전극 단자(6)와 반도체 소자(1)의 전극(2)이 전기적으로 접속되어 있다. 도 2의 공정도에 따라서 본 발명의 반도체 소자의 실장 방법을 설명한다.As shown in the drawing, the protrusion bumps 3 formed on the electrodes 2 of the semiconductor element 1 are in contact with each other in the form of being embedded in a conductive paste filled in the through hole 8 of the circuit board 4. The external electrode terminal 6 of the circuit board 4 and the electrode 2 of the semiconductor element 1 are electrically connected. The mounting method of the semiconductor element of this invention is demonstrated according to the process diagram of FIG.

우선, 회로 기판(4)의 외부 전극 단자(6)와 반도체 소자(1)의 전극(2)을 접속시키는, 회로 기판(4)의 개소에 관통 구멍부(8)를 형성하고, 도 2a에 도시하는 바와 같이, 도전성 페이스트(7)를 스퀴지(9)를 이동시킴으로써 상기 회로 기판(4)의 관통 구멍부(8)에 인쇄·충전하여 회로 기판(4)의 외부 전극 단자(33)를 형성한다.First, a through hole 8 is formed in a portion of the circuit board 4 that connects the external electrode terminal 6 of the circuit board 4 and the electrode 2 of the semiconductor element 1, As shown in the figure, the conductive paste 7 is moved and squeegee 9 to print and charge the through hole 8 of the circuit board 4 to form the external electrode terminal 33 of the circuit board 4. do.

다음에, 도 2b에 도시하는 바와 같이, 반도체 소자(1)를 흡착 노즐(10)에 흡착시켜, 돌기 범프(3)와 관통 구멍부(8)에 충전된 도전성 페이스트(7)에 의해 형성된 회로 기판(4)의 외부 전극 단자(33)와의 위치 맞춤을 행한다.Next, as shown in FIG. 2B, a circuit formed by the conductive paste 7 filled in the protrusion bump 3 and the through hole 8 by adsorbing the semiconductor element 1 to the adsorption nozzle 10. Positioning with the external electrode terminal 33 of the board | substrate 4 is performed.

다음에, 도 2c에 도시하는 바와 같이, 반도체 소자(1)를 흡착 노즐(10)에 의해 가압하여, 도 2d에 도시하는 바와 같이, 돌기 범프(3)를 회로 기판(4)의 관통구멍부(8)에 충전된 도전성 페이스트(7)에 매립시킨다.Next, as shown in FIG. 2C, the semiconductor element 1 is pressurized by the adsorption nozzle 10, and as shown in FIG. 2D, the protrusion bump 3 passes through the through hole portion of the circuit board 4. It embeds in the electrically conductive paste 7 filled in (8).

그 결과, 반도체 소자(1)의 돌기 범프(3)가 회로 기판(4)의 관통 구멍부내에서 도전성 페이스트(7)와 접촉하여 전기적으로 접속된다.As a result, the projection bumps 3 of the semiconductor element 1 are in contact with the conductive paste 7 in the through-holes of the circuit board 4 to be electrically connected.

또한, 회로 기판(4)은, 도 3에 도시하는 바와 같이, 내측 비아홀에 의해 기판내 층간의 도통이 이루어진 다층 기판이어도 무방하고, 도 4에 도시하는 바와 같이 스루 홀에 의해 층간의 도통이 이루어진 다층 기판이어도 무방하다.As shown in FIG. 3, the circuit board 4 may be a multilayer substrate in which conduction between layers in the substrate is made by the inner via hole, and as shown in FIG. 4, the conduction between layers is achieved by the through hole. It may be a multilayer substrate.

본 실시예 1에 따르면, 반도체 소자(1)의 전극(2)상에 형성된 돌기 범프(3)가 회로 기판(4)의 관통 구멍부(8)내에서 도전성 페이스트(7)에 매립되어 접촉하여 전기적으로 접속되기 때문에, 단락이 발생하지 않으며, 또한 회로 기판(4)의 휘어짐, 굴곡에 대한 허용 범위도 넓어져, 개방이 발생하는 일이 없어, 높은 신뢰성을 가지고 반도체 소자(1)와 회로 기판(4)을 접합할 수 있다.According to the first embodiment, the protrusion bumps 3 formed on the electrodes 2 of the semiconductor element 1 are buried in the conductive paste 7 in the through-holes 8 of the circuit board 4 to be in contact with each other. Since it is electrically connected, a short circuit does not occur, and the permissible range for bending and bending of the circuit board 4 is also widened, and opening does not occur, and the semiconductor element 1 and the circuit board have high reliability. (4) can be bonded.

(실시예 2)(Example 2)

도 5는 본 발명의 실시예 2에 있어서의 와이어 본딩법을 이용한, 반도체 소자의 전극상의 돌기 범프의 형성 방법을 나타내는 공정도이며, 도 5를 참조하면서 와이어 본딩법을 설명한다.FIG. 5 is a process chart showing a method of forming a bump on an electrode of a semiconductor element using the wire bonding method according to the second embodiment of the present invention. The wire bonding method will be described with reference to FIG. 5.

우선, 도 5a에 도시하는 바와 같이, 금, 구리, 알루미늄, 땜납 등으로 제작된 금속 와이어(11)를 세라믹이나 루비로 만들어진 캐필러리(capillary)(13)에 통과시키고, 통과시킨 금속 와이어(11)의 선단과 토치라고 불리우는 전극(14)과의 사이에서 방전시켜 금속볼(12)을 형성한다.First, as shown in FIG. 5A, a metal wire 11 made of gold, copper, aluminum, solder, or the like is passed through a capillary 13 made of ceramic or ruby, and passed through a metal wire ( A metal ball 12 is formed by discharging between the tip of 11) and an electrode 14 called a torch.

다음에, 도 5b에 도시하는 바와 같이, 예열되어 있는 반도체 소자(1)의 전극(2) 위에 상기 금속볼(12)을 가압하여, 초음파 진동을 가해 온도, 압력, 초음파 진동의 작용에 의해서 금속볼(12)을 전극(2)에 접합시킨다.Next, as shown in FIG. 5B, the metal ball 12 is pressed on the electrode 2 of the preheated semiconductor element 1, and ultrasonic vibration is applied to the metal by the action of temperature, pressure, and ultrasonic vibration. The ball 12 is bonded to the electrode 2.

다음에, 도 5c에 도시하는 바와 같이, 캐필러리(13)를 연직 방향으로 상승시키고, 금속 와이어(11)를 잡아 당기는 것에 의해, 도 6에 도시하는, 금속볼에 의한 범프(15)를 형성한다.Next, as shown in FIG. 5C, the bump 15 by the metal balls shown in FIG. 6 is lifted by raising the capillary 13 in the vertical direction and pulling the metal wire 11. Form.

그리고, 도 5d에 도시하는 바와 같이, 캐필러리(13)를 상승시킨 후, 금속 와이어(11)를 잡아당기지 않고 캐필러리(13)를 옆으로 비껴 하강시키고, 금속 와이어(11)를 금속볼(12)상에 접촉시켜 온도와 압력, 혹은 온도, 압력, 초음파 진동의 작용에 의해 금속 와이어(11)를 금속볼(12)에 접합한다.Then, as shown in FIG. 5D, after the capillary 13 is raised, the capillary 13 is deflected to the side without pulling the metal wire 11, and the metal wire 11 is lowered. The metal wire 11 is joined to the metal ball 12 by contact with the ball 12 by the action of temperature and pressure or by temperature, pressure and ultrasonic vibration.

다음에, 도 5e에 도시하는 바와 같이, 캐필러리(13)를 상승시키고, 금속 와이어(11)를 잡아당겨서, 도 5f 및 도 7에 도시하는, 금속볼에 의한 2단 돌기 형상 범프(15)를 형성한다.Next, as shown in FIG. 5E, the capillary 13 is raised, the metal wire 11 is pulled out, and the two-stage protruding bumps 15 by the metal balls shown in FIGS. 5F and 7 are shown. ).

상기 방법에 의해 반도체 소자(1)의 전극(2)상에 금속볼에 의한 돌기 범프(15)를 형성한 후, 도 8에 도시하는 방법에 의해 반도체 소자(1)와 회로 기판(4)을 접합한다.After forming the bumps 15 by the metal balls on the electrodes 2 of the semiconductor element 1 by the above method, the semiconductor element 1 and the circuit board 4 are formed by the method shown in FIG. Bond.

도 8의 실장 방법은 상기 실시예 1에서 설명한 방법과 마찬가지이므로 설명을 생략한다.Since the mounting method of FIG. 8 is the same as the method described in Embodiment 1, description thereof is omitted.

본 실시예 2에 따르면, 실시예 1에서의 효과에 덧붙여, 돌기 범프를 전기 도금법에 의해 형성한 경우, 최대라도 25㎛ 정도 높이의 낮은 범프밖에는 형성할 수없는 데 반하여, 와이어 본딩법을 사용함으로써 50㎛ 이상의 높이가 높은 범프를 형성할 수 있으며, 따라서 도 8e에 도시하는 바와 같이, 회로 기판(4)의 관통 구멍부(8)의 도전성 페이스트(7)에 매립되는 범프(15)의 양이 많아지고, 회로 기판(4)의 휘어짐, 굴곡에 대한 허용 범위가 넓어지므로, 보다 신뢰성이 높은 실장을 행할 수 있다.According to the second embodiment, in addition to the effect of the first embodiment, when the bumps are formed by the electroplating method, only bumps with a height of about 25 µm can be formed at most, but by using the wire bonding method A bump having a height of 50 μm or more can be formed, and therefore, as shown in FIG. 8E, the amount of bump 15 embedded in the conductive paste 7 of the through hole 8 of the circuit board 4 is increased. Since the permissible range for bending and bending of the circuit board 4 becomes wider, mounting with higher reliability can be performed.

(실시예 3)(Example 3)

본 발명의 실시예 3에 있어서의 반도체 소자의 실장 방법을, 도 9를 참조하면서 설명한다.The semiconductor device mounting method in Example 3 of this invention is demonstrated, referring FIG.

도 9는, 반도체 소자(1)를 흡착 노즐(10)에 흡착시키고, 돌기 범프(15)와 관통 구멍부(8)에 충전된 도전성 페이스트(7)에 의해 형성된 회로 기판(4)의 외부 전극 단자와 위치 맞춤한 후 가압하여, 돌기 범프(15)가 도전성 페이스트(7)에 매립된 상태를 도시하고 있다. 그 때, 흡착 노즐(10)은 내장되어 있는 히터(17)에 의해 가열되어 있고, 가압과 동시에 도전성 페이스트(7)를 경화시키고 있다.9 shows the external electrode of the circuit board 4 formed by the conductive paste 7 filled with the projection bump 15 and the through hole 8 by adsorbing the semiconductor element 1 to the adsorption nozzle 10. The state where the projection bump 15 is embedded in the conductive paste 7 is shown by aligning with the terminal and pressing. At that time, the adsorption nozzle 10 is heated by the built-in heater 17, and the electroconductive paste 7 is hardened simultaneously with pressurization.

본 실시예 3에 따르면, 상기 실시예 1, 2에서의 효과에 덧붙여, 도전성 페이스트(7)를 경화함으로써, 반도체 소자(1)와 회로 기판(4)과의 고정이 보다 강고하게 되고, 보다 신뢰성이 높은 접합이 가능하게 되고, 또한 종래 도전성 페이스트(7)의 경화가 모듈을 평로에 넣고 일괄 처리했던 데 반하여, 접합과 동시에 동일 설비로 실행할 수 있기 때문에, 반도체 소자(1) 생산 라인의 택트 타임 단축이 가능하게 된다.According to the third embodiment, in addition to the effects of the first and second embodiments, by hardening the conductive paste 7, the fixing between the semiconductor element 1 and the circuit board 4 becomes more firm and more reliable. This high bonding becomes possible, and since the conventional hardening of the conductive paste 7 puts a module into a flat surface and batch-processes, it can be performed by the same equipment at the same time as the bonding, and therefore the tact time of the semiconductor element 1 production line Shortening is possible.

(실시예 4)(Example 4)

본 발명의 실시예 4에 있어서의 반도체 소자의 실장 방법을 도 10을 참조하면서 설명한다.A method of mounting a semiconductor element in Embodiment 4 of the present invention will be described with reference to FIG.

도 10은 반도체 소자(1)를 흡착 노즐(10)에 흡착시키고, 돌기 범프(15)와 관통 구멍부(8)에 충전된 도전성 페이스트(7)에 의해 형성된 회로 기판(4)의 외부 전극 단자(33)와 위치 맞춤한 후 가압하여, 돌기 범프(15)가 도전성 페이스트(7)에 매립된 상태를 도시하고 있다. 그 때, 회로 기판(4)을 유지하고 있는 스테이지(18)는 내장되어 있는 히터(17)에 의해 가열되어 있으며, 반도체 소자(1)의 가압시에 열을 가함으로써, 가압과 동시에 도전성 페이스트(7)를 경화시키고 있다.10 shows the external electrode terminal of the circuit board 4 formed by the conductive paste 7 filled with the protrusion bump 15 and the through hole 8 by adsorbing the semiconductor element 1 to the adsorption nozzle 10. The state where the projection bump 15 is embedded in the conductive paste 7 is shown by aligning with 33 and pressing. At that time, the stage 18 holding the circuit board 4 is heated by the built-in heater 17, and by applying heat at the time of pressurization of the semiconductor element 1, the pressurizing and conductive paste ( 7) is hardened.

본 실시예 4에 따르면, 상기 실시예 1, 2에서의 효과에 덧붙여, 도전성 페이스트(7)를 경화시킴으로써, 반도체 소자(1)와 회로 기판(4)과의 고정이 보다 강고해져서, 보다 신뢰성이 높은 접합이 가능하게 되고, 또한 종래 도전성 페이스트(7)의 경화가 모듈을 평로에 넣고 일괄 처리하고 있던데 반하여, 접합과 동시에 동일 설비에서 실행할 수 있기 때문에, 반도체 소자(1) 생산 라인의 택트 타임을 단축할 수 있다.According to the fourth embodiment, in addition to the effects of the first and second embodiments, the conductive paste 7 is cured, whereby the fixing between the semiconductor element 1 and the circuit board 4 is made stronger, resulting in more reliability. Since the high bonding is possible, and the curing of the conductive paste 7 is conventionally carried out by placing the module in a flat state, the process can be performed in the same equipment at the same time as the bonding, so that the tact time of the semiconductor element 1 production line is reduced. It can be shortened.

(실시예 5)(Example 5)

본 발명의 실시예 5에 있어서의 반도체 소자의 실장 방법을 도 11을 참조하면서 설명한다.A method of mounting a semiconductor element in Embodiment 5 of the present invention will be described with reference to FIG.

도 11에 도시하는 바와 같이 실시예 5에서는, 반도체 소자(1)를 가압하여 회로 기판(4)의 관통 구멍부(8)의 도전성 페이스트(7)와 반도체 소자(1)의 전극(2)상의 돌기 범프(15)를 접촉시킨 후, 모듈(회로 기판(4) 및 반도체 소자(1))을 컨베이어(32)에 탑재하여 이동시키면서 모듈 전체를 히터(19)에 의해 가열하여 도전성 페이스트(7)를 경화시킨다.As shown in FIG. 11, in Example 5, the semiconductor element 1 is pressurized and the conductive paste 7 of the through-hole part 8 of the circuit board 4 and the electrode 2 of the semiconductor element 1 are carried out. After contacting the bumps 15, the module (circuit board 4 and semiconductor element 1) is mounted on the conveyor 32, and the whole module is heated by the heater 19 while moving the conductive paste 7 Cure.

본 실시예 5에 따르면, 상기 실시예 1, 2에서의 효과에 덧붙여, 도전성 페이스트(7)의 경화를, 모듈 전체를 컨베이어(32)에 탑재하여 이동시키면서 가열하는 리플로우 방식으로 실행하기 때문에, 실장과 동일 생산 라인상에서의 경화가 가능해져, 반도체 소자(1) 생산 라인의 택트 타임에는 영향을 미치는 일 없이, 반도체 소자(1)와 회로 기판(4)과의 고정을 보다 강고하게 할 수 있어, 보다 신뢰성이 높은 접합을 행할 수 있다.According to the fifth embodiment, in addition to the effects of the first and second embodiments, the hardening of the conductive paste 7 is performed by a reflow method in which the entire module is mounted on the conveyor 32 and heated while being moved. Curing is possible on the same production line as the mounting, and the fixing between the semiconductor element 1 and the circuit board 4 can be more firmly without affecting the tact time of the semiconductor element 1 production line. More reliable bonding can be performed.

(실시예 6)(Example 6)

본 발명의 실시예 6에 있어서의 반도체 소자의 실장 방법을 도 12를 참조하면서 설명한다.A method of mounting a semiconductor device in Embodiment 6 of the present invention will be described with reference to FIG.

도 12에 도시하는 바와 같이 실시예 6에서는, 상기 실시예 1 내지 실시예 5의 실장 공정에 있어서, 회로 기판(4)에 반도체 소자(1)를 실장한 후에, 반도체 소자(1)와 회로 기판(4)과의 간격에 시린지(31)를 이용하여 에폭시계 수지(20)를 충전한다.As shown in FIG. 12, in Example 6, in the mounting process of Example 1-5, after mounting the semiconductor element 1 on the circuit board 4, the semiconductor element 1 and a circuit board are carried out. The epoxy resin 20 is filled in the space | interval with (4) using the syringe 31.

본 실시예 6에 따르면, 상기 실시예 1 내지 실시예 5에서의 효과에 덧붙여, 도 13에 도시하는 바와 같이, 에폭시계 수지(20)의 충전에 의해, 반도체 소자(1)의활성면 및 전극(2)의 표면이 보호되기 때문에, 예를 들면 모듈이 고온 다습 등의 환경에 노출되더라도 전극(2) 및 돌기 범프(3)의 부식을 막을 수 있어, 보다 신뢰성이 높은 접속을 행할 수 있다.According to the sixth embodiment, in addition to the effects in the first to fifth embodiments, as shown in FIG. 13, the active surface and the electrode of the semiconductor element 1 are filled by the epoxy resin 20. Since the surface of (2) is protected, corrosion of the electrode 2 and the protrusion bump 3 can be prevented even if the module is exposed to an environment such as high temperature and high humidity, for example, and a more reliable connection can be made.

(실시예 7)(Example 7)

본 발명의 실시예 7에 있어서의 반도체 소자의 실장 방법을, 도 14를 참조하면서 설명한다.A method of mounting a semiconductor element in Embodiment 7 of the present invention will be described with reference to FIG. 14.

우선, 도 14a에 도시하는 바와 같이, 회로 기판(4)의 관통 구멍부(8)에 도전성 페이스트(7)를 충전하여 외부 전극 단자(33)를 형성한 후, 회로 기판(4)상에 열 경화계, 또는 열 가소계, 또는 열 경화와 열 가소의 혼합계 수지로 이루어지는 접착제 시트(21)를 배치한다.First, as shown in FIG. 14A, the conductive paste 7 is filled in the through hole 8 of the circuit board 4 to form the external electrode terminal 33, and then heat is formed on the circuit board 4. The adhesive sheet 21 which consists of a hardening system or a thermoplastic system, or a mixture resin of thermosetting and thermoplastics is arrange | positioned.

또, 접착제 시트(21)에는 니켈, 땜납, 카본, 금박 플라스틱 입자 등을 균일하게 분산시켜 놓아도 무방하다.In addition, nickel, solder, carbon, gold foil plastic particles, etc. may be disperse | distributed to the adhesive sheet 21 uniformly.

다음에, 도 14b에 도시하는 바와 같이, 반도체 소자(1)를 흡착 노즐(10)에 흡착하여, 돌기 범프(15)와 관통 구멍부(8)에 충전된 도전성 페이스트(7)에 의해 형성된 회로 기판(4)의 외부 전극 단자(33)와 위치 맞춤한다.Next, as shown in FIG. 14B, a circuit formed by the conductive paste 7 filled in the projection bumps 15 and the through holes 8 by adsorbing the semiconductor element 1 to the adsorption nozzle 10. It is aligned with the external electrode terminal 33 of the board | substrate 4.

다음에, 도 14c에 도시하는 바와 같이, 반도체 소자(1)를 가압하여, 돌기 범프(15)가 접착제 시트(21)를 뚫고 나와 도전성 페이스트(7)에 돌기 범프(15)가 매립된다. 그 때, 흡착 노즐(10)은 내장되어 있는 히터(17)에 의해 가열되어 있으며, 가압과 동시에 접착제 시트(21)의 용융·경화가 이루어진다.Next, as shown in FIG. 14C, the semiconductor element 1 is pressurized so that the bump bumps 15 penetrate the adhesive sheet 21 and the bump bumps 15 are embedded in the conductive paste 7. At that time, the adsorption nozzle 10 is heated by the built-in heater 17, and the adhesive sheet 21 is melted and hardened simultaneously with the pressurization.

본 실시예 7에 따르면, 상기 실시예 1, 2에서의 효과에 덧붙여, 도 14d에 도시하는 바와 같이, 접착제 시트(21)가 용융·경화하여, 반도체 소자(1)의 활성면 및 전극(2)의 표면을 보호하기 때문에, 보다 접속의 신뢰성이 증대되고, 또한 접착제 시트(21)의 경우, 가압·경화에 필요한 시간이 약 30초로서, 에폭시계 수지의 경화 시간인 약 4시간에 비해 큰 폭으로 짧기 때문에, 반도체 소자(1) 생산 라인의 택트 타임 단축이 가능해진다.According to the seventh embodiment, in addition to the effects of the first and second embodiments, as illustrated in FIG. 14D, the adhesive sheet 21 is melted and cured to form the active surface and the electrode 2 of the semiconductor element 1. ), The reliability of the connection is increased, and in the case of the adhesive sheet 21, the time required for pressurization and curing is about 30 seconds, which is larger than about 4 hours that is the curing time of the epoxy resin. Since the width is short, the tact time of the semiconductor element 1 production line can be shortened.

(실시예 8)(Example 8)

본 발명의 실시예 8에 있어서의 반도체 소자의 실장 방법을 도 15를 참조하면서 설명한다.A method of mounting a semiconductor element in Embodiment 8 of the present invention will be described with reference to FIG. 15.

우선, 도 15a에 도시하는 바와 같이, 반도체 소자(1)의 전극(2)상에 돌기 범프(15)를 형성한 후, 미리 돌기 범프(15)상에 열 경화계 또는 열 가소계, 또는 열 경화와 열 가소의 혼합계 수지로 이루어지는 접착제 시트(21)를 배치한다. 또, 접착제 시트(21)에는, 니켈, 땜납, 카본, 금박 플라스틱 입자 등을 균일하게 분산시켜 놓아도 무방하다.First, as shown in FIG. 15A, after forming the bumps 15 on the electrodes 2 of the semiconductor element 1, the thermosetting system or the thermoplastic system or the heat is formed on the bumps 15 beforehand. The adhesive sheet 21 which consists of hardening and thermoplastic mixed resin is arrange | positioned. In addition, nickel, solder, carbon, gold foil plastic particles, etc. may be disperse | distributed uniformly to the adhesive sheet 21.

그 후, 도 15b에 도시하는 바와 같이, 반도체 소자(1)를 흡착 노즐(10)에 흡착하고, 돌기 범프(15)와 관통 구멍부(8)에 충전된 도전성 페이스트(7)에 의해 형성된 회로 기판(4)의 외부 전극 단자(33)와 위치 맞춤한 후 가압하여, 돌기 범프(15)가 접착제 시트(21)를 뚫고 나와 도전성 페이스트(7)에 돌기 범프(15)가 매립된다. 그 때, 흡착 노즐(10)은 내장되어 있는 히터(17)에 의해 가열되어 있어, 가압과 동시에 접착제 시트(21)의 용융·경화가 이루어진다.After that, as shown in FIG. 15B, the semiconductor element 1 is adsorbed by the adsorption nozzle 10 and formed of the conductive paste 7 filled in the projection bumps 15 and the through holes 8. After positioning with the external electrode terminal 33 of the board | substrate 4, it presses, and the bump bump 15 penetrates the adhesive sheet 21, and the bump bump 15 is embedded in the electrically conductive paste 7. At that time, the adsorption nozzle 10 is heated by the built-in heater 17, and the adhesive sheet 21 is melted and hardened simultaneously with the pressurization.

본 실시예 8에 따르면, 상기 실시예 1, 2에서의 효과에 덧붙여, 실시예 7과 마찬가지로, 접착제 시트(21)가 용융·경화하여 반도체 소자(1)의 활성면 및 전극(2)의 표면을 보호하기 때문에, 보다 접속의 신뢰성이 증대되고, 또한 접착제 시트(21)의 경우 가압·경화에 대한 시간이 약 30초로서, 에폭시계 수지의 경화 시간인 약 4시간에 비해 큰 폭으로 짧아, 반도체 소자(1) 생산 라인의 택트 타임의 단축이 가능해진다.According to the eighth embodiment, in addition to the effects of the first and second embodiments, the adhesive sheet 21 is melted and cured in the same manner as in the seventh embodiment so that the active surface of the semiconductor element 1 and the surface of the electrode 2 are formed. In this regard, the reliability of the connection is increased, and in the case of the adhesive sheet 21, the time for pressing and curing is about 30 seconds, which is significantly shorter than about 4 hours, which is the curing time of the epoxy resin, The tact time of the semiconductor element 1 production line can be shortened.

이상과 같이 본 발명에 의하면, 반도체 소자의 전극상에 형성된 돌기 범프를, 회로 기판의 관통 구멍부내의 도전성 페이스트에 접촉시켜, 반도체 소자의 전극과 회로 기판의 외부 전극 단자를 전기적으로 접속함으로써, 전극간의 단락을 막을 수 있고, 또한 회로 기판의 휘어짐, 굴곡에 대한 허용 범위가 넓음으로 인해 전극간의 개방을 막을 수 있어서, 전기적 신뢰성이 높은 실장이 가능하게 된다.As described above, according to the present invention, the protrusion bump formed on the electrode of the semiconductor element is brought into contact with the conductive paste in the through hole of the circuit board, and the electrode of the semiconductor element is electrically connected to the external electrode terminal of the circuit board. The short circuit between the electrodes can be prevented and the circuit board can be prevented from opening due to the wide range of allowances for bending and bending of the circuit board, thereby enabling mounting with high electrical reliability.

또한, 접착제 시트를 미리 회로 기판 위, 또는 반도체 소자의 돌기 범프 위에 배치해 두고, 실장시에 돌기 범프가 접착제 시트를 뚫고 나와 회로 기판 관통 구멍부내의 도전성 페이스트에 접촉되어 전기적으로 접속되고, 또한 접착제 시트를 용융·경화함으로써 반도체 소자의 활성면 및 전극의 표면을 접착제 시트에 의해 보호할 수 있어, 보다 접속의 신뢰성을 증대시킬 수 있으며, 또한 접착제 시트의 경우 가압·경화에 필요한 시간이 약 30초로서, 에폭시계 수지의 경화 시간인 약 4시간에 비해 큰 폭으로 짧아, 봉지 공정의 시간을 대폭 삭감할 수 있으므로, 반도체 소자 생산 라인의 택트 타임의 단축을 실현할 수 있다.In addition, the adhesive sheet is disposed on the circuit board or on the bumps of the semiconductor element in advance, and at the time of mounting, the bumps of the bumps penetrate the adhesive sheet and come into contact with the conductive paste in the circuit board through hole to be electrically connected to each other. By melting and curing the sheet, the active surface of the semiconductor element and the surface of the electrode can be protected by an adhesive sheet, thereby increasing the reliability of the connection, and in the case of the adhesive sheet, the time required for pressing and curing is about 30 seconds. As a result, it is considerably shorter than about 4 hours of the curing time of the epoxy resin, and the time of the encapsulation process can be greatly reduced, so that the tact time of the semiconductor element production line can be shortened.

도면의 참조 부호의 일람표List of Reference Symbols in the Drawings

1 : 반도체 소자 2 : 전극1 semiconductor device 2 electrode

3 : 돌기 범프(도금법에 의함) 4 : 회로 기판3: bump bump (by plating method) 4: circuit board

5 : 동박 6 : 외부 전극 단자5: copper foil 6: external electrode terminal

7 : 도전성 페이스트 8 : 관통 구멍부7: conductive paste 8: through hole

9 : 스퀴지 10 : 흡착 노즐9: squeegee 10: adsorption nozzle

11 : 금속 와이어 12 : 금속볼11: metal wire 12: metal ball

13 : 캐필러리 14 : 전극13: capillary 14: electrode

15 : 돌기 범프(와이어 본딩법에 의함) 16 : 패시베이션막15: bump bump (by wire bonding method) 16: passivation film

17, 19 : 히터 18 : 스테이지17, 19: heater 18: stage

20 : 에폭시계 수지 21 : 수지 시트20: epoxy resin 21: resin sheet

31 : 시린지 32 : 컨베이어31 syringe 32: conveyor

33 : 외부 전극 단자33: external electrode terminal

Claims (5)

회로 기판의 회로와 반도체 소자의 전극을 접속하는 상기 회로 기판의 개소에 관통 구멍부를 형성하는 공정과,Forming a through hole in a portion of the circuit board connecting the circuit of the circuit board and the electrode of the semiconductor element; 상기 관통 구멍부에 도전성 페이스트를 충전하여 상기 회로 기판의 이면측에 외부 전극 단자를 형성하는 공정과,Filling a through hole in the through hole to form an external electrode terminal on the back surface side of the circuit board; 상기 반도체 소자의 상기 전극에 원추형으로 뾰족한 형상의 돌기 범프를 형성하는 공정과,Forming a convex pointed bump on the electrode of the semiconductor element; 상기 외부 전극 단자와 상기 반도체 소자의 상기 전극에 형성된 상기 돌기 범프를 위치 결정하는 공정과,Positioning the protrusion bumps formed on the external electrode terminal and the electrode of the semiconductor element; 상기 반도체 소자를 가압하여 상기 관통 구멍부내의 상기 도전성 페이스트와 상기 돌기 범프를 접촉시킴으로써, 상기 반도체 소자의 상기 전극과 상기 회로 기판의 상기 외부 전극 단자를 전기적으로 접속하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 실장 방법.Pressurizing the semiconductor element to contact the conductive paste and the protrusion bump in the through hole to electrically connect the electrode of the semiconductor element with the external electrode terminal of the circuit board. Method of mounting a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 반도체 소자의 전극에 형성되어 있는 돌기 범프는, 와이어 본딩법에 의해 형성되는 금속볼 범프인 것을 특징으로 하는 반도체 소자의 실장 방법.A projection bump formed on an electrode of the semiconductor element is a metal ball bump formed by a wire bonding method. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 반도체 소자를 가압하여, 상기 회로 기판의 상기 관통 구멍부에 충전된 상기 도전성 페이스트와 상기 반도체 소자의 상기 전극상의 상기 돌기 범프를 접촉시킨 후, 가열 도구에 의해 상기 반도체 소자 및 상기 회로 기판의 적어도 한쪽을 가열하여, 상기 도전성 페이스트를 경화시키는 공정을 부가하는 것을 특징으로 하는 반도체 소자의 실장 방법.Pressurizing the semiconductor element to bring the conductive paste filled in the through hole portion of the circuit board into contact with the protrusion bump on the electrode of the semiconductor element; and then at least the semiconductor element and the circuit board by a heating tool. A step of heating one side to cure the conductive paste is added. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 반도체 소자의 전극과 회로 기판의 외부 전극 단자를 접속한 후, 상기 반도체 소자와 상기 회로 기판과의 간극에 에폭시계 수지를 유입하여, 봉지하는 공정을 부가하는 것을 특징으로 하는 반도체 소자의 실장 방법.After connecting the electrode of the said semiconductor element and the external electrode terminal of a circuit board, the process of injecting and sealing an epoxy resin into the clearance gap between the said semiconductor element and the said circuit board is added, The method of mounting a semiconductor element characterized by the above-mentioned. . 회로 기판의 회로와 반도체 소자의 전극을 접속하는 상기 회로 기판의 개소에 관통 구멍부를 형성하는 공정과,Forming a through hole in a portion of the circuit board connecting the circuit of the circuit board and the electrode of the semiconductor element; 상기 관통 구멍부에 도전성 페이스트를 충전하여 외부 전극 단자를 형성하는 공정과,Forming an external electrode terminal by filling a conductive paste into the through hole; 상기 반도체 소자의 상기 전극에 원추형으로 뾰족한 형상의 돌기 범프를 형성하는 공정과,Forming a convex pointed bump on the electrode of the semiconductor element; 상기 외부 전극 단자가 형성된 회로 기판 위, 또는 상기 반도체 소자의 돌기 범프 위에 열경화계 수지 또는 열가소계 수지 또는 열경화와 열가소의 혼합계 수지를 갖는 접착제 시트를 배치하는 공정과,Arranging an adhesive sheet having a thermosetting resin or a thermoplastic resin or a mixture of a thermosetting and thermoplastic resin on a circuit board on which the external electrode terminal is formed or on a bump of the semiconductor element; 상기 외부 전극 단자와 상기 반도체 소자의 상기 전극에 형성된 상기 돌기 범프를 위치 결정하는 공정과,Positioning the protrusion bumps formed on the external electrode terminal and the electrode of the semiconductor element; 상기 반도체 소자를 가압하여, 상기 돌기 범프가 상기 접착제 시트를 뚫고 나와서 상기 관통 구멍부내의 상기 도전성 페이스트와 상기 돌기 범프가 접촉되어, 상기 반도체 소자의 상기 전극과 상기 회로 기판의 상기 외부 전극 단자를 전기적으로 접속하는 공정과,Pressing the semiconductor element, the bump bump penetrates the adhesive sheet, and the conductive paste and the bump bump in the through hole contact each other to electrically connect the electrode of the semiconductor element and the external electrode terminal of the circuit board. The process of connecting with, 가열 도구에 의해 상기 반도체 소자를 가열하여, 상기 접착제 시트를 용융, 경화시키는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 실장 방법.And a step of heating the semiconductor element with a heating tool to melt and harden the adhesive sheet.
KR10-1998-0700903A 1996-06-07 1997-06-06 Method for mounting semiconductor chip KR100457609B1 (en)

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JPH09326419A (en) 1997-12-16

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