JP2574369B2 - Semiconductor chip mounted body and mounting method thereof - Google Patents
Semiconductor chip mounted body and mounting method thereofInfo
- Publication number
- JP2574369B2 JP2574369B2 JP63052847A JP5284788A JP2574369B2 JP 2574369 B2 JP2574369 B2 JP 2574369B2 JP 63052847 A JP63052847 A JP 63052847A JP 5284788 A JP5284788 A JP 5284788A JP 2574369 B2 JP2574369 B2 JP 2574369B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- conductive
- connection
- insulating resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体チップと基板上の接続電極との電気
的接続に関するものであり、特に、導電性樹脂を用いた
フェースダウンボンディング法に係る電気的接続方法に
関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical connection between a semiconductor chip and a connection electrode on a substrate, and more particularly, to an electrical connection according to a face-down bonding method using a conductive resin. It relates to the connection method.
従来の技術 従来、電子部品の接続端子と基板上の回路パターン端
子との接続には半田付けがよく利用されていたが、近
年、例えばICフラットパッケージ等の小型化と、接続端
子の増加により、接続端子間、いわゆるピッチ間隔が次
第に狭くなり、従来の半田付け技術で対処することが次
第に困難になって来た。2. Description of the Related Art Conventionally, soldering has often been used to connect a connection terminal of an electronic component to a circuit pattern terminal on a board. The pitch between connection terminals, so-called pitch interval, has been gradually narrowed, and it has become increasingly difficult to cope with conventional soldering techniques.
そこで、最近では裸の半導体チップを基板上の接続電
極に直付けして実装面積の効率的使用を図ろうとする方
法が提案されてきた。なかでも、半導体チップを基板上
に接続するに際し、半導体チップをフェースダウン（下
向き）にして、あらかじめ端子電極上にメッキ等により
形成したハンダからなる突起電極（バンプ）を高温に加
熱して融着する方法が、接続後の機械的強度が強く、接
続の回数も１回で済むことなどから有益な方法であると
されている。Thus, recently, a method has been proposed in which a bare semiconductor chip is directly attached to a connection electrode on a substrate to make efficient use of a mounting area. Above all, when connecting the semiconductor chip to the substrate, the semiconductor chip is face down (downward), and the protruding electrodes (bumps) made of solder previously formed on the terminal electrodes by plating etc. are heated to a high temperature and fused. This method is considered to be a useful method because the mechanical strength after connection is high and the number of connections is only one.
以下図面を参照しながら、上述した従来のハンダバン
プによる半導体チップの接続方法の一例について説明す
る。Hereinafter, an example of a method for connecting a semiconductor chip by the above-described conventional solder bump will be described with reference to the drawings.
第２図は従来のハンダパンプによる半導体チップの接
続方法の概略説明図である。第２図において、８は半導
体チップで、９は端子電極である。10はハンダからなる
突起電極（バンプ）である。11は接続電極で、12は基板
である。FIG. 2 is a schematic explanatory view of a conventional method of connecting semiconductor chips by a solder pump. In FIG. 2, reference numeral 8 denotes a semiconductor chip, and 9 denotes a terminal electrode. Reference numeral 10 denotes a bump electrode (bump) made of solder. 11 is a connection electrode and 12 is a substrate.
以上のように構成されたハンダバンプによる半導体チ
ップの接続方法について、以下その概略について説明す
る。An outline of a method of connecting a semiconductor chip using the solder bumps configured as described above will be described below.
まず、半導体チップ８の端子電極９にあらかじめハン
ダからなる突起電極（バンプ）10を形成しておき、この
半導体チップ８を下向きにして基板12の接続電極11に位
置合せを行う。その後、200〜300℃の高温に加熱してハ
ンダを溶融し、融着させることによって電気的接続を得
るものである。First, a protruding electrode (bump) 10 made of solder is formed on the terminal electrode 9 of the semiconductor chip 8 in advance, and the semiconductor chip 8 is oriented downward to the connection electrode 11 of the substrate 12. Thereafter, the solder is heated to a high temperature of 200 to 300 ° C. to melt the solder, and the electrical connection is obtained by fusing the solder.
このような突起電極（バンプ）10は、まず半導体チッ
プ８の端子電極９に、Cr、Cu、Au等の金属薄膜を形成し
た後、メッキによりハンダを積層して形成するものであ
る。Such a protruding electrode (bump) 10 is formed by first forming a metal thin film of Cr, Cu, Au or the like on the terminal electrode 9 of the semiconductor chip 8, and then laminating solder by plating.
発明が解決しようとする課題 しかしながら上記のような方法では、 （１） ハンダを溶融する際に高温に加熱する必要があ
り、熱応力の影響を受け易い。Problems to be Solved by the Invention However, in the above method, (1) it is necessary to heat the solder to a high temperature when melting it, and the solder is easily affected by thermal stress.
（２） ハンダによる接続のために基板側の接続電極が
ハンダ接続可能なものである必要があり、汎用性に欠け
る。(2) The connection electrode on the substrate needs to be solderable for connection by soldering, and thus lacks versatility.
（３） 突起電極（バンプ）を形成するハンダが加熱溶
融する際に流れ、ショートが発生する危険がある。(3) When the solder forming the protruding electrodes (bumps) is heated and melted, it flows, and there is a danger that a short circuit will occur.
（４） 基板への固定が突起電極（バンプ）部のみでな
されているため接着強度が弱く、接続の安定性に欠け
る。(4) Since fixing to the substrate is performed only at the protruding electrode (bump) portion, the bonding strength is weak, and connection stability is lacking.
などといった課題を有していた。 And so on.
本発明は上記の課題に鑑みてなされたものであり、そ
の目的とする所は、半導体チップと実装基板とを容易
に、かつ、信頼性良く電気的接続を行う接続方法を提供
することである。The present invention has been made in view of the above problems, and an object of the present invention is to provide a connection method for easily and reliably electrically connecting a semiconductor chip and a mounting board. .
課題を解決するための手段 本発明は上記の課題を解決するため、導電性樹脂を用
いた半導体チップのフェイスダウンによる基板への電気
的接続において、該基板上の所定の位置に前記半導体チ
ップを載置する工程と、加熱により前記導電性樹脂を硬
化せしめ、該基板の接続電極への該半導体チップの電気
的接続を得る工程と、ディスペンサーにより該基板上の
所定の位置に熱硬化性の絶縁性樹脂を塗布する工程と、
該半導体チップと該基板との間のギャップに前記絶縁性
樹脂を充填する工程と、加熱により前記絶縁性樹脂を硬
化せしめ、硬化収縮により該半導体チップと該基板の電
気的接続の安定化を図る工程とからなることを特徴とし
て半導体チップの電気的な接続を実現しようとするもの
である。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a method for electrically connecting a semiconductor chip using a conductive resin to a substrate by face-down, in which the semiconductor chip is placed at a predetermined position on the substrate. Placing, curing the conductive resin by heating to obtain an electrical connection of the semiconductor chip to the connection electrodes of the substrate, and disposing a thermosetting insulating material at a predetermined position on the substrate by a dispenser. Applying a conductive resin,
A step of filling the gap between the semiconductor chip and the substrate with the insulating resin, and curing the insulating resin by heating, and stabilizing the electrical connection between the semiconductor chip and the substrate by curing shrinkage. It is intended to realize an electrical connection of a semiconductor chip by being characterized by comprising a process.
作用 本発明は上記した方法によって、絶縁性樹脂の硬化収
縮で導電性樹脂による半導体チップの端子電極と基板の
接続電極との電気的接続の安定化を図ることができ、容
易で信頼性の高い半導体チップの電気的な接続が可能と
なる。The present invention can stabilize the electrical connection between the terminal electrode of the semiconductor chip and the connection electrode of the substrate by the conductive resin by the curing shrinkage of the insulating resin by the method described above, and it is easy and reliable. Electrical connection of the semiconductor chip becomes possible.
実施例 以下、本発明の一実施例の半導体チップの接続方法に
ついて、図面を参照しながら説明する。Embodiment Hereinafter, a method for connecting a semiconductor chip according to an embodiment of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例における半
導体チップの接続方法を示す工程説明図である。第１図
において、１は半導体チップ、２は端子電極である。３
は電気的接続を得るための熱硬化性の導電性樹脂であ
る。４は接続電極であり、５は基板である。６はディス
ペンサーであり、７は熱硬化性の絶縁性樹脂である。1 (a) to 1 (d) are process explanatory views showing a method of connecting semiconductor chips according to one embodiment of the present invention. In FIG. 1, 1 is a semiconductor chip, and 2 is a terminal electrode. 3
Is a thermosetting conductive resin for obtaining electrical connection. 4 is a connection electrode and 5 is a substrate. Reference numeral 6 denotes a dispenser, and reference numeral 7 denotes a thermosetting insulating resin.
以上のように構成された半導体チップの接続方法につ
いて、以下図面を用いてその動作を説明する。The operation of the method for connecting the semiconductor chips configured as described above will be described below with reference to the drawings.
まず、半導体チップ１の端子電極２部にあらかじめ熱
硬化性の導電性樹脂３を形成しておく。このとき導電性
樹脂３は端子電極２上に直接形成してもよいし、端子電
極２にあらかじめ形成した突起電極（バンプ）上に形成
してもよい。First, a thermosetting conductive resin 3 is formed on the terminal electrodes 2 of the semiconductor chip 1 in advance. At this time, the conductive resin 3 may be formed directly on the terminal electrode 2 or may be formed on a protruding electrode (bump) formed on the terminal electrode 2 in advance.
そして、第１図（ａ）に示す様に、この半導体チップ
１を下向きにして基板５の接続電極４に位置合せを行
い、基板５上に半導体チップ１を載置した後、加熱し導
電性樹脂３を硬化させることによって、第１図（ｂ）に
示す様に、半導体チップ１の端子電極２と基板５の接続
電極４が電気的に接続される。Then, as shown in FIG. 1 (a), the semiconductor chip 1 is positioned downward and aligned with the connection electrode 4 of the substrate 5, the semiconductor chip 1 is placed on the substrate 5, and then heated to form a conductive film. By curing the resin 3, the terminal electrodes 2 of the semiconductor chip 1 and the connection electrodes 4 of the substrate 5 are electrically connected as shown in FIG. 1 (b).
つぎに、第１図（ｃ）に示す様に、ディスペンサー６
によって絶縁性樹脂７を塗布した後、基板５を傾けて保
持すると、第１図（ｄ）に示す様に、絶縁性樹脂７が半
導体チップ１と基板５の間のギャップに充填できる。こ
の状態で加熱して絶縁性樹脂７の硬化を行う。Next, as shown in FIG.
When the substrate 5 is tilted and held after the application of the insulating resin 7, the insulating resin 7 can fill the gap between the semiconductor chip 1 and the substrate 5 as shown in FIG. 1 (d). In this state, the insulating resin 7 is cured by heating.
このとき、絶縁性樹脂７は硬化反応が進むにつれて硬
化収縮するため、半導体チップ１の端子電極２と基板５
の接続電極４の間で電気的接続を行う導電性樹脂３にお
ける密着性が増し接続の安定性が向上できる。At this time, since the insulating resin 7 cures and contracts as the curing reaction proceeds, the terminal electrodes 2 of the semiconductor chip 1 and the substrate 5
The adhesion of the conductive resin 3 for making an electrical connection between the connection electrodes 4 is increased, and the stability of the connection can be improved.
また、導電性樹脂３および絶縁性樹脂７の加熱硬化
は、ハンダによる接続に比べて低温で行うため、熱応力
による影響を軽減することができ、かつ、絶縁性接着剤
７によっても半導体チップ１の固定を行っているために
極めて安定な接続が得られる。Further, the heat curing of the conductive resin 3 and the insulating resin 7 is performed at a lower temperature than the connection by soldering, so that the influence of the thermal stress can be reduced, and the semiconductor chip 1 can be cured by the insulating adhesive 7. , A very stable connection can be obtained.
さらに、半導体チップ１の端子電極２と基板５の接続
電極５の電気的接続は導電性樹脂３による接着状態で行
うため、基板５の接続電極４の材質は配線材料であれば
いかなるものでもよい。Furthermore, since the electrical connection between the terminal electrode 2 of the semiconductor chip 1 and the connection electrode 5 of the substrate 5 is performed in a bonded state by the conductive resin 3, the material of the connection electrode 4 of the substrate 5 may be any material as long as it is a wiring material. .
以上のようにして、半導体チップ１と基板５を極めて
安定に、かつ、汎用性のある方法で接続が可能となる。As described above, the semiconductor chip 1 and the substrate 5 can be connected in a very stable and versatile manner.
また、導電性樹脂３の材質は、エポキシ系樹脂、シリ
コーン系樹脂、ポリイミド系樹脂、フェノール系樹脂等
にAg、Au、Cu、Ni等の微粉末を含んだもので、良好な導
電性があって、かつ、熱硬化性の導電性樹脂であればい
かなるものでもよい。The conductive resin 3 is made of epoxy resin, silicone resin, polyimide resin, phenol resin or the like containing fine powder of Ag, Au, Cu, Ni, etc., and has good conductivity. Any material may be used as long as it is a thermosetting conductive resin.
同様に、絶縁性樹脂７の材質も、エポキシ系樹脂、シ
リコーン系樹脂、ポリイミド系樹脂、フェノール系樹脂
等、熱硬化による硬化収縮性があって、かつ、熱硬化性
の絶縁性樹脂であればいかなるものでもよい。Similarly, if the material of the insulating resin 7 is a thermosetting insulating resin which has curing shrinkage due to thermosetting, such as an epoxy resin, a silicone resin, a polyimide resin, and a phenol resin, and the like. Anything is acceptable.
さらに、導電性樹脂４と絶縁性樹脂７の熱硬化の条件
が等しい場合には、一括して同時に行ってもよい。Furthermore, when the conditions of the thermosetting of the conductive resin 4 and the insulating resin 7 are equal, they may be performed collectively and simultaneously.
発明の効果 以上に説明したように、本発明の半導体チップの接続
方法によれば、絶縁性樹脂の硬化収縮によって半導体チ
ップと基板間の電気的接続部の安定性が増すために、容
易で信頼性の高い電気的接続が可能となり、極めて実用
価値が高い。Effect of the Invention As described above, according to the method for connecting a semiconductor chip of the present invention, the stability of the electrical connection between the semiconductor chip and the substrate is increased by the curing shrinkage of the insulating resin. This makes it possible to make highly-reliable electrical connections, and has extremely high practical value.
第１図（ａ）〜（ｄ）は本発明の一実施例における半導
体チップの接続方法を示す工程説明図、第２図は従来の
半導体チップの接続方法を示す概略説明図である。 1,8……半導体チップ、2,9……端子電極、３……導電性
樹脂、4,11……接続電極、5,12……基板、10……突起電
極（バンプ）。1 (a) to 1 (d) are process explanatory views showing a method of connecting a semiconductor chip in one embodiment of the present invention, and FIG. 2 is a schematic explanatory view showing a conventional method of connecting a semiconductor chip. 1,8 ... Semiconductor chip, 2,9 ... Terminal electrode, 3 ... Conductive resin, 4,11 ... Connection electrode, 5,12 ... Substrate, 10 ... Protrusion electrode (bump).
───────────────────────────────────────────────────── フロントページの続き (72)発明者 津田 俊雄 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 昭52−113196（ＪＰ，Ａ) 特開 昭60−262430（ＪＰ，Ａ) 特開 昭62−169433（ＪＰ，Ａ) 実開 昭62−118266（ＪＰ，Ｕ) ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Tsuda 1006 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-52-113196 (JP, A) 262430 (JP, A) JP-A-62-169433 (JP, A) JP-A-62-118266 (JP, U)
Claims (5)
した構成であって、前記半導体チップの端子電極部上に
設けられた突起電極が、前記突起電極上に予め形成され
た導電性樹脂層を介して前記基板の前記接続電極部と電
気的に接続されており、さらに前記半導体チップと前記
基板との間のギャップに硬化収縮性を有する絶縁性樹脂
が充填されることにより、前記導電性樹脂層中の導電粉
相互の接触性を増していることを特徴とする半導体チッ
プの実装体。1. A semiconductor chip mounted on a connection electrode portion on a substrate, wherein a projecting electrode provided on a terminal electrode portion of the semiconductor chip is formed of a conductive resin formed on the projecting electrode in advance. The conductive layer is electrically connected to the connection electrode portion of the substrate via a layer, and furthermore, the gap between the semiconductor chip and the substrate is filled with an insulative resin having a curing shrinkage property, thereby forming the conductive layer. A semiconductor chip mounting body characterized in that the contact between conductive powders in a conductive resin layer is increased.
縁性樹脂であることを特徴とする請求項１記載の半導体
チップの実装体。2. The semiconductor chip mounted body according to claim 1, wherein the insulating resin is an insulating resin that cures and shrinks when heated.
する方法であって、前記半導体チップの端子電極部上に
突起電極を設ける工程と、前記突起電極上に予め導電性
樹脂層を形成する工程と、前記突起電極を前記導電性樹
脂層を介して前記基板の前記接続電極部と接続する工程
と、前記半導体チップと前記基板との間のギャップに硬
化収縮性を有する絶縁性樹脂を充填する工程と、前記絶
縁性樹脂を硬化収縮させることにより前記導電性樹脂層
中の導電粉相互の接触性を増して電気的接続の安定化を
図る工程とからなることを特徴とする半導体チップの実
装方法。3. A method of mounting a semiconductor chip on a connection electrode portion on a substrate, the method comprising: providing a projecting electrode on a terminal electrode portion of the semiconductor chip; and forming a conductive resin layer on the projecting electrode in advance. And connecting the protruding electrode to the connection electrode portion of the substrate via the conductive resin layer, and applying an insulating resin having a curing shrinkage property to a gap between the semiconductor chip and the substrate. A semiconductor chip comprising: a filling step; and a step of stabilizing electrical connection by increasing the contact between conductive powders in the conductive resin layer by curing and shrinking the insulating resin. How to implement.
続電極部と接続する工程が、前記導電性樹脂層を加熱に
より硬化させて行う工程であることを特徴とする請求項
３記載の半導体チップの実装方法。4. The method according to claim 3, wherein the step of connecting the projecting electrode to the connection electrode portion of the substrate via the conductive resin layer is a step of curing the conductive resin layer by heating. Semiconductor chip mounting method.
の絶縁性樹脂を加熱により硬化収縮させて行う工程であ
ることを特徴とする請求項３または４記載の半導体チッ
プの実装方法。5. The method according to claim 3, wherein the step of shrinking the insulating resin is a step of shrinking the thermosetting insulating resin by heating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63052847A JP2574369B2 (en) | 1988-03-07 | 1988-03-07 | Semiconductor chip mounted body and mounting method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63052847A JP2574369B2 (en) | 1988-03-07 | 1988-03-07 | Semiconductor chip mounted body and mounting method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01226161A JPH01226161A (en) | 1989-09-08 |
| JP2574369B2 true JP2574369B2 (en) | 1997-01-22 |
Family
ID=12926238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63052847A Expired - Lifetime JP2574369B2 (en) | 1988-03-07 | 1988-03-07 | Semiconductor chip mounted body and mounting method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2574369B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543585A (en) * | 1994-02-02 | 1996-08-06 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
| US5677246A (en) * | 1994-11-29 | 1997-10-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
| JPH1145954A (en) * | 1997-07-28 | 1999-02-16 | Hitachi Ltd | Method and structure for flip-chip connection and electronic device employing it |
| WO2000019516A1 (en) | 1998-09-30 | 2000-04-06 | Seiko Epson Corporation | Semiconductor device, connection method for semiconductor chip, circuit board and electronic apparatus |
| JP5333291B2 (en) * | 2010-03-01 | 2013-11-06 | 富士通株式会社 | Semiconductor circuit test method and test apparatus |
| US8932909B2 (en) | 2012-11-14 | 2015-01-13 | International Business Machines Corporation | Thermocompression for semiconductor chip assembly |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52113196A (en) * | 1976-03-18 | 1977-09-22 | Seiko Epson Corp | Liquid crystal unit |
| JPS60262430A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0447739Y2 (en) * | 1986-01-21 | 1992-11-11 | ||
| JPS62129586U (en) * | 1986-02-07 | 1987-08-15 |
-
1988
- 1988-03-07 JP JP63052847A patent/JP2574369B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01226161A (en) | 1989-09-08 |
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