KR20090098076A - Flip chip package - Google Patents

Flip chip package Download PDF

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Publication number
KR20090098076A
KR20090098076A KR1020080023253A KR20080023253A KR20090098076A KR 20090098076 A KR20090098076 A KR 20090098076A KR 1020080023253 A KR1020080023253 A KR 1020080023253A KR 20080023253 A KR20080023253 A KR 20080023253A KR 20090098076 A KR20090098076 A KR 20090098076A
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South Korea
Prior art keywords
substrate
anisotropic conductive
semiconductor chip
bump
bumps
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KR1020080023253A
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Korean (ko)
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박창준
정관호
한권환
김성철
김성민
최형석
이하나
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주식회사 하이닉스반도체
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Priority to KR1020080023253A priority Critical patent/KR20090098076A/en
Publication of KR20090098076A publication Critical patent/KR20090098076A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A flip chip package is provided to increase a dimension contacted between a bump and an electrode terminal of a substrate by forming the bump having a concave shape on a semiconductor chip. A substrate(102) includes an electrode terminal(106). A semiconductor chip(114) is attached on one surface of the substrate with a face-down type, and has a bonding pad. An anisotropic conductive adhesive(110) is interposed between the semiconductor chip and the substrate, and has a plurality of conductive particles. A connection part(113) has a concave shape in order to widen a contact dimension with the particle inside the anisotropic conductive adhesive. The connection part is made of a bump. The connection part has a concave shape by a coining mode. The bump includes a gold stud bump.

Description

플립 칩 패키지{FLIP CHIP PACKAGE}Flip Chip Package {FLIP CHIP PACKAGE}

본 발명은 플립 칩 패키지에 관한 것으로, 보다 자세하게는, 범프의 접촉 저항을 감소시킴과 아울러, 반도체 칩과 기판 간의 신뢰성을 향상시킬 수 있는 플립 칩 패키지에 관한 것이다. The present invention relates to a flip chip package, and more particularly, to a flip chip package that can reduce the contact resistance of the bump and improve the reliability between the semiconductor chip and the substrate.

각종 전기, 전자 제품의 크기가 소형화되는 추세에 따라, 한정된 크기의 기판에 보다 많은 수의 칩을 실장시켜 소형이면서도 고용량을 달성하고자 하는 많은 연구가 전개되고 있고, 이에 따라, 기판 상에 실장되는 반도체 패키지의 크기 및 두께가 점차 감소되고 있는 실정이다. As the size of various electric and electronic products is miniaturized, a lot of researches are attempting to achieve a small size and high capacity by mounting a larger number of chips on a limited size substrate, and thus, a semiconductor mounted on the substrate. The size and thickness of the package is gradually decreasing.

예들 들어, 패키지의 전체 사이즈에 대해 반도체칩의 사이즈가 80% 이상이 되는 칩 사이즈 패키지(Chip Size Package)가 제안되었으며, 이러한 칩 사이즈 패키지는 경박단소의 잇점 때문에 여러가지 형태로 개발되고 있다. For example, a chip size package has been proposed in which the size of a semiconductor chip is 80% or more with respect to the total size of the package, and such a chip size package has been developed in various forms due to the advantages of light and small.

한편, 전형적인 반도체 패키지 및 일부 칩 사이즈 패키지는 인쇄회로기판(Printed Circuit Board)에의 실장방법으로 리드프레임에 의한 솔더링(soldering) 방식을 이용하고 있다. 그러나, 상기 리드프레임에 의한 솔더링 방식은 공정 진행이 용이하고 신뢰성 측면에서 우수하다는 잇점이 있지만, 반도체칩 과 인쇄회로기판 간의 전기적 신호 전달 길이가 긴 것과 관련하여 전기적 특성 측면에서는 불리함이 있다. Meanwhile, typical semiconductor packages and some chip size packages use a soldering method using a lead frame as a mounting method on a printed circuit board. However, the soldering method using the lead frame has advantages in that the process proceeds easily and is excellent in terms of reliability. However, the soldering method using the lead frame has disadvantages in terms of electrical characteristics in connection with a long electrical signal transmission length between the semiconductor chip and the printed circuit board.

이에, 반도체칩과 인쇄회로기판 간의 전기적 신호 전달 경로를 최소화시킬 목적으로, 범프(Bump)를 이용한 플립 칩 패키지 구조가 제안되었다. Accordingly, in order to minimize the electrical signal transmission path between the semiconductor chip and the printed circuit board, a flip chip package structure using bumps has been proposed.

상기 플립 칩 패키지는 칩의 본딩패드 상에 형성시킨 범프에 의해 상기 반도체칩이 인쇄회로기판에의 접착이 이루어지도록 함과 동시에 반도체칩과 인쇄회로기판 간의 전기적 접속이 이루어지도록 한 구조로서, 상기 반도체칩과 인쇄회로기판 간의 전기적 신호 전달이 단지 범프에 의해서만 이루어지므로 신호 전달 경로가 매우 짧으며, 따라서, 전기적 특성 측면에서 잇점을 갖는다The flip chip package is a structure in which the semiconductor chip is adhered to the printed circuit board by the bump formed on the bonding pad of the chip, and the electrical connection is made between the semiconductor chip and the printed circuit board. Since the electrical signal transfer between the chip and the printed circuit board is made only by bumps, the signal transmission path is very short and therefore has advantages in terms of electrical characteristics.

따라서, 이러한 플립 칩 패키지는 반도체칩과 인쇄회로기판을 전기적으로 연결하는 범프의 조인트(Joint) 안정성을 확보하는 것이 중요하다.Therefore, it is important for the flip chip package to secure joint stability of bumps electrically connecting the semiconductor chip and the printed circuit board.

상기와 같은 플립 칩 패키지는 일반적으로 반도체 칩의 본딩 패드 상에 언더 범프 메탈(Under Buffer Metal)을 형성한 후, 다시 상기 언더 범프 메탈 상에 솔더를 도금한 후 리플로우(Reflow)로 범프를 형성한 다음, 상기 반도체 칩 상의 범프와 기판을 접촉시킨 상태로 리플로우를 실시하여 접합시키는 솔더 범프 타입과, 반도체 칩 상에 금 또는 구리 스터드(Stud) 범프를 형성한 후 기판 상에 상기 스터드 범프와의 접착을 위한 솔더를 형성하고, 상기 반도체 칩과 상기 기판 간을 열 압착하여 접합하거나, 또는, 상기 스터드 범프와 기판 사이에 이방성 도전 필름(ACF : Anistropic Conductive Film), 비전도성 페이스트(NCP : Non Conductive Paste)와 같은 이방성 전도 접착제를 삽입 후 압축하여 접합시키는 스터드 범프 타입과 같은 두 가지 방식으로 제조한다.In general, the flip chip package may form an under bump metal on an bonding pad of a semiconductor chip, and then plate a solder on the under bump metal, and then form a bump by reflow. Next, a solder bump type is formed by reflowing and bonding the bumps on the semiconductor chip in contact with the substrate, and a gold or copper stud bump is formed on the semiconductor chip, and then the stud bumps are formed on the substrate. To form a solder for adhesion, and thermally compress the bonding between the semiconductor chip and the substrate, or between the stud bump and the substrate, an anisotropic conductive film (ACF), non-conductive paste (NCP: Non Anisotropic conductive adhesives such as Conductive Paste are prepared in two ways, such as the stud bump type, which is bonded and pressed after insertion.

그러나, 자세하게 도시하고 설명하지는 않았지만 상기와 같은 이방성 전도 접착제를 이용한 스터드 범프 타입의 플립 칩 패키지는, 상기 스터드 범프의 접촉저항 신뢰성이 상기 이방성 전도 접착제의 도전성 파티클과 범프, 그리고, 상기 범프와 기판 전극 단자 간에 접촉되는 면적, 또는, 상기 이방성 전도 접착제 내의 도전성 파티클의 갯수에 의존하는 경향이 크다.However, although not shown and described in detail, the stud bump type flip chip package using the anisotropic conductive adhesive as described above, the contact resistance reliability of the stud bump is conductive particles and bumps of the anisotropic conductive adhesive, and the bump and the substrate electrode There is a large tendency to depend on the area contacted between the terminals or the number of conductive particles in the anisotropic conductive adhesive.

따라서, 상기와 같이 이방성 전도 접착제를 이용한 플립 칩 본딩에서의 스터드 범프 적용시, 스터드 범프의 접촉 저항을 감소시킴과 아울러, 반도체 칩과 기판 간의 신뢰성을 향상시킬 수 있는 방법이 절실히 요구되고 있다.Therefore, when the stud bump is applied in flip chip bonding using an anisotropic conductive adhesive as described above, a method for reducing the contact resistance of the stud bump and improving the reliability between the semiconductor chip and the substrate is urgently required.

본 발명은 이방성 전도 접착제를 이용한 스터드 범프 적용시, 범프의 접촉 저항을 감소시킴과 아울러, 반도체 칩과 기판 간의 신뢰성을 향상시킨 플립 칩 패키지를 제공한다.The present invention provides a flip chip package that reduces the contact resistance of the bumps and improves the reliability between the semiconductor chip and the substrate when applying stud bumps using an anisotropic conductive adhesive.

본 발명에 따른 플립 칩 패키지는, 전극 단자를 구비한 기판; 상기 기판의 일면 상에 페이스-다운(Face-Down) 타입으로 부착되며, 본딩패드를 갖는 반도체 칩; 상기 반도체 칩과 기판 사이에 개재되며, 다수의 도전성 파티클(Particle)을 갖는 이방성 전도 접착제; 및 상기 반도체 칩의 본딩패드와 상기 이방성 전도 접착제 사이에 개재되며, 상기 이방성 전도 접착제 내의 파티클과의 접촉 면적이 넓어 지도록 오목 형상을 갖는 연결부;를 포함한다.A flip chip package according to the present invention includes a substrate having electrode terminals; A semiconductor chip attached to one surface of the substrate in a face-down type and having a bonding pad; An anisotropic conductive adhesive interposed between the semiconductor chip and the substrate and having a plurality of conductive particles; And a connection part interposed between the bonding pad of the semiconductor chip and the anisotropic conductive adhesive and having a concave shape to widen a contact area with particles in the anisotropic conductive adhesive.

상기 이방성 전도 접착제는 ACF(Anisotropic Conductive Film) 또는 ACP(Anisotropic Conductive Paste)를 포함한다.The anisotropic conductive adhesive includes an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP).

상기 연결부는 범프로 이루어진 것을 특징으로 한다.The connecting portion is characterized in that consisting of a bump.

상기 범프는 금 스터드 범프를 포함하는 것을 특징으로 한다. The bumps are characterized in that they comprise gold stud bumps.

상기 범프는 니켈 및 금 범프를 포함하는 것을 특징으로 한다.The bumps are characterized in that they comprise nickel and gold bumps.

상기 연결부는 코이닝(Coining) 방식에 의해 오목한 형상을 갖는 것을 특징으로 한다.The connection portion is characterized in that it has a concave shape by a coining (Coining) method.

상기 기판 타면에 부착된 외부 접속 단자를 더 포함하는 것을 특징으로 한다.It further comprises an external connection terminal attached to the other surface of the substrate.

본 발명은 이방성 전도 접착제를 적용한 플립 칩 패키지 형성시, 반도체 칩 상에 일면이 오목한 형상을 갖는 범프를 형성하여 기판 상에 플립 칩 본딩함으로써, 상기 일면에 오목한 형상을 갖는 범프로 인해 범프와 기판의 전극 단자 간에 접촉되는 면적을 증가시킬 수 있다.According to the present invention, when forming a flip chip package to which an anisotropic conductive adhesive is applied, a bump having one concave shape is formed on a semiconductor chip and flip chip bonding onto the substrate, thereby forming bumps and a substrate. The area of contact between the electrode terminals can be increased.

따라서, 본 발명은 상기와 같이 플립 칩 본딩에서의 스터드 범프 적용시, 범프와 기판의 전극 단자 간의 증가된 면적으로 상기 이방성 전도 접착제 내의 도전성 파티클이 상기 범프의 오목한 형상 내로 집중됨으로써, 상기 반도체 칩과 기판 간을 전기적 연결을 종래보다 용이하게 할 수 있다.Accordingly, in the present invention, when the stud bump is applied in flip chip bonding, the conductive particles in the anisotropic conductive adhesive are concentrated into the concave shape of the bump by increasing the area between the bump and the electrode terminal of the substrate. Electrical connection between substrates can be made easier than before.

그 결과, 본 발명은 상기 스터드 범프의 접촉 저항을 감소시킴과 아울러, 반 도체 칩과 기판 간의 신뢰성을 향상시킬 수 있다.As a result, the present invention can reduce the contact resistance of the stud bump and improve the reliability between the semiconductor chip and the substrate.

본 발명은, ACF 또는 ACP와 같은 이방성 전도 접착제를 적용한 플립 칩 패키지 형성시, 반도체 칩 상에 일면이 오목한 형상을 갖는 범프를 형성하여 기판 상에 플립 칩 본딩한다.In the present invention, when forming a flip chip package to which an anisotropic conductive adhesive such as ACF or ACP is applied, bumps having a concave shape on one surface are formed on a semiconductor chip and flip chip bonded onto a substrate.

이렇게 하면, 상기와 같이 일면이 오목한 형상을 갖는 범프를 이용하여 반도체 칩을 기판 상에 플립 칩 본딩함으로써, 상기 일면이 오목한 형상을 갖는 범프로 인해 반도체 칩에의 범프와 기판의 전극 단자 간에 접촉되는 면적을 증가시킬 수 있다.In this case, the semiconductor chip is flip-chip bonded onto the substrate using bumps having one concave shape as described above, so that the bumps having one concave shape are contacted between the bumps on the semiconductor chip and the electrode terminals of the substrate. You can increase the area.

따라서, 상기와 같이 플립 칩 본딩에서의 스터드 범프 적용시, 상기 이방성전도 접착제와 범프, 그리고, 범프와 기판의 전극 단자 간의 증가된 면적으로 상기 이방성 전도 접착제 내의 도전성 파티클이 상기 범프의 홈 내로 집중됨으로써, 상기 반도체 칩과 기판 간을 전기적 연결을 종래보다 용이하게 할 수 있다.Thus, when applying stud bumps in flip chip bonding as described above, the conductive particles in the anisotropic conductive adhesive are concentrated into the grooves of the bumps by the increased area between the anisotropic conductive adhesive and the bumps and the electrode terminals of the bumps and the substrate. In addition, the electrical connection between the semiconductor chip and the substrate can be made easier than before.

그 결과, 상기 스터드 범프의 접촉 저항을 감소시킴과 아울러, 반도체 칩과 기판 간의 신뢰성을 향상시킬 수 있다.As a result, while reducing the contact resistance of the stud bump, it is possible to improve the reliability between the semiconductor chip and the substrate.

이하에서는, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

자세하게, 도 1은 본 발명의 실시예에 따른 플립 칩 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, FIG. 1 is a cross-sectional view illustrating a flip chip package according to an exemplary embodiment of the present invention.

도시된 바와 같이 본 발명의 실시예에 따른 플립 칩 패키지(100)는, 전극 단 자(106) 및 상기 전극 단자(106)를 노출시키도록 솔더 마스크(108)가 형성된 기판(102) 상에 본딩패드(116) 및 상기 본딩패드(116)를 노출시키도록 PIQ(Polyimide Isoindro Quinazorindione)와 같은 보호막(118)이 형성된 반도체 칩(114)이 상기 반도체 칩(114)의 본딩패드(116) 상에 형성된 연결부(113)를 매개로 플립 칩 본딩된 구조를 갖는다.As shown, the flip chip package 100 according to the embodiment of the present invention is bonded on a substrate 102 on which a solder mask 108 is formed to expose the electrode terminal 106 and the electrode terminal 106. A semiconductor chip 114 on which a protective film 118 such as polyimide isoindro quinazorindione (PIQ) is formed to expose the pad 116 and the bonding pad 116 is formed on the bonding pad 116 of the semiconductor chip 114. It has a flip chip bonded structure via the connection portion 113.

상기 전극 단자(106) 및 솔더 마스크(108)를 포함하는 기판(102)과 상기 반도체 칩(114) 사이에는 ACF(Anisotropic Conductive Film) 또는 ACP(Anisotropic Conductive Paste)로 이루어진 이방성 도전 접착제(110)가 개재된다.An anisotropic conductive adhesive 110 made of an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP) is formed between the substrate 102 including the electrode terminal 106 and the solder mask 108 and the semiconductor chip 114. It is interposed.

또한, 상기 연결부(113)는 범프로 이루어지며, 상기 범프는 코이닝(Coining) 방식에 의해 일면이 오목한 형상의 홈(H)이 형성된다.In addition, the connection part 113 is formed of a bump, and the bump is formed with a groove H having a concave shape on one surface by a coining method.

한편, 상기 오목한 형상의 홈을 갖는 범프는 전술한 코이닝 방식 뿐만 아니라, 웨이퍼 레벨 패키지에서 반도체 칩 상에 구리 전해 도금을 이용한 구리 범프가 형성되고, 상기 구리 범프의 습식 식각(Wet Etching)에 의해, 본 발명의 실시예에서와 같이 오목한 형상으로 형성될 수 있다.Meanwhile, the bumps having the concave-shaped grooves are formed with copper bumps using copper electroplating on a semiconductor chip in a wafer-level package, as well as the coining method described above, and by wet etching of the copper bumps. As in the embodiment of the present invention, it may be formed in a concave shape.

여기서, 본 발명은 상기 범프와 같은 연결부(113)의 일면에 형성된 오목한 형상의 홈(H)으로 인해 상기 이방성 전도 접착제(110) 내의 도전성 파티클(112)이 집중되며, 이로 인해, 상기 홈(H) 내에는 이방성 전도 접착제의 도전성 파티클(112) 밀도가 증가되어, 상기 범프와 같은 연결부(113)와 기판(102)의 전극 단자(106) 간의 접촉 면적이 향상된다.Here, the present invention concentrates the conductive particles 112 in the anisotropic conductive adhesive 110 due to the concave groove (H) formed on one surface of the connection portion 113 such as the bump, thereby, the groove (H) ), The density of the conductive particles 112 of the anisotropic conductive adhesive is increased, thereby improving the contact area between the connection portion 113 such as the bump and the electrode terminal 106 of the substrate 102.

상기 범프는 금 스터드 범프 또는 니켈 및 금 범프로 형성된다.The bumps are formed of gold stud bumps or nickel and gold bumps.

상기 연결부(113), ACF 또는 ACP로 이루어진 이방성 전도 접착제(110) 및 반도체 칩(114)을 포함한 기판(102)의 일면을 상기 반도체 칩(114)을 외부의 스트레스로부터 보호하기 위해 EMC(Epoxy Molding Compound)와 같은 봉지제(도시안됨)로 밀봉된다.Epoxy molding to protect the semiconductor chip 114 from external stress on one surface of the substrate 102 including the connection part 113, the anisotropic conductive adhesive 110 made of ACF or ACP, and the semiconductor chip 114. Sealed with an encapsulant (not shown).

상기 기판(102) 타면의 볼 랜드(도시안됨)에는 실장수단으로서 솔더 볼과 같은 다수의 외부 접속 단자(120)가 부착된다.A plurality of external connection terminals 120 such as solder balls are attached to the ball lands (not shown) on the other surface of the substrate 102.

전술한 바와 같이 본 발명에 따른 플립 칩 패키지는, ACF 또는 ACP와 같은 이방성 전도 접착제를 적용한 플립 칩 본딩시, 상기와 같이 반도체 칩 상에 일면이 오목한 형상을 갖는 범프를 형성하여 기판 상에 플립 칩 본딩함으로써, 상기 일면이 오목한 형상을 갖는 범프로 인해 범프와 기판의 전극 단자 간에 접촉되는 면적을 증가시킬 수 있다.As described above, the flip chip package according to the present invention, when flip chip bonding is applied an anisotropic conductive adhesive such as ACF or ACP, the flip chip on the substrate by forming a bump having a concave shape on one side on the semiconductor chip as described above By bonding, the contact area between the bump and the electrode terminal of the substrate may be increased due to the bump having one concave shape.

따라서, 상기와 같이 플립 칩 본딩에서의 스터드 범프 적용시, 범프와 기판의 전극 단자 간의 증가된 면적으로 상기 이방성 전도 접착제 내의 도전성 파티클이 상기 범프의 오목한 형상 내로 집중됨으로써, 상기 반도체 칩과 기판 간을 전기적 연결을 종래보다 용이하게 할 수 있다.Thus, when applying stud bumps in flip chip bonding as described above, the conductive particles in the anisotropic conductive adhesive are concentrated into the concave shape of the bumps by increasing the area between the bumps and the electrode terminals of the substrate, thereby allowing the semiconductor chip to be separated from the substrate. Electrical connection can be made easier than before.

그 결과, 상기 스터드 범프의 접촉 저항을 감소시킴과 아울러, 반도체 칩과 기판 간의 신뢰성을 향상시킬 수 있다.As a result, while reducing the contact resistance of the stud bump, it is possible to improve the reliability between the semiconductor chip and the substrate.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 웨이퍼 레벨 패키지의 공정에서도 일면이 오목한 형상을 갖는 홈이 형성된 구리 범프를 이용하여 본 발명의 실시예를 적용 및 그에 따른 본 발명의 실시예에서와 같은 동일한 효과를 얻을 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to a specific embodiment, but the present invention is not limited thereto. In the process of a wafer level package, a copper bump having a groove having one concave shape is used. By applying the embodiment of the present invention and accordingly the same effect as in the embodiment of the present invention can be obtained.

또한, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In addition, it is readily apparent to those skilled in the art that the scope of the following claims may be variously modified and modified without departing from the spirit and scope of the present invention.

도 1은 본 발명의 실시예에 따른 플립 칩 패키지를 설명하기 위해 도시한 단면도.1 is a cross-sectional view illustrating a flip chip package according to an embodiment of the present invention.

Claims (7)

전극 단자를 구비한 기판;A substrate having electrode terminals; 상기 기판의 일면 상에 페이스-다운(Face-Down) 타입으로 부착되며, 본딩패드를 갖는 반도체 칩; A semiconductor chip attached to one surface of the substrate in a face-down type and having a bonding pad; 상기 반도체 칩과 기판 사이에 개재되며, 다수의 도전성 파티클(Particle)을 갖는 이방성 전도 접착제; 및An anisotropic conductive adhesive interposed between the semiconductor chip and the substrate and having a plurality of conductive particles; And 상기 반도체 칩의 본딩패드와 상기 이방성 전도 접착제 사이에 개재되며, 상기 이방성 전도 접착제 내의 파티클과의 접촉 면적이 넓어지도록 오목 형상을 갖는 연결부;A connection part interposed between the bonding pad of the semiconductor chip and the anisotropic conductive adhesive and having a concave shape to widen a contact area with particles in the anisotropic conductive adhesive; 를 포함하는 것을 특징으로 하는 플립 칩 패키지.Flip chip package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 이방성 전도 접착제는 ACF(Anisotropic Conductive Film) 또는 ACP(Anisotropic Conductive Paste)를 포함하는 것을 특징으로 하는 플립 칩 패키지.The anisotropic conductive adhesive includes an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). 제 1 항에 있어서,The method of claim 1, 상기 연결부는 범프로 이루어진 것을 특징으로 하는 플립 칩 패키지.Flip chip package, characterized in that the connection portion made of a bump. 제 3 항에 있어서,The method of claim 3, wherein 상기 범프는 금 스터드 범프를 포함하는 것을 특징으로 하는 플립 칩 패키지.And the bumps comprise gold stud bumps. 제 3 항에 있어서,The method of claim 3, wherein 상기 범프는 니켈 및 금 범프를 포함하는 것을 특징으로 하는 플립 칩 패키지.And the bumps include nickel and gold bumps. 제 1 항에 있어서,The method of claim 1, 상기 연결부는 코이닝(Coining) 방식에 의해 오목한 형상을 갖는 것을 특징으로 하는 플립 칩 패키지.And the connection part has a concave shape by a coining method. 제 1 항에 있어서,The method of claim 1, 상기 기판 타면에 부착된 외부 접속 단자를 더 포함하는 것을 특징으로 하는 플립 칩 패키지.The flip chip package further comprises an external connection terminal attached to the other surface of the substrate.
KR1020080023253A 2008-03-13 2008-03-13 Flip chip package KR20090098076A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101106927B1 (en) * 2009-11-30 2012-01-25 주식회사 심텍 Method for fabricating ultra-silm coreless flip-chip chip scale package
CN105405825A (en) * 2015-12-09 2016-03-16 南通富士通微电子股份有限公司 Chip on film package structure
CN107153307A (en) * 2017-07-10 2017-09-12 武汉华星光电半导体显示技术有限公司 Array base palte and liquid crystal display
US10591788B2 (en) 2017-07-10 2020-03-17 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and liquid crystal display panel

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101106927B1 (en) * 2009-11-30 2012-01-25 주식회사 심텍 Method for fabricating ultra-silm coreless flip-chip chip scale package
CN105405825A (en) * 2015-12-09 2016-03-16 南通富士通微电子股份有限公司 Chip on film package structure
CN107153307A (en) * 2017-07-10 2017-09-12 武汉华星光电半导体显示技术有限公司 Array base palte and liquid crystal display
WO2019010893A1 (en) * 2017-07-10 2019-01-17 武汉华星光电半导体显示技术有限公司 Array substrate and liquid crystal display
US10591788B2 (en) 2017-07-10 2020-03-17 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and liquid crystal display panel
CN107153307B (en) * 2017-07-10 2020-08-04 武汉华星光电半导体显示技术有限公司 Array substrate and liquid crystal display

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