KR100790454B1 - Flip chip package - Google Patents

Flip chip package Download PDF

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Publication number
KR100790454B1
KR100790454B1 KR1020070014042A KR20070014042A KR100790454B1 KR 100790454 B1 KR100790454 B1 KR 100790454B1 KR 1020070014042 A KR1020070014042 A KR 1020070014042A KR 20070014042 A KR20070014042 A KR 20070014042A KR 100790454 B1 KR100790454 B1 KR 100790454B1
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KR
South Korea
Prior art keywords
solder
circuit board
printed circuit
semiconductor chip
flip chip
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Application number
KR1020070014042A
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Korean (ko)
Inventor
이하나
서민석
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주식회사 하이닉스반도체
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Priority to KR1020070014042A priority Critical patent/KR100790454B1/en
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Publication of KR100790454B1 publication Critical patent/KR100790454B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

A flip chip package is provided to adjust easily height of a solder bump by forming the solder bump of a pillar type. A printed circuit board(200) includes an electrode terminal formed at one surface thereof. A semiconductor chip(202) is arranged at a top of the printed circuit board in a face-down manner. The semiconductor chip includes a plurality of bonding pads. A copper pillar(208) is formed to connect the bonding pads of the semiconductor chip with the electrode terminal of the printed circuit board. A sealing agent is used for sealing one surface of the printed circuit board including the copper filler and the semiconductor chip. A first solder and a second solder are inserted between the bonding pads of the semiconductor chip and the copper filler, and between the electrode terminal and the copper filler, respectively.

Description

플립 칩 패키지{Flip chip package}Flip chip package

도 1은 종래의 플립 칩 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional flip chip package.

도 2는 본 발명의 실시예에 따른 플립 칩 패키지를 도시한 단면도.2 is a cross-sectional view illustrating a flip chip package according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

200 : 인쇄회로기판 202 : 반도체칩200: printed circuit board 202: semiconductor chip

204 : 솔더 206 : 본딩 패드204 solder 206 bonding pad

208 : 구리 필러(pillar) 210 : 전극 단자208: copper pillar 210: electrode terminal

212 : 언더필 216 : 볼랜드212: Underfill 216: Borland

218 : 솔더 볼218: Solder Balls

본 발명은 플립 칩 패키지에 관한 것으로, 보다 자세하게는, 100㎛ 이상의 솔더 범프 높이 구현 및 패키지 전체의 신뢰성을 향상시킨 플립 칩 패키지에 관한 것이다.The present invention relates to a flip chip package, and more particularly, to a flip chip package to improve the solder bump height implementation and the reliability of the entire package.

플립 칩 패키지는 고밀도 패키징이 가능한 본딩 프로세스로 반도체 칩의 입출력 패드 위에 전기적 도선 역할을 하는 솔더 범프(solder bump)와 같은 돌출부를 형성시켜 반도체 칩과 기판을 연결하는 것으로 반도체의 동작 속도를 향상시킬 수 있는 반도체 칩 패키지이다. The flip chip package is a bonding process that enables high-density packaging to improve the operation speed of the semiconductor by connecting the semiconductor chip and the substrate by forming protrusions such as solder bumps that serve as electrical conductors on the input / output pads of the semiconductor chip. Is a semiconductor chip package.

또한, 플립 칩 타입 반도체 패키지는 반도체 칩 내부 회로에서 입출력 패드의 위치를 필요에 따라 결정할 수 있으므로 회로 설계를 단순화시키고, 회로선에 의한 저항이 감소하여 소요 전력을 줄일 수 있어 전기적 특성이 우수하고, 반도체 칩의 배면이 외부로 노출되어 있어 열적 특성이 우수하며, 작은 형태의 패키지를 구현할 수 있고, 솔더 자기정력(Self-Alignment) 특성 때문에 본딩이 용이한 장점이 있다.In addition, since the flip chip type semiconductor package can determine the position of the input / output pads in the internal circuit of the semiconductor chip as needed, the circuit design can be simplified, the resistance by the circuit line can be reduced, and the power consumption can be reduced. The rear surface of the semiconductor chip is exposed to the outside, so the thermal characteristics are excellent, a small package can be realized, and the bonding is easy due to the solder self-alignment characteristics.

도 1은 종래 플립 칩 패키지를 도시한 단면도로서 이를 설명하면 다음과 같다.1 is a cross-sectional view illustrating a conventional flip chip package as follows.

도시된 바와 같이, 일측에 다수의 본딩 패드(102)가 형성된 반도체 칩(100)과 상기 반도체 칩(100)의 전기적 신호를 외부에 전달하기 위한 매개체 역할을 하는 인쇄회로기판(112)이 상기 반도체 칩(100) 하부에 배치되며, 상기 반도체 칩(100)의 본딩 패드(102)에는 다수의 언더 범프 메탈러지(Under bump metallurgy : 104)가 형성된다.As illustrated, the semiconductor chip 100 having a plurality of bonding pads 102 formed on one side thereof and a printed circuit board 112 serving as a medium for transmitting electrical signals of the semiconductor chip 100 to the outside are the semiconductor. A plurality of under bump metallurgy 104 is formed on the bonding pads 102 of the semiconductor chip 100.

또한, 상기 언더 범프 메탈러지(104) 및 인쇄회로기판(112)의 전극 단자(118)에 형성되어 전기 신호의 도선 역할을 하는 솔더 범프(106)가 상기 반도체칩(100)과 인쇄회로기판(112) 사이의 영역에 형성되고, 상기 반도체 칩(100)과 인쇄회로기판(112) 사이에 충진되어 솔더 접합부의 피로 수명을 향상시키고 외부 환경으로부터 반도체 칩(100)을 보호하며 솔더 범프(106)가 받는 응력의 일부를 흡수 하는 언더필(Underfill : 108)이 상기 솔더 범프(106), 본딩 패드(102) 및 전극 단자(118)를 포함하도록 밀봉된다.In addition, a solder bump 106 formed on the under bump metallage 104 and the electrode terminal 118 of the printed circuit board 112 to serve as a conductor of an electrical signal is formed of the semiconductor chip 100 and the printed circuit board ( Formed in an area between the 112 and filled between the semiconductor chip 100 and the printed circuit board 112 to improve the fatigue life of the solder joint, protect the semiconductor chip 100 from the external environment, and solder bumps 106. An underfill 108 that absorbs a portion of the stress received is sealed to include the solder bumps 106, the bonding pads 102, and the electrode terminals 118.

그리고, 외부 환경으로부터 상기 반도체 칩(100)을 보호하기 위하여 반도체 칩(100)과 언더필(108) 등을 봉지하도록 EMC(Epoxy Molding Compound)와 같은 물질로 이루어진 봉지제(110)가 형성되며, 상기 인쇄회로기판(112)의 하면에 구비된 볼랜드(114)에는 다수의 솔더 볼(116)이 융착된다.In addition, an encapsulant 110 made of a material such as an epoxy molding compound (EMC) is formed to encapsulate the semiconductor chip 100 and the underfill 108 in order to protect the semiconductor chip 100 from an external environment. A plurality of solder balls 116 are fused to the ball lands 114 provided on the bottom surface of the printed circuit board 112.

그러나, 자세하게 도시하고 설명하지는 않았지만, 상기와 같은 솔더 범프를 이용한 플립 칩 패키지는 상기 솔더 범프의 높이를 100㎛ 이상 구현하고자 할 경우, 상기 솔더 범프가 구와 같은 형상을 하고 있어 리플로우(reflow) 공정 수행 후 좌측 또는 우측으로의 변형이 발생하기 때문에 상기와 같은 범위의 높이를 구현하기 힘들다.However, although not illustrated and described in detail, in the flip chip package using the solder bump as described above, when the solder bump is to have a height of 100 μm or more, the solder bump has a spherical shape, such as a reflow process. Since deformation to the left or right occurs after the execution, it is difficult to implement the height in the above range.

또한, 파인-피치(Fine-pitch)에서 상기와 같은 솔더 범프를 적용하게 되면 리플로우시 좁은 간격과 솔더 범프의 구형인 형상으로 인해 솔더 범프 간의 브릿지가 발생하게 되어, 200㎛ 이하의 파인 피치 플립 칩 패키지를 구현할 수 없게 된다.In addition, if the above solder bumps are applied in fine-pitch, bridges between the solder bumps are generated due to the narrow spacing and the spherical shape of the solder bumps during reflow, and the fine pitch flip of 200 μm or less You will not be able to implement the chip package.

따라서, 상기와 같은 솔더 범프 간의 문제점들로 인해 전체 플립 칩 패키지의 신뢰성이 저하되게 된다.Therefore, the reliability of the entire flip chip package is lowered due to the problems between the solder bumps.

따라서, 본 발명은 솔더 범프의 높이를 100㎛ 이상 구현시킨 플립 칩 패키지를 제공한다.Accordingly, the present invention provides a flip chip package in which the height of solder bumps is 100 μm or more.

또한, 본 발명은 리플로우(reflow) 공정 후 솔더 범프 간의 브릿지를 억제하여 200㎛이하의 파인-피치(fine-pitch)를 구현할 수 있는 플립 칩 패키지를 제공한다.In addition, the present invention provides a flip chip package that can implement a fine-pitch of 200 μm or less by suppressing a bridge between solder bumps after a reflow process.

게다가, 본 발명은 전체 패키지의 신뢰성 저하를 방지할 수 있는 플립 칩 패키지를 제공한다.In addition, the present invention provides a flip chip package which can prevent the degradation of the reliability of the entire package.

일 실시예에 있어서 플립 칩 패키지는, 일면에 다수의 전극 단자를 구비한 인쇄회로기판; 상기 인쇄회로기판 상부에 페이스-다운(face-down) 타입으로 배치되며, 다수의 본딩 패드를 구비한 반도체칩; 상기 반도체칩의 본딩 패드와 인쇄회로기판의 전극 단자 간을 연결시키는 구리 필러(pillar); 및 상기 구리 필러 및 반도체칩을 포함한 인쇄회로기판의 일면을 밀봉하는 봉지제;를 포함한다.In one embodiment, a flip chip package includes: a printed circuit board having a plurality of electrode terminals on one surface thereof; A semiconductor chip disposed in a face-down type on the printed circuit board and having a plurality of bonding pads; A copper pillar connecting the bonding pad of the semiconductor chip and the electrode terminal of the printed circuit board; And an encapsulant for sealing one surface of the printed circuit board including the copper filler and the semiconductor chip.

상기 반도체칩의 본딩패드와 구리 필러 및 상기 인쇄회로기판의 전극 단자와 구리 필러 사이 각각에 개재된 제1솔더 및 제2솔더를 더 포함한다.And a first solder and a second solder interposed between the bonding pad and the copper filler of the semiconductor chip and the electrode terminal and the copper filler of the printed circuit board.

상기 본딩패드는 구리 필러 및 제1솔더가 개재되어 형성된 것을 특징으로 한다.The bonding pad may be formed by interposing a copper filler and a first solder.

상기 전극단자는 제2솔더가 개재되어 형성된 것을 특징으로 한다.The electrode terminal is characterized in that formed through the second solder.

상기 인쇄회로기판은 타면에 부착된 솔더 볼을 더 포함한다.The printed circuit board further includes a solder ball attached to the other surface.

(실시예)(Example)

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 필러(pillar) 형태의 구리로 이루어지고 상기 구리 필러 상부 및 하부에 각 솔더로 이루어진 솔더 범프를 이용하여 플립 칩 패키지를 구성한다.The present invention constitutes a flip chip package using solder bumps made of copper in a pillar shape and each solder is formed on upper and lower portions of the copper filler.

이 경우, 구의 형상으로 이루어진 솔더 범프를 이용하는 종래의 플립 칩 패키지와 달리, 솔더 범프가 필러 형태로 이루어짐으로써 솔더 범프의 높이를 100㎛ 이상뿐만 아니라 그에 따른 솔더 범프의 높이 조절을 수월하게 조절할 수 있다.In this case, unlike a conventional flip chip package using a solder bump formed in the shape of a sphere, the solder bumps are formed in the form of a filler, so that the height of the solder bumps can be easily adjusted as well as the height of the solder bumps accordingly. .

또한, 미세 피치(pitch) 구현시 구형으로 이루어진 솔더 범프와 달리 필러 형태의 솔더 범프를 이용함으로써 리플로우(reflow) 공정 수행 후 상기 솔더 범프가 좌측 및 우측으로의 변형으로 유발되어 발생하는 솔더 범프들 간의 브릿지(bridge)를 방지할 수 있어, 그에 따른 200㎛ 이하의 미세 피치 플립 칩 패키지를 구현할 수 있다.In addition, unlike the spherical solder bumps, the solder bumps are caused by deformation of the solder bumps to the left and the right sides after the reflow process, unlike the spherical solder bumps. It is possible to prevent the bridge (bridge) between the, it is possible to implement a fine pitch flip chip package of 200㎛ or less accordingly.

따라서, 플립 칩 패키지의 전체 신뢰성을 향상시킬 수 있다.Therefore, the overall reliability of the flip chip package can be improved.

자세하게, 도 2는 본 발명의 실시예에 따른 플립 칩 패키지를 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, Figure 2 is a cross-sectional view showing a flip chip package according to an embodiment of the present invention, as follows.

도시된 바와 같이, 일면에 회로패턴이 형성되고, 다수의 전극 단자(210)를 구비한 인쇄회로기판(200) 상에 다수의 본딩 패드(206)를 구비한 반도체칩(202)이 페이스-다운(face-down) 타입으로 배치되며, 상기 반도체칩(202)의 본딩 패드(206)와 인쇄회로기판(200)의 전극 단자(210)간이 솔더 범프를 매개로 전기적으로 연결된다.As shown, a circuit pattern is formed on one surface, and the semiconductor chip 202 having a plurality of bonding pads 206 is face-down on a printed circuit board 200 having a plurality of electrode terminals 210. It is disposed in a face-down type and is electrically connected between the bonding pad 206 of the semiconductor chip 202 and the electrode terminal 210 of the printed circuit board 200 via solder bumps.

여기서, 상기 솔더 범프는 구리로 이루진 구리 필러(pillar : 208)를 갖으며, 상기 구리 필러(208) 상부 및 하부에는 솔더(204)가 형성되어 각 상부 및 하부 의 솔더(204) 및 구리 필러(208)의 적층구조로 형성된다.Here, the solder bump has a copper filler (208) made of copper, the solder 204 is formed on the upper and lower portions of the copper filler 208, the solder 204 and the copper filler of the upper and lower portions, respectively. 208 is formed in a laminated structure.

즉, 상기 반도체칩(202)의 본딩 패드(206)에 상부 솔더(204)가 형성되고, 상기 인쇄회로기판(200)의 전극 단자(210) 상에 하부 솔더(204)가 형성되며, 상기 상부 솔더(204) 및 하부 솔더(204) 사이에 구리 필러(208)가 형성된 구조이다.That is, an upper solder 204 is formed on the bonding pad 206 of the semiconductor chip 202, and a lower solder 204 is formed on the electrode terminal 210 of the printed circuit board 200. The copper filler 208 is formed between the solder 204 and the lower solder 204.

또한, 상기 솔더 범프를 포함한 인쇄회로기판(200)과 반도체칩(202) 사이의 공간이 언더필과 같은 충진재(212) 물질로 충진되며, 상기 충진재(212) 및 반도체칩(208)을 포함하는 인쇄회로기판(200)의 일면이 외부의 스트레스로부터 보호하기 위해 EMC(epoxy mo;ding compound)와 같은 봉지제(214)로 밀봉된다.In addition, a space between the printed circuit board 200 including the solder bumps and the semiconductor chip 202 is filled with a filler 212 material such as underfill, and includes a print including the filler 212 and the semiconductor chip 208. One surface of the circuit board 200 is sealed with an encapsulant 214 such as an epoxy moding compound (EMC) to protect it from external stress.

한편, 상기 인쇄회로기판(200)의 타면에는 볼랜드(216)가 형성되고, 상기 볼랜드(216)에는 실장부재로서 다수의 솔더볼(218)이 부착된다.Meanwhile, a ball land 216 is formed on the other surface of the printed circuit board 200, and a plurality of solder balls 218 are attached to the ball land 216 as mounting members.

이 경우, 본 발명은 구의 형상으로 이루어진 솔더 범프를 이용하는 종래의 플립 칩 패키지와 달리, 솔더 범프가 필러 형태로 이루어짐으로써 솔더 범프의 높이를 100㎛ 이상뿐만 아니라 그에 따른 솔더 범프의 높이 조절을 수월하게 조절할 수 있다.In this case, the present invention, unlike the conventional flip chip package using a solder bump formed in the shape of a sphere, the solder bump is made in the form of a filler to facilitate the height adjustment of the solder bump as well as the height of the solder bumps more than 100㎛ I can regulate it.

또한, 미세 피치(pitch) 구현시 구형으로 이루어진 솔더 범프와 달리 필러 형태의 솔더 범프를 이용함으로써 리플로우(reflow) 공정 수행 후 상기 솔더 범프가 좌측 및 우측으로의 변형으로 유발되어 발생하는 솔더 범프들 간의 브릿지(bridge)를 방지할 수 있어, 그에 따른 200㎛ 이하의 미세 피치 플립 칩 패키지를 구현할 수 있다.In addition, unlike the spherical solder bumps, the solder bumps are caused by deformation of the solder bumps to the left and the right sides after the reflow process, unlike the spherical solder bumps. It is possible to prevent the bridge (bridge) between the, it is possible to implement a fine pitch flip chip package of 200㎛ or less accordingly.

따라서, 플립 칩 패키지의 전체 신뢰성을 향상시킬 수 있다.Therefore, the overall reliability of the flip chip package can be improved.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

이상에서와 같이 본 발명은, 솔더 범프가 필러 형태로 이루어짐으로써 솔더 범프의 높이를 100㎛ 이상뿐만 아니라 그에 따른 솔더 범프의 높이 조절을 수월하게 조절할 수 있다.As described above, in the present invention, the solder bumps are formed in the form of a filler, so that the height of the solder bumps is not less than 100 μm, and thus the height adjustment of the solder bumps can be easily adjusted.

또한, 본 발명은 미세 피치(pitch) 구현시 구형으로 이루어진 솔더 범프와 달리 필러 형태의 솔더 범프를 이용함으로써 리플로우(reflow) 공정 수행 후 상기 솔더 범프가 좌측 및 우측으로의 변형으로 유발되어 발생하는 솔더 범프들 간의 브릿지(bridge)를 방지할 수 있어, 그에 따른 200㎛ 이하의 미세 피치 플립 칩 패키지를 구현할 수 있다.In addition, the present invention, unlike the spherical solder bumps when the fine pitch (pitch) is implemented by using the filler-shaped solder bumps after the reflow process performed by the solder bumps caused by deformation to the left and right Bridges between the solder bumps can be prevented, thereby realizing a fine pitch flip chip package of 200 μm or less.

따라서, 본 발명은 플립 칩 패키지의 전체 신뢰성을 향상시킬 수 있다.Therefore, the present invention can improve the overall reliability of the flip chip package.

Claims (5)

일면에 다수의 전극 단자를 구비한 인쇄회로기판;A printed circuit board having a plurality of electrode terminals on one surface thereof; 상기 인쇄회로기판 상부에 페이스-다운(face-down) 타입으로 배치되며, 다수의 본딩 패드를 구비한 반도체칩;A semiconductor chip disposed in a face-down type on the printed circuit board and having a plurality of bonding pads; 상기 반도체칩의 본딩 패드와 인쇄회로기판의 전극 단자 간을 연결시키는 구리 필러(pillar); 및A copper pillar connecting the bonding pad of the semiconductor chip and the electrode terminal of the printed circuit board; And 상기 구리 필러 및 반도체칩을 포함한 인쇄회로기판의 일면을 밀봉하는 봉지제;An encapsulant for sealing one surface of the printed circuit board including the copper filler and the semiconductor chip; 를 포함하는 것을 특징으로 하는 플립 칩 패키지.Flip chip package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 반도체칩의 본딩패드와 구리 필러 및 상기 인쇄회로기판의 전극 단자와 구리 필러 사이 각각에 개재된 제1솔더 및 제2솔더를 더 포함하는 것을 특징으로 하는 플립 칩 패키지.And a first solder and a second solder interposed between the bonding pad and the copper filler of the semiconductor chip and the electrode terminal and the copper filler of the printed circuit board. 제 1 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 본딩패드는 구리 필러 및 제1솔더가 개재되어 형성된 것을 특징으로 하는 플립 칩 패키지.The bonding pad is a flip chip package, characterized in that formed by interposing a copper filler and a first solder. 제 1 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 전극단자는 제2솔더가 개재되어 형성된 것을 특징으로 하는 플립 칩 패키지.The electrode terminal is a flip chip package, characterized in that formed by interposing a second solder. 제 1 항에 있어서,The method of claim 1, 상기 인쇄회로기판은 타면에 부착된 솔더 볼을 더 포함하는 것을 특징으로 하는 플립 칩 패키지.The printed circuit board further comprises a flip chip package comprising a solder ball attached to the other surface.
KR1020070014042A 2007-02-09 2007-02-09 Flip chip package KR100790454B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040055734A (en) * 2001-03-28 2004-06-26 인텔 코오퍼레이션 Fluxless flip chip interconnection

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040055734A (en) * 2001-03-28 2004-06-26 인텔 코오퍼레이션 Fluxless flip chip interconnection

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
한국 특허공개공보 1020040055734호

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