KR101453328B1 - Semiconductor Package - Google Patents

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KR101453328B1
KR101453328B1 KR1020120000152A KR20120000152A KR101453328B1 KR 101453328 B1 KR101453328 B1 KR 101453328B1 KR 1020120000152 A KR1020120000152 A KR 1020120000152A KR 20120000152 A KR20120000152 A KR 20120000152A KR 101453328 B1 KR101453328 B1 KR 101453328B1
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semiconductor chip
substrate
semiconductor
lead frame
conductive material
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KR1020120000152A
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Korean (ko)
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KR20130078961A (en
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박병규
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박병규
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

본 발명은 반도체 패키지 및 반도체 패키지 방법에 관한 것으로, 더욱 상세하게는 플립 칩(Flip Chip)과 기판 또는 리드 프레임의 연결 구조에 관한 것이다.
이를 위해 본 발명의 반도체 패키지는 기판, 상기 기판의 상단에 적층되는 제1반도체 칩, 상기 기판과 상기 제1반도체 칩은 도전성 물질로 전기적으로 결합되어 있음을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a semiconductor package method, and more particularly to a connection structure of a flip chip and a substrate or a lead frame.
To this end, the semiconductor package of the present invention is characterized in that the substrate, the first semiconductor chip stacked on the top of the substrate, and the substrate and the first semiconductor chip are electrically coupled by a conductive material.

Description

반도체 패키지 및 반도체 패키지 방법{Semiconductor Package}Semiconductor package and semiconductor package method

본 발명은 반도체 패키지 및 반도체 패키지 방법에 관한 것으로, 더욱 상세하게는 플립 칩(Flip Chip)과 기판 또는 리드 프레임의 연결 구조에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a semiconductor package method, and more particularly to a connection structure of a flip chip and a substrate or a lead frame.

플립 칩은 반도체 칩을 회로 기판에 부착시킬 때 금속 리드(와이어)와 같은 추가적인 연결구조나 볼그리드어레이(BGA)와 같은 중간 매체를 사용하지 않고 칩 아랫면의 전극 패턴을 이용해 그대로 융착시키는 방식을 의미한다. 따라서 패키지가 칩 크기와 같아 소형, 경량화에 유리하고, 전극간 거리(피치)를 훨씬 미세하게 할 수 있어 선 없는(leadless) 반도체라고 부른다. A flip chip means a method of attaching a semiconductor chip to a circuit board without using an additional connection structure such as a metal lead (wire) or an intermediate medium such as a ball grid array (BGA) do. Therefore, the package is the same size as the chip, which is advantageous for miniaturization and weight reduction, and the distance (pitch) between the electrodes can be much finer, which is called a leadless semiconductor.

상술한 바와 같이 플립칩은 PCB나 리드-프레임(lead-frame) 같은 패키지 캐리어(carrier)와 다이(die; 칩)를 전기적으로 연결하는 하나의 방식을 의미한다. As described above, the flip chip refers to a method of electrically connecting a package carrier such as a PCB or a lead-frame to a die.

일반적인 패키지에서 다이와 캐리어의 접합은 와이어(wire)를 이용한다. 다이는 캐리어의 표면에 접착되고, 와이어로 다이와 캐리어를 연결하게 된다. 와이어는 대체로 길이가 1~5mm정도이다. 반면 플립칩 패키지에서 다이와 캐리어의 접합은 다이 표면에 형성된 도체물질인 '범프(bump; 융기 또는 혹)'에 의해 이루어진다. 즉, 다이에 범프를 형성시킨 후 범프가 형성된 면을 캐리어에 직접 접합하게 되는 것이다. In a typical package, the die and carrier are connected using a wire. The die is bonded to the surface of the carrier, and the wire connects the die and the carrier. The wire is usually 1 to 5 mm long. On the other hand, in the flip chip package, the bonding of the die and the carrier is made by a bump (bump) which is a conductive material formed on the die surface. That is, after the bumps are formed on the die, the surface on which the bumps are formed is directly bonded to the carrier.

플립칩 접합은 일반적으로 솔더(solder)를 이용한다. 솔더 범프(bump)가 형성된 다이는 BGA볼을 외부 기판과 연결할 때 사용하는 공정과 유사한 솔더 리플로우(reflow) 공정을 통해 기판에 접합한다. 다이가 접합이 되면, 다이와 기판의 사이는 언더필(underfill)을 사용하여 보강한다. 언더필(underfill)이란 다이와 캐리어의 틈을 보강하기 위한 용도로 개발된 전용 에폭시(epoxy)를 의미한다. 언더필(underfill)이 사용되는 이유는 실리콘 다이와 캐리어가 열에 의한 팽창율이 다름에 따라 솔더 접합점에 가해지는 충격(stress)를 완화하기 위해서이다.Flip chip bonding generally uses a solder. The die on which the solder bump is formed is bonded to the substrate through a solder reflow process similar to the process used to connect the BGA ball to an external substrate. When the die is bonded, the gap between the die and the substrate is reinforced using an underfill. Underfill means a dedicated epoxy developed to reinforce the gap between the die and the carrier. The reason that underfill is used is to alleviate the stress applied to the solder joint as the silicon die and carrier are different in thermal expansion coefficient.

큐어(cure) 공정을 거치고 나면, 언더필은 충격을 흡수하고, 솔더 범프에 가해지는 장력을 감소시키며, 궁극적으로 최종 패키지의 수명을 늘리는 효과가 있다. After undergoing a cure process, underfill absorbs impact, reduces the tension on the solder bumps, and ultimately increases the life of the final package.

플립칩의 기본적인 공정은 바로 이 칩을 접합하는 공정과 언더필(underfill) 공정이라고 할 수 있겠다. 이 외에도 다이 주변의 패키지 구조의 나머지 부분은 여러가지 형태를 취할 수 있고, 따라서 일반적인 패키지 공정을 준용할 수 있다. The basic process of flip chip is the bonding process and the underfill process. In addition, the remainder of the package structure around the die can take many forms, so that the general packaging process can be used in common.

도 1을 참조하면, 리드 프레임 패드(11) 위에 제1반도체 칩(20)이 올려진다. 이때, 제1반도체 칩(20)의 접속 범프(21)가 리드(12) 위에 플립칩 본딩된다.Referring to FIG. 1, a first semiconductor chip 20 is mounted on a lead frame pad 11. At this time, the connection bumps 21 of the first semiconductor chip 20 are flip-chip bonded onto the leads 12.

플립칩 본딩된 제1 반도체 칩(20) 위에 필름이나 에폭시로 제2반도체 칩(30)을 부착한 후 리드(12)에 제2반도체 칩(30)을 와이어 본딩(51)한다. 그리고 와이어 본딩된 제2 반도체 칩(30) 위에 필름이나 에폭시로 다시 제3 반도체 칩(40)을 부착한 후 리드(12)에 제3 반도체 칩(40)을 와이어 본딩(52)한다.The second semiconductor chip 30 is attached to the flip chip bonded first semiconductor chip 20 with a film or epoxy and then the second semiconductor chip 30 is wire bonded 51 to the lead 12. Then, the third semiconductor chip 40 is attached to the wire-bonded second semiconductor chip 30 by a film or epoxy, and then the third semiconductor chip 40 is wire-bonded 52 to the lead 12.

그런데 제2, 제3 반도체 칩(30, 40)을 제1 반도체 칩(20) 즉 플립칩 위에 연속적으로 부착하고 와이어 본딩하는 과정에서 제1 반도체 칩(20)에 스트레스가 가해진다. 제1 반도체 칩(20)에 가해지는 스트레스로 인하여 제1 반도체 칩(20) 또는 제1 반도체 칩(20)의 플립칩 범프(21)에 크랙이 유발되어 패키지의 품질이 저하될 수 있다.Stress is applied to the first semiconductor chip 20 during the process of continuously attaching the second and third semiconductor chips 30 and 40 on the first semiconductor chip 20, that is, the flip chip. The stress applied to the first semiconductor chip 20 may cause a crack in the flip chip bumps 21 of the first semiconductor chip 20 or the first semiconductor chip 20 and the quality of the package may be deteriorated.

또한, 반도체 칩들(20, 30, 40)이 한 방향으로 적층되기 때문에 본딩 와이어(51, 52)의 길이가 길어지고 와이어 본딩 공정이 어려워지고, 전체 패키지의의 두께가 두꺼워 진다.
Further, since the semiconductor chips 20, 30, and 40 are stacked in one direction, the length of the bonding wires 51 and 52 becomes long, the wire bonding process becomes difficult, and the thickness of the entire package becomes thick.

본 발명이 해결하려는 과제는 와이어 본딩 공정에서 발생하는 와이어 숏트(short)나 오픈(open) 현상으로 발생하는 불량을 감소시킬 수 있는 방안을 제안함에 있다.A problem to be solved by the present invention is to propose a method for reducing defects caused by a wire short or an open phenomenon occurring in a wire bonding process.

본 발명이 해결하려는 다른 과제는 고가의 금(Au) 와이어를 이용하여 본딩을 수행함으로 발생하는 비용 문제를 해결할 수 있는 방안을 제안함에 있다.Another problem to be solved by the present invention is to propose a method for solving cost problems caused by performing bonding using an expensive gold (Au) wire.

본 발명이 해결하려는 또 다른 과제는 구리(Cu) 와이어를 사용함으로써 발생하는 산화 문제를 해결할 수 있는 방안을 제안함에 있다.Another problem to be solved by the present invention is to propose a solution to solve the oxidation problem caused by using copper (Cu) wire.

본 발명이 해결하려는 또 다른 과제는 반도체 패키지의 두께를 감소시킬 수 있는 방안을 제안함에 있다.
Another object of the present invention is to propose a method of reducing the thickness of a semiconductor package.

이를 위해 본 발명의 반도체 패키지는 기판, 상기 기판의 상단에 적층되는 제1반도체 칩, 상기 기판과 상기 제1반도체 칩은 도전성 물질로 전기적으로 결합되어 있음을 특징으로 한다.To this end, the semiconductor package of the present invention is characterized in that the substrate, the first semiconductor chip stacked on the top of the substrate, and the substrate and the first semiconductor chip are electrically coupled by a conductive material.

이를 위해 본 발명의 반도체 패키지는 리드 프레임, 상기 리드 프레임의 상단에 적층되는 제1반도체 칩, 상기 리드 프레임과 상기 제1반도체 칩은 도전성 물질로 전기적으로 결합되어 있음을 특징으로 한다.
To this end, the semiconductor package of the present invention is characterized in that the lead frame, the first semiconductor chip stacked on the top of the lead frame, and the lead frame and the first semiconductor chip are electrically coupled to each other by a conductive material.

현재 와이어를 사용하여 칩과 리드 프레임 또는 기판을 연결 하게 되지만, 칩과 리드 프레임, 기판을 도전성 접착제를 사용하여 연결하면 와이어 본딩 공정을 없앨 수 있고, Au Wire, Cu Wire를 사용하지 않고도 보다 좋은 특성을 가지며 동시에 반도체 가격을 낮출 수 있게 된다. 또한 와이어 본딩시 발생되는 Wire Short , Wire Open 현상을 제거할 수 있게 된다.
Currently, wires are used to connect the chip to the lead frame or substrate. However, if the chip, lead frame, and substrate are connected using a conductive adhesive, the wire bonding process can be eliminated and better characteristics can be achieved without using Au Wire or Cu Wire And at the same time lower the price of semiconductors. In addition, it is possible to eliminate wire short and wire open phenomenon that occurs when wire bonding is performed.

도 1은 종래 반도체 칩 패키지 방식을 도시하고 있다,
도 2는 본 발명의 일실시 예에 따른 PCB 또는 플렉시블(flexible) PCB를 포함하는 기판에 반도체 칩을 적층하는 반도체 패키지를 도시하고 있다.
도 3은 본 발명의 일실시 예에 따른 PCB 또는 플렉시블 PCB를 포함하는 기판에 반도체 칩을 적층하는 다른 형태의 반도체 패키지를 도시하고 있다.
도 4는 본 발명의 일실시 예에 따른 도 3에 도시되어 있는 반도체 패키지를 상부에서 바라본 도면이다.
도 5는 본 발명의 일실시 예에 따른 리드 프레임에 반도체 칩을 적층하는 반도체 패키지를 도시하고 있다.
도 6은 본 발명의 일실시 예에 따른 리드 프레임에 반도체 칩을 적층하는 다른 형태의 반도체 패키지를 도시하고 있다.
도 7은 본 발명의 일실시 예에 따른 도 6에 도시되어 있는 반도체 패키지를 상부에서 바라본 도면이다.1 shows a conventional semiconductor chip package system,
2 shows a semiconductor package for stacking semiconductor chips on a substrate including a PCB or a flexible PCB according to an embodiment of the present invention.
3 illustrates another type of semiconductor package for stacking semiconductor chips on a substrate including a PCB or a flexible PCB according to an embodiment of the present invention.
FIG. 4 is a top view of the semiconductor package shown in FIG. 3 according to an embodiment of the present invention.
5 shows a semiconductor package for stacking semiconductor chips on a lead frame according to an embodiment of the present invention.
6 illustrates another type of semiconductor package for stacking semiconductor chips on a lead frame according to an embodiment of the present invention.
FIG. 7 is a top view of the semiconductor package shown in FIG. 6 according to an embodiment of the present invention.

전술한, 그리고 추가적인 본 발명의 양상들은 첨부된 도면을 참조하여 설명되는 바람직한 실시 예들을 통하여 더욱 명백해질 것이다. 이하에서는 본 발명의 이러한 실시 예를 통해 당업자가 용이하게 이해하고 재현할 수 있도록 상세히 설명하기로 한다.BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and further aspects of the present invention will become more apparent from the following detailed description of preferred embodiments with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

도 2는 본 발명의 일실시 예에 따른 기판에 반도체 칩을 적층하는 반도체 패키지를 도시하고 있다. 이하 도 2를 이용하여 본 발명의 일실시 예에 따른 기판에 반도체 칩을 적층하는 반도체 패키지에 대해 상세하게 알아보기로 한다. 기판은 PCB 또는 플렉시블 PCB를 포함한다.2 shows a semiconductor package for stacking semiconductor chips on a substrate according to an embodiment of the present invention. Hereinafter, a semiconductor package for stacking semiconductor chips on a substrate according to an embodiment of the present invention will be described in detail with reference to FIG. The substrate includes a PCB or a flexible PCB.

도 2에 의하면, 반도체 패키지는 기판, 반도체 칩, 기판과 반도체 칩을 전기적으로 결합하는 도전성 물질을 포함한다. According to Fig. 2, the semiconductor package includes a substrate, a semiconductor chip, and a conductive material that electrically couples the substrate and the semiconductor chip.

반도체 패키지에서 기판(200)과 반도체 칩(202)을 전기적으로 결합하는 도전성 물질(204)을 도포하는 과정은 다음과 같이 수행된다. 먼저, 기판(200)의 상단에 도전성 물질(204)을 도포한 후 기판(200)과 반도체 칩(202)을 전기적으로 결합한다. 또는 반도체 칩(202)의 패드(PAD)에 도전성 물질(204)을 도포한 후 기판(200)과 반도체 칩(202)을 전기적으로 결합할 수 있다. 부가하여 기판(200)과 반도체 칩(202)을 전기적으로 결합할 필요가 없는 부분은 접착제를 이용하여 기판(200)과 반도체 칩(202)을 결합한다. 이와 같이 기판(200)과 반도체 칩(202)을 전기적으로 결합할 필요가 없는 부분은 접착제를 이용하여 접착함으로서 기판(200)과 반도체 칩(202)을 안정적으로 결합할 수 있게 된다.The process of applying the conductive material 204 electrically connecting the substrate 200 and the semiconductor chip 202 in the semiconductor package is performed as follows. First, a conductive material 204 is applied to the top of the substrate 200, and then the substrate 200 and the semiconductor chip 202 are electrically coupled to each other. Alternatively, the conductive material 204 may be applied to the pad PAD of the semiconductor chip 202, and then the substrate 200 and the semiconductor chip 202 may be electrically coupled. In addition, a portion where the substrate 200 and the semiconductor chip 202 do not need to be electrically coupled, the substrate 200 and the semiconductor chip 202 are bonded using an adhesive. The substrate 200 and the semiconductor chip 202 can be stably bonded by bonding the substrate 200 and the semiconductor chip 202 without bonding them electrically with an adhesive.

도 3은 본 발명의 일실시 예에 따른 기판에 반도체 칩을 적층하는 다른 반도체 패키지를 도시하고 있다. 이하 도 3을 이용하여 본 발명의 일실시 예에 따른 기판에 반도체 칩을 적층하는 반도체 패키지에 대해 상세하게 알아보기로 한다.3 shows another semiconductor package for stacking semiconductor chips on a substrate according to an embodiment of the present invention. Hereinafter, a semiconductor package for stacking semiconductor chips on a substrate according to an embodiment of the present invention will be described in detail with reference to FIG.

도 3에 의하면, 반도체 패키지는 기판, 제1반도체 칩, 제2반도체 칩, 기판과 제1반도체 칩을 전기적으로 결합하는 도전성 물질, 기판과 제2 반도체 칩을 결합하는 와이어를 포함한다.According to Fig. 3, the semiconductor package includes a substrate, a first semiconductor chip, a second semiconductor chip, a conductive material electrically connecting the substrate and the first semiconductor chip, and a wire coupling the substrate and the second semiconductor chip.

도 3에 의하면, 기판(300)의 상단에 제1반도체 칩(302)이 적층되며, 제1반도체 칩(302)의 상단에 제2반도체 칩(304)이 적층된다. 반도체 패키지에서 기판(300)과 제1반도체 칩(302)을 전기적으로 결합하는 도전성 물질(306)을 도포하는 과정은 다음과 같이 수행된다. 먼저, 기판(300)의 상단에 도전성 물질(306)을 도포한 후 기판(300)과 제1반도체 칩(302)을 전기적으로 결합한다. 또는 제1반도체 칩(302)의 패드(PAD)에 도전성 물질(306)을 도포한 후 기판(300)과 제1반도체 칩(302)을 전기적으로 결합할 수 있다. 또한 제2반도체 칩(304)과 기판(300)은 와이어(308)를 이용하여 전기적으로 결합한다. 이와 같이 기판(300)은 제1반도체 칩(302)과 도전성 물질(306)로 전기적으로 결합되며, 제2반도체 칩(304)과 와이어(308)로 전기적 결합된다.Referring to FIG. 3, a first semiconductor chip 302 is stacked on an upper end of a substrate 300, and a second semiconductor chip 304 is stacked on an upper end of a first semiconductor chip 302. The process of applying the conductive material 306 electrically connecting the substrate 300 and the first semiconductor chip 302 in the semiconductor package is performed as follows. First, a conductive material 306 is applied to the top of the substrate 300, and then the substrate 300 and the first semiconductor chip 302 are electrically coupled. Alternatively, the conductive material 306 may be applied to the pad PAD of the first semiconductor chip 302, and then the substrate 300 and the first semiconductor chip 302 may be electrically coupled. The second semiconductor chip 304 and the substrate 300 are electrically coupled to each other using a wire 308. The substrate 300 is electrically coupled to the first semiconductor chip 302 by the conductive material 306 and is electrically coupled to the second semiconductor chip 304 by the wire 308. [

부가하여 기판(300)과 제1반도체 칩(302)을 전기적으로 결합할 필요가 없는 부분, 제1반도체 칩(302)과 제2반도체 칩(304)은 접착제를 이용하여 결합한다. 이와 같이 기판(300)과 제1반도체 칩(302)을 전기적으로 결합할 필요가 없는 부분, 제1반도체 칩(302)과 제2반도체 칩(304)은 접착제를 이용하여 접착함으로서 안정적으로 결합할 수 있게 된다.In addition, the first semiconductor chip 302 and the second semiconductor chip 304 do not need to electrically couple the substrate 300 and the first semiconductor chip 302 to each other. As described above, the first semiconductor chip 302 and the second semiconductor chip 304, which do not need to be electrically coupled to the substrate 300 and the first semiconductor chip 302, are bonded together using an adhesive, .

도 4는 본 발명의 일실시 예에 따른 도 3에 도시되어 있는 반도체 패키지를 상부에서 바라본 도면이다. 도 4에 의하면, 기판과 제1반도체 칩은 도전성 물질로 전기적으로 연결되며, 기판과 제2반도체 칩은 와이어를 이용하여 전기적으로 연결된다.FIG. 4 is a top view of the semiconductor package shown in FIG. 3 according to an embodiment of the present invention. Referring to FIG. 4, the substrate and the first semiconductor chip are electrically connected by a conductive material, and the substrate and the second semiconductor chip are electrically connected by using a wire.

도 5는 본 발명의 일실시 예에 따른 리드 프레임에 반도체 칩을 적층하는 반도체 패키지를 도시하고 있다. 이하 도 5를 이용하여 본 발명의 일실시 예에 따른 리드 프레임에 반도체 칩을 적층하는 반도체 패키지에 대해 상세하게 알아보기로 한다.5 shows a semiconductor package for stacking semiconductor chips on a lead frame according to an embodiment of the present invention. Hereinafter, a semiconductor package for stacking semiconductor chips on a lead frame according to an embodiment of the present invention will be described in detail with reference to FIG.

도 5에 의하면, 반도체 패키지는 리드 프레임, 반도체 칩, 리드 프레임과 반도체 칩을 전기적으로 결합하는 도전성 물질을 포함한다.According to Fig. 5, the semiconductor package includes a lead frame, a semiconductor chip, and a conductive material electrically connecting the lead frame and the semiconductor chip.

반도체 패키지는 리드 프레임(500)과 반도체 칩(502)을 전기적으로 결합하는 도전성 물질(504)을 도포하는 과정은 다음과 같이 수행된다. 먼저, 리드 프레임(500)의 상단 또는 LOC Type의 리드 프레임의 하단에 도전성 물질(504)을 도포한 후 기판(500)과 반도체 칩(502)을 전기적으로 결합한다. 또는 반도체 칩(502)의 하단에 도전성 물질(504)을 도포한 후 리드 프레임(500)과 반도체 칩(502)을 전기적으로 결합할 수 있다. The process of applying the conductive material 504 that electrically couples the lead frame 500 and the semiconductor chip 502 to the semiconductor package is performed as follows. First, a conductive material 504 is applied to the upper end of the lead frame 500 or the lower end of the LOC type lead frame, and then the substrate 500 and the semiconductor chip 502 are electrically coupled. Or the conductive material 504 may be applied to the lower end of the semiconductor chip 502 and then the lead frame 500 and the semiconductor chip 502 may be electrically coupled.

도 6은 본 발명의 일실시 예에 따른 리드 프레임에 반도체 칩을 적층하는 다른 반도체 패키지를 도시하고 있다. 이하 도 6을 이용하여 본 발명의 일실시 예에 따른 리드 프레임에 반도체 칩을 적층하는 반도체 패키지에 대해 상세하게 알아보기로 한다.6 shows another semiconductor package for stacking semiconductor chips on a lead frame according to an embodiment of the present invention. Hereinafter, a semiconductor package for stacking semiconductor chips on a lead frame according to an embodiment of the present invention will be described in detail with reference to FIG.

도 6에 의하면, 반도체 패키지는 리드 프레임, 제1반도체 칩, 제2반도체 칩, 리드 프레임과 제1반도체 칩을 전기적으로 결합하는 도전성 물질, 리드 프레임과 제2 반도체 칩을 결합하는 와이어를 포함한다.According to Fig. 6, the semiconductor package includes a lead frame, a first semiconductor chip, a second semiconductor chip, a conductive material electrically coupling the lead frame and the first semiconductor chip, and a wire coupling the lead frame and the second semiconductor chip .

도 6에 의하면, 리드 프레임(600)의 상단에 제1반도체 칩(602)이 적층되며, 제1반도체 칩(602)의 상단에 제2반도체 칩(604)이 적층된다. 반도체 패키지에서 리드 프레임(600)과 제1반도체 칩(602)을 전기적으로 결합하는 도전성 물질(606)을 도포하는 과정은 다음과 같이 수행된다. 먼저, 리드 프레임(600)의 상단 또는 LOC Type의 리드 프레임의 하단에 도전성 물질(606)을 도포한 후 리드 프레임(600)과 제1반도체 칩(602)을 전기적으로 결합한다. 또는 제1반도체 칩(602)의 하단에 도전성 물질(606)을 도포한 후 리드 프레임(600)과 제1반도체 칩(602)을 전기적으로 결합할 수 있다. 또한 제2반도체 칩(604)과 리드 프레임(600)은 와이어(608)를 이용하여 전기적으로 결합한다. 이와 같이 리드 프레임(600)은 제1반도체 칩(602)과 도전성 물질(606)로 전기적으로 결합되며, 제2반도체 칩(604)과 와이어(608)로 전기적 결합된다.Referring to FIG. 6, the first semiconductor chip 602 is stacked on the top of the lead frame 600, and the second semiconductor chip 604 is stacked on the top of the first semiconductor chip 602. The process of applying the conductive material 606 that electrically couples the lead frame 600 and the first semiconductor chip 602 in the semiconductor package is performed as follows. First, a conductive material 606 is applied to the upper end of the lead frame 600 or the lower end of the LOC type lead frame, and then the lead frame 600 and the first semiconductor chip 602 are electrically coupled. Or the conductive material 606 may be applied to the lower end of the first semiconductor chip 602 and then the lead frame 600 and the first semiconductor chip 602 may be electrically coupled. The second semiconductor chip 604 and the lead frame 600 are electrically coupled to each other using a wire 608. The lead frame 600 is electrically coupled to the first semiconductor chip 602 by the conductive material 606 and electrically coupled to the second semiconductor chip 604 by the wire 608. [

부가하여 제1반도체 칩(602)과 제2반도체 칩(604)은 접착제를 이용하여 결합한다. 이와 같이 제1반도체 칩(602)과 제2반도체 칩(604)은 접착제를 이용하여 접착함으로서 안정적으로 결합할 수 있게 된다.In addition, the first semiconductor chip 602 and the second semiconductor chip 604 are bonded using an adhesive. Thus, the first semiconductor chip 602 and the second semiconductor chip 604 can be stably bonded by bonding using an adhesive.

도 7은 본 발명의 일실시 예에 따른 도 6에 도시되어 있는 반도체 패키지를 상부에서 바라본 도면이다. 도 7에 의하면, 리드 프레임과 제1반도체 칩은 도전성 물질로 전기적으로 연결되며, 리드 프레임과 제2반도체 칩은 와이어를 이용하여 전기적으로 연결된다.FIG. 7 is a top view of the semiconductor package shown in FIG. 6 according to an embodiment of the present invention. According to FIG. 7, the lead frame and the first semiconductor chip are electrically connected to each other with a conductive material, and the lead frame and the second semiconductor chip are electrically connected to each other using a wire.

상술한 바와 같이 본 발명은 도전성 물질을 이용하여 반도체 칩과 기판, 반도체 칩과 리드 프레임을 전기적으로 결합하는 것을 도시하고 있다. 도전성 물질은 Au, Cu 등 전기가 흐를 수 있는 모든 물질이 포함될 수 있다. 이와 같이 본 발명은 와이어나 범퍼가 아닌 도전성 물질을 사용함으로써 반도체 패키지의 두께를 감소시킬 수 있으며, 와이어 본딩 시 발생하는 다양한 문제점을 해결할 수 있게 된다.As described above, the present invention shows that a conductive material is used to electrically couple a semiconductor chip, a substrate, and a semiconductor chip to a lead frame. The conductive material may include all materials capable of flowing electricity such as Au and Cu. As described above, the present invention can reduce the thickness of the semiconductor package by using a conductive material other than a wire or a bumper, and solve a variety of problems caused by wire bonding.

본 발명은 도면에 도시된 일실시 예를 참고로 설명되었으나, 이는 예시적인 것에 불과하며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention .

200: 기판 202: 반도체 칩
204: 도전성 물질 500: 리드 프레임
502: 반도체 칩 504: 도전성 물질200: substrate 202: semiconductor chip
204: conductive material 500: lead frame
502: semiconductor chip 504: conductive material

Claims (7)

PCB 또는 플렉시블 PCB 기판 및
상기 기판의 상부에 적층되는 제1반도체 칩이 포함된 반도체 패키지에 있어서,
상기 기판의 패드에 도전성 물질을 도포하고, 상기 제1반도체 칩을 뒤집어 상기 기판에 접착제로 붙여, 상기 제1반도체 칩의 패드와 상기 기판의 패드가 상기 도전성 물질에 의하여 전기적으로 연결되고,
상기 제1반도체 칩 상부에 제2반도체 칩 밑면을 접착제로 접착시키고,
상기 기판의 패드와 제2반도체 칩의 패드를 와이어로 본딩한 것을 특징으로 하는 반도체 패키지.PCB or flexible PCB substrate and
And a first semiconductor chip stacked on the substrate,
A conductive material is applied to the pad of the substrate and the first semiconductor chip is turned over and adhered to the substrate with an adhesive so that the pad of the first semiconductor chip and the pad of the substrate are electrically connected by the conductive material,
Bonding the bottom surface of the second semiconductor chip to the top of the first semiconductor chip with an adhesive,
Wherein a pad of the substrate and a pad of the second semiconductor chip are bonded with a wire. 삭제delete 삭제delete 삭제delete 리드 프레임 및
상기 리드 프레임의 상부에 적층되는 제1반도체 칩이 포함된 반도체 패키지에 있어서,
상기 리드 프레임의 리드에 도전성 물질을 도포하고, 상기 제1반도체 칩을 뒤집어 패키지 기판에 접착제로 붙여, 상기 제1반도체 칩의 패드와 상기 리드 프레임의 리드가 상기 도전성 물질에 의하여 전기적으로 연결되고,
상기 제1반도체 칩 상부에 제2반도체 칩 밑면을 접착제로 접착시키고,
상기 리드 프레임의 리드와 제2반도체 칩의 패드를 와이어로 본딩한 것을 특징으로 하는 반도체 패키지.Lead frame and
And a first semiconductor chip stacked on top of the lead frame,
Wherein a conductive material is applied to a lead of the lead frame, the first semiconductor chip is turned over and adhered to the package substrate with an adhesive, the lead of the lead frame and the pad of the first semiconductor chip are electrically connected by the conductive material,
Bonding the bottom surface of the second semiconductor chip to the top of the first semiconductor chip with an adhesive,
Wherein the leads of the lead frame and the pads of the second semiconductor chip are bonded with wires. 삭제delete 삭제delete
KR1020120000152A 2012-01-02 2012-01-02 Semiconductor Package KR101453328B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040087866A (en) * 2004-03-10 2004-10-15 삼성전자주식회사 Semiconductor multi-chip package and fabrication method for the same
JP2006190834A (en) * 2005-01-06 2006-07-20 Fuji Electric Systems Co Ltd Semiconductor package and flexible circuit board
KR20070120591A (en) * 2005-04-11 2007-12-24 쓰리엠 이노베이티브 프로퍼티즈 컴파니 Connection method of conductive articles, and electric or electronic component with parts connected by the connection method
KR20110109616A (en) * 2010-03-31 2011-10-06 삼성전자주식회사 Package on package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040087866A (en) * 2004-03-10 2004-10-15 삼성전자주식회사 Semiconductor multi-chip package and fabrication method for the same
JP2006190834A (en) * 2005-01-06 2006-07-20 Fuji Electric Systems Co Ltd Semiconductor package and flexible circuit board
KR20070120591A (en) * 2005-04-11 2007-12-24 쓰리엠 이노베이티브 프로퍼티즈 컴파니 Connection method of conductive articles, and electric or electronic component with parts connected by the connection method
KR20110109616A (en) * 2010-03-31 2011-10-06 삼성전자주식회사 Package on package

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