JP2006148037A - Flip chip ball grid package structure - Google Patents

Flip chip ball grid package structure Download PDF

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Publication number
JP2006148037A
JP2006148037A JP2005029981A JP2005029981A JP2006148037A JP 2006148037 A JP2006148037 A JP 2006148037A JP 2005029981 A JP2005029981 A JP 2005029981A JP 2005029981 A JP2005029981 A JP 2005029981A JP 2006148037 A JP2006148037 A JP 2006148037A
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JP
Japan
Prior art keywords
package structure
dielectric layer
solder
elastic dielectric
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005029981A
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Japanese (ja)
Inventor
Wen-Kun Yang
楊文焜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Chip Engineering Technology Inc
Original Assignee
Advanced Chip Engineering Technology Inc
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Publication date
Priority claimed from US10/997,343 external-priority patent/US20050242427A1/en
Application filed by Advanced Chip Engineering Technology Inc filed Critical Advanced Chip Engineering Technology Inc
Publication of JP2006148037A publication Critical patent/JP2006148037A/en
Pending legal-status Critical Current

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip chip ball grid array package structure capable of preventing the phenomenon that stress is increased by the deviation of a position induced by the change of a temperature after connecting a solder ball and a printed circuit board and the solder ball is cracked. <P>SOLUTION: The package structure comprises: a base provided with a plurality of leads; a plurality of solder bumps electrically connected to the leads; a patterned first elastic dielectric layer covering the partial area of a protective layer on a flip chip; a conductive layer formed on the first elastic dielectric layer and provided with a refracted pattern generated by the pattern of the first dielectric layer, where the refracted pattern is partially attached on a protective layer and the patterned first elastic dielectric layer; and a second elastic dielectric layer covering the dielectric layer and forming a plurality of openings, where the openings are provided with the plurality of solder bumps coupled to the plurality of leads. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明はウェハのパッケージ技術に関し、特にフリップチップ・ボールグリッドアレイ（FCBGA）パッケージ構造に関する。   The present invention relates to wafer packaging technology, and more particularly to a flip chip ball grid array (FCBGA) package structure.

初期のボンディング技術はターミナル密度が極端に高くなり、且つ技術的に更に進歩した半導体結晶には適さない。このため新規なボールグリッドアレイ（EGA）が既に開発され、進歩した半導体結晶のパッケージに係るニーズを満たしている。ボールグリッドアレイパッケージの特徴は、球形のターミナルを具えているという点にあり、球形のターミナルはボンディングによるパッケージに比してピッチが狭い。しかも、係るターミナルは損傷を受けにくく、変形しにくい。また、信号送信距離が短いため操作の頻度を高めることができ、より速く効率的な操作を求めるニーズに符合する。   Early bonding techniques have extremely high terminal densities and are not suitable for further advanced semiconductor crystals. For this reason, a new ball grid array (EGA) has already been developed to meet the needs for advanced semiconductor crystal packaging. A feature of the ball grid array package is that it has a spherical terminal, and the pitch of the spherical terminal is narrower than that of the package by bonding. Moreover, such terminals are not easily damaged and are not easily deformed. In addition, since the signal transmission distance is short, the frequency of operations can be increased, which meets the needs for faster and more efficient operations.

パッケージ技術のほとんどは、ウェハ上のダイを分割して個別のダイとし、更にこれら個別のダイにパッケージとテストを行う。別途ウェハレベルパッケージ（WLP）と称するパッケージ技術は、個別のダイに分割する前にウェハ上のダイにパッケージを行う。係るウェハレベルパッケージは、例えば生産周期が短く低価格で、且つ充填物（ｕｎｄｅｒ−ｆｉｌｌ）、もしくはモールディングを必要としない等といった特徴を有する。   Most packaging technologies divide the dies on the wafer into individual dies, and then package and test these individual dies. A separate package technology, called wafer level package (WLP), packages a die on the wafer before it is divided into individual dies. Such a wafer level package has features such as a short production cycle, low price, and no need for under-fill or molding.

目下、市場に見られるパッケージの部分の構造は、図１に開示するように絶縁層１０３と、集積回路素子１００の保護層１０２とを含んでなる。絶縁層１０３の材質は厚さ約５μｍのＢＣＢ、ポリイミド等の誘電材であって、保護層１０２はポリイミドか、もしくは窒化シリコン（ＳｉＮ）等を材質とする。また、再配置する導電層（ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ ｌａｙｅｒ：ＲＤＬ）１０４を、該絶縁層１０３、集積回路素子のアルミボンディングパッド１０１とを結合させる。該導電層１０４は、厚さ約１５μｍの銅、ニッケル、金（Ｃｕ／Ｎｉ／Ａｕ）合金を材質とする。また、絶縁層１０５によって導電層１０４を被覆し、絶縁層１０５には複数の開口を形成し、それぞれの開口にソルダーボール１０６を設け、プリント回路ボードか、もしくは外部接続装置と電気的に接続する。絶縁層１０５はＢＣＢ、エポキシ化物、樹脂、もしくはポリイミド等の誘電材を材質とする。   Currently, the structure of the portion of the package found on the market comprises an insulating layer 103 and a protective layer 102 of the integrated circuit element 100 as disclosed in FIG. The insulating layer 103 is made of a dielectric material such as BCB or polyimide having a thickness of about 5 μm, and the protective layer 102 is made of polyimide or silicon nitride (SiN). In addition, a conductive layer (redistribution layer: RDL) 104 to be rearranged is bonded to the insulating layer 103 and the aluminum bonding pad 101 of the integrated circuit element. The conductive layer 104 is made of copper, nickel, gold (Cu / Ni / Au) alloy having a thickness of about 15 μm. In addition, the conductive layer 104 is covered with an insulating layer 105, and a plurality of openings are formed in the insulating layer 105. A solder ball 106 is provided in each opening, and is electrically connected to a printed circuit board or an external connection device. . The insulating layer 105 is made of a dielectric material such as BCB, epoxidized material, resin, or polyimide.

上述する従来のパッケージ構造は、最上層の材料によってソルダーボール１０６の固定を強める。但し、導電層１０４と、絶縁層１０３の結合の強度が強すぎると、かえってマイナスの効果が発生する。即ちソルダーボール１０６と、プリント回路ボードとを結合した後、温度の変化によって応力が発生すると負荷領域１０７においてソルダーボール１０６と、導電層１０４との接合部では温度の変化によって発生する位置のずれの力が大きくなり、ソルダーボール１０６とボンディングパッドとの間に亀裂が発生し、オープンサーキットが発生する。係るパッケージ構造の欠点について改善が望まれている。   The conventional package structure described above enhances the fixation of the solder balls 106 by the uppermost layer material. However, if the bonding strength between the conductive layer 104 and the insulating layer 103 is too strong, a negative effect occurs. That is, after the solder ball 106 and the printed circuit board are coupled, if a stress is generated due to a change in temperature, the position shift caused by the change in temperature at the joint between the solder ball 106 and the conductive layer 104 in the load region 107 is prevented. The force is increased, a crack is generated between the solder ball 106 and the bonding pad, and an open circuit is generated. It is desired to improve the drawbacks of such a package structure.

この発明は、ソルダーボールとプリント回路ボードとを結合した後、温度の変化によって発生する位置のずれにより応力が増大して、ソルダーボールに亀裂が発生する現象を防ぐことのできるフリップチップボールグリッドアレイパッケージ構造を提供することを課題とする。   The present invention relates to a flip chip ball grid array which can prevent a phenomenon in which a stress is increased due to a position shift caused by a change in temperature after a solder ball and a printed circuit board are combined, and a crack occurs in the solder ball. It is an object to provide a package structure.

そこで本発明者は、従来の技術に鑑み鋭意研究を重ねた結果、複数リードを具えるベースと、該リードに電気的に接続する複数のソルダーバンプと、フリップチップ上の保護層の一部領域を被覆するパターン化された第一弾性誘電層と、該第一性誘電層上に形成され、該第一電層のパターンによって発生する屈折したパターンを具え、かつ該屈折したパターンが保護層上と、該パターン化された第一性誘電層上の一部に付着する導電層と、該誘電層を被覆、かつ複数の開口を形成し、該開口に該複数のリードにカップリングする複数のソルダーバンプを設ける第二弾性誘電層と、を含んでなるパッケージ構造によって課題を解決できる点に着眼し、係る知見に基づき本発明を完成させた。
以下、この発明について具体的に説明する。 Therefore, as a result of intensive research in view of the prior art, the present inventor has obtained a base having a plurality of leads, a plurality of solder bumps electrically connected to the leads, and a partial region of the protective layer on the flip chip. A patterned first elastic dielectric layer covering the first dielectric layer and a refracted pattern formed on the first dielectric layer and generated by the pattern of the first electrical layer, the refracted pattern on the protective layer A conductive layer attached to a portion of the patterned first dielectric layer; a plurality of openings covering the dielectric layer and forming a plurality of openings, and coupling the leads to the plurality of leads; The present invention has been completed based on the knowledge that the problem can be solved by a package structure including a second elastic dielectric layer provided with solder bumps.
The present invention will be specifically described below.

請求項１に記載するパッケージ構造は、複数リードを具えるベースと、
該リードに電気的に接続する複数のソルダーバンプと、
フリップチップ上の保護層の一部領域を被覆するパターン化された第一弾性誘電層と、
該第一弾性誘電層上に形成され、該第一誘電層のパターンによって発生する屈折したパターンを具え、かつ該屈折したパターンが保護層上と、該パターン化された第一弾性誘電層上の一部に付着する導電層と、
該誘電層を被覆、かつ複数の開口を形成し、該開口に該複数のリードにカップリングする複数のソルダーバンプを設ける第二弾性誘電層と、を含む。 The package structure according to claim 1 includes a base having a plurality of leads,
A plurality of solder bumps electrically connected to the leads;
A patterned first elastic dielectric layer covering a portion of the protective layer on the flip chip; and
Formed on the first elastic dielectric layer, comprising a refracted pattern generated by the pattern of the first dielectric layer, wherein the refracted pattern is on the protective layer and on the patterned first elastic dielectric layer A conductive layer adhering to a part;
A second elastic dielectric layer covering the dielectric layer, forming a plurality of openings, and providing a plurality of solder bumps coupled to the openings in the openings.

請求項２に記載するパッケージ構造は、請求項１におけるパッケージ構造が、さらに該複数のリードに電気的にカップリングするハンダボールを具えるプリント回路ボードを含む。 According to a second aspect of the present invention, the package structure according to the first aspect further includes a printed circuit board including a solder ball that is electrically coupled to the plurality of leads.

請求項３に記載するパッケージ構造は、請求項２におけるパッケージシステムが、該複数のソルダーバンプの間に形成される充填物を更に含む。 According to a third aspect of the present invention, the package system according to the second aspect further includes a filler formed between the plurality of solder bumps.

請求項４に記載するパッケージ構造は、請求項１におけるソルダーバンプを該ベースに設けた場合、該パッケージ構造の固定領域における該導電層が、該チップのボンディングパッド上の力を直接受けることないように、該屈折した導電パターンを該パッケージ構造の緩衝物として応力を吸収するように構成する。 In the package structure according to claim 4, when the solder bump according to claim 1 is provided on the base, the conductive layer in the fixed region of the package structure is not directly subjected to the force on the bonding pad of the chip. Further, the refracted conductive pattern is configured to absorb stress as a buffer of the package structure.

請求項５に記載するパッケージ構造は、請求項１におけるパターン化された第一弾性誘電層と該導電層との間に、パターン化された第三絶縁層を形成し、該第三絶縁層の材質がＢＣＢか、シリカゲルか、エポキシ化物か、ポリイミド、もしくは樹脂から選択される。 A package structure according to claim 5 is formed by forming a patterned third insulating layer between the patterned first elastic dielectric layer according to claim 1 and the conductive layer. The material is selected from BCB, silica gel, epoxidized material, polyimide, or resin.

請求項６に記載するパッケージ構造は、請求項１における第一弾性誘電層と第二誘電層の材質が、ＢＣＢか、シリカゲルか、エポキシ化物か、ポリイミド、もしくは樹脂から選択される。 In the package structure described in claim 6, the material of the first elastic dielectric layer and the second dielectric layer in claim 1 is selected from BCB, silica gel, epoxidized material, polyimide, or resin.

請求項７に記載するパッケージ構造は、請求項１における導電層の材質が金属の合金であって、該金属の合金がスパッタリングで形成されるチタン銅（Ｔｉ／Ｃｕ）合金か、もしくは電気メッキで形成される銅ニッケル金（Ｃｕ／Ｎｉ／Ａｕ）合金であり、且つ該金属合金の厚さが１０μｍから２０μｍである。 The package structure described in claim 7 is an alloy of metal in which the conductive layer material in claim 1 is a metal alloy, and the metal alloy is a titanium copper (Ti / Cu) alloy formed by sputtering or electroplating. It is a copper nickel gold (Cu / Ni / Au) alloy formed, and the thickness of the metal alloy is 10 μm to 20 μm.

請求項８に記載するパッケージ構造は、請求項１におけるパッケージ構造がウェハレベルパッケージの構造であって、該屈折した導電層パターンが、該ボンディングパッドから該ソルダーバンプ下のソルダーパッドに延伸し、且つ線と半径方向との間に形成される夾角が４５°より大きく、該線が該チップの中心から該ソルダーバンプの中心に至る線であって、該半径方向が該ソルダーバンプの中心から該屈折した導電層パターンに至り、該ソルダーバンプから離れる方向である。 The package structure according to claim 8, wherein the package structure according to claim 1 is a wafer level package structure, and the refracted conductive layer pattern extends from the bonding pad to a solder pad under the solder bump, and A depression angle formed between the line and the radial direction is greater than 45 °, and the line extends from the center of the chip to the center of the solder bump, and the radial direction is refracted from the center of the solder bump. It is the direction which leads to the conductive layer pattern and leaves | separates from this solder bump.

請求項９に記載するパッケージ構造は、請求項８における第一弾性誘電層自身の作用と、該第一弾性誘電層、該第二弾性誘電層と、該導電層との間の比較的弱い付着力によって、該ベースの熱膨張が該チップの熱膨張より高くなった場合、該ソルダーバンプが持ち上げられて亀裂が発生しないように構成する。 The package structure described in claim 9 has a relatively weak attachment between the action of the first elastic dielectric layer itself of claim 8 and the first elastic dielectric layer, the second elastic dielectric layer, and the conductive layer. When the thermal expansion of the base becomes higher than the thermal expansion of the chip due to the attachment force, the solder bumps are lifted so that cracks do not occur.

請求項１０に記載するパッケージ構造はにおけるバンプの配置方法は、ダイ上に形成される複数のボンディングパッドと、
該ダイ上に設けられリードによって該複数のボンディングパッドに接続する複数の金属バンプと、を含むパッケージ構造における導電バンプの配置方法であって、
線と半径方向との間に形成される夾角が４５°より大きく、該線が該チップの中心から該ソルダーバンプの中心に至る線であって、該半径方向が該ソルダーバンプの中心から該屈折した導電層パターンに至り、該ソルダーバンプから離れる方向である。 The method for arranging bumps in the package structure according to claim 10 includes a plurality of bonding pads formed on a die,
A plurality of metal bumps provided on the die and connected to the plurality of bonding pads by leads; and a method of arranging conductive bumps in a package structure comprising:
A depression angle formed between the line and the radial direction is greater than 45 °, and the line extends from the center of the chip to the center of the solder bump, and the radial direction is refracted from the center of the solder bump. It is the direction which leads to the conductive layer pattern and leaves | separates from this solder bump.

請求項１１に記載するパッケージ構造における導電バンプの配置方法は、請求項１０におけるリードが、該ボンディングパッドから該金属バンプ下のパッドに延伸する。 According to the eleventh aspect of the present invention, there is provided the method for arranging conductive bumps in the package structure, wherein the lead in the tenth aspect extends from the bonding pad to a pad below the metal bump.

本発明のパッケージ構造は、ソルダーボールとプリント回路ボードとを結合した後、温度の変化によって発生する位置のずれにより応力が増大して、ソルダーボールに亀裂が発生する現象を防ぐことのでき、ソルダーボールの使用寿命を長くすることができるとともに、余剰の材料によってソルダーボールの固定を強める必要がないため、製造コストを節減し、且つ製造工程を簡易化できるという利点がある。   The package structure of the present invention can prevent a phenomenon in which after the solder ball and the printed circuit board are coupled, the stress increases due to the position shift caused by the temperature change, and the solder ball cracks. There is an advantage that the service life of the ball can be extended, and it is not necessary to strengthen the fixing of the solder ball by the surplus material, so that the manufacturing cost can be reduced and the manufacturing process can be simplified.

この発明は、フリップチップ・ボールグリッドアレイ（ＦＣＢＧＡ）パッケージ構造を提供するものであって、ソルダーボールとプリント回路ボードとを結合した後、温度の変化によって発生する位置のずれによる応力（ｅｎｆｏｒｃｉｎｇ ｓｔｒｅｓｓ）が増強し、ハンダボールの亀裂を招き、オープンサーキットが発生することを防ぐという目的を、実現した。   The present invention provides a flip chip ball grid array (FCBGA) package structure, in which a stress caused by a displacement caused by a temperature change after a solder ball and a printed circuit board are combined. The purpose of preventing the occurrence of an open circuit by causing cracks in the solder balls and increasing the resistance was realized.

この発明に開示するフリップチップ・ボールグリッドアレイパッケージの構造は、複数のソルダーバンプを具えるフリップチップソルダーボールの構造を含んでなり、ベースに複数のリードを具え、該複数のソルダーバンプと電気的にカップリングする。プリント回路ボードは複数のソルダーボールを具え、該複数のリードと電気的にカップリングする。   The structure of the flip chip ball grid array package disclosed in the present invention includes a flip chip solder ball structure including a plurality of solder bumps, and includes a plurality of leads on a base, and the plurality of solder bumps electrically To be coupled to. The printed circuit board includes a plurality of solder balls and is electrically coupled to the plurality of leads.

上述するフリップチップは集積回路であってもよい。   The flip chip described above may be an integrated circuit.

上述するフリップチップパッケージの構造は、ダイと、その上に形成されるソルダーバンプと、パターン化された第一弾性誘電層と、導電層と、及びパターン化された第二弾性導電層を含み、該パターン化された第一弾性誘電層は、集積回路の保護層上に形成される。該導電層は、該集積回路素子の保護層とボンディングパッド上に形成され、パターン化された第一弾性誘電層のパターンに基づき発生する湾曲、屈折した導電層パターンを具える。屈折した導電層パターンは、一部が保護層の上に付着し、また、一部が図案化した第一弾性誘電層上に付着する。該第二弾性誘電層は、該導電層上に形成され、該第二弾性誘電層は複数の開口を具える。該複数のソルダーバンプは該開口に形成され、複数のリードとカップリングする。   The flip chip package structure described above includes a die, a solder bump formed thereon, a patterned first elastic dielectric layer, a conductive layer, and a patterned second elastic conductive layer, The patterned first elastic dielectric layer is formed on the protective layer of the integrated circuit. The conductive layer is formed on the protective layer and the bonding pad of the integrated circuit element, and includes a curved and refracted conductive layer pattern generated based on the pattern of the patterned first elastic dielectric layer. The refracted conductive layer pattern is partly deposited on the protective layer and partly deposited on the first elastic dielectric layer that is designed. The second elastic dielectric layer is formed on the conductive layer, and the second elastic dielectric layer has a plurality of openings. The plurality of solder bumps are formed in the openings and coupled to the plurality of leads.

該ソルダーバンプをベース上に設けると、該導電層はチップのボンディングパッド上から直接力を受けない。該第一、第二弾性誘電層と導電層との間の比較的弱い付着力によって、該屈折した導電層パターンに緩衝パッドに類似する緩衝領域が発生して応力を吸収する。   When the solder bump is provided on the base, the conductive layer does not receive a direct force from the bonding pad of the chip. Due to the relatively weak adhesive force between the first and second elastic dielectric layers and the conductive layer, a buffer region similar to a buffer pad is generated in the refracted conductive layer pattern to absorb the stress.

該屈折した導電層パターンは、ボンディングパッドからソルダーバンプ下のソルダーパッドに至る。   The refracted conductive layer pattern extends from the bonding pad to the solder pad under the solder bump.

上述する第一、第二弾性誘電層自身の作用、及び第一、第二誘電層、及び導電層との間の比較的弱い付着力によって、ベースの熱膨張がチップの熱膨張より高くなった場合、該ソルダーバンプは持ち上げられるため亀裂が発生しない。   Due to the effects of the first and second elastic dielectric layers themselves and the relatively weak adhesion between the first, second dielectric layer and the conductive layer, the thermal expansion of the base is higher than the thermal expansion of the chip. In this case, since the solder bump is lifted, no crack is generated.

また、この発明はパッケージ構造の導電バンプの配置方法を提供する。係る配置方法は、ダイ上に形成される複数のボンディングパッドと、該ダイ上に形成されリードによって該複数のボンディングパッドに接続する複数の金属バンプと、を含んでなり、且つ線と半径方向との間に形成される夾角が４５°より大きく、該線は該チップの中心から該金属バンプの中心に至る線であって、該半径方向は該金属の中心から該屈折した導電層パターンに至り、該ソルダーバンプから離れる方向である。また、該リードは、該ボンディングパッドから該金属バンプ下のパッドに延伸する。
係る構成のパッケージ構造の構造と特徴を詳述するために具体的な実施例を挙げ、以下に説明する。 The present invention also provides a method for arranging conductive bumps in a package structure. The arrangement method includes a plurality of bonding pads formed on the die and a plurality of metal bumps formed on the die and connected to the plurality of bonding pads by leads, and a line and a radial direction. The included angle formed between the metal and the bump is larger than 45 °, and the line extends from the center of the chip to the center of the metal bump. The radial direction extends from the center of the metal to the refracted conductive layer pattern. , Away from the solder bump. The lead extends from the bonding pad to a pad below the metal bump.
In order to describe the structure and characteristics of the package structure having such a configuration in detail, a specific example will be given and described below.

図２にこの発明によるパッケージ構造を開示する。図面においてはパッケージ構造について説明しているが、これは本発明の実施の範囲を限定するものではない。この発明は素子２００の保護層２０２の一部領域を被覆する弾性誘電層２０３を含む。弾性誘電層２０３は、例えばＢＣＢ、シリカゲル、エポキシ化物、ポリイミド、もしくは樹脂等の誘電材質によって形成する。該パターン化した弾性誘電層２０３は、ベース層である保護層２０２を露出させる複数の開口を具える。該パターン化された弾性誘電層２０３と保護層２０２の領域に形成される荷重領域２０７は、図２に開示するように外部からの力の影響を受ける領域である。保護層２０２の材質はポリイミド、もしくは窒化珪素などの材質を含む。   FIG. 2 discloses a package structure according to the present invention. Although the package structure is described in the drawings, this does not limit the scope of the present invention. The present invention includes an elastic dielectric layer 203 that covers a partial region of the protective layer 202 of the device 200. The elastic dielectric layer 203 is formed of a dielectric material such as BCB, silica gel, epoxidized material, polyimide, or resin. The patterned elastic dielectric layer 203 includes a plurality of openings exposing the protective layer 202 as a base layer. The load region 207 formed in the region of the patterned elastic dielectric layer 203 and the protective layer 202 is a region affected by an external force as disclosed in FIG. The material of the protective layer 202 includes a material such as polyimide or silicon nitride.

再配置する導電層（ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ ｌａｙｅｒ：ＲＤＬ）２０４は、パターン化された弾性誘電層２０３上に形成され、パターン化された弾性誘電層２０３に基づき少なくとも一以上の屈折、もしくは湾曲した導電層パターンを発生させる。実施例において導電層２０４は、厚さを１０〜２０μｍ、好ましくは１５μｍのチタン銅（Ｔｉ／Ｃｕ）合金か、もしくは銅ニッケル金（Ｃｕ／Ｎｉ／Ａｕ）合金等の導電材質によって形成される。チタン銅合金はスパッタリングで形成し、銅ニッケル金合金は電気メッキで形成する。ボンディングパッド２０１は、例えばアルミ（Ａｌ）、もしくは銅（Ｃｕ）等の導電材質で形成する。 A redistribution layer (RDL) 204 is formed on the patterned elastic dielectric layer 203 and has at least one refracted or curved conductive layer pattern based on the patterned elastic dielectric layer 203. generate. In the embodiment, the conductive layer 204 is formed of a conductive material such as a titanium copper (Ti / Cu) alloy having a thickness of 10 to 20 μm, preferably 15 μm, or a copper nickel gold (Cu / Ni / Au) alloy. Titanium copper alloy is formed by sputtering, and copper nickel gold alloy is formed by electroplating. The bonding pad 201 is formed of a conductive material such as aluminum (Al) or copper (Cu).

また、パターン化された弾性誘電層２０５を導電層２０４上に形成する。パターン化された弾性誘電層２０５は複数の開口を具え、それぞれの開口にはコンタクト金属ボールを設け、該コンタクト金属ボールによってプリント回路ボード（ＰＣＢ）、もしくは外部接続装置（図示しない）に電気的に接続する。コンタクト金属ボールは、例えば図面に開示するソルダーボール２０６である。パターン化された弾性誘電層２０５はＢＣＢ、シリカゲル、エポキシ化物、ポリイミド、もしくは樹脂等の誘電材質によって形成する。 In addition, a patterned elastic dielectric layer 205 is formed on the conductive layer 204. The patterned elastic dielectric layer 205 has a plurality of openings, each of which is provided with a contact metal ball, which is electrically connected to a printed circuit board (PCB) or an external connection device (not shown). Connecting. The contact metal ball is, for example, a solder ball 206 disclosed in the drawings. The patterned elastic dielectric layer 205 is formed of a dielectric material such as BCB, silica gel, epoxidized material, polyimide, or resin.

この発明に開示するパッケージ構造のレイアウトは、上述する保護層２０２が導電層２０４を緊密に捕らえる。よって、隣接するパッケージ構造の固定領域２１０における導電層２０４は集積回路素子２００のインターコネクターのボンディングパッド２０１からの力を直接受けることがない。ソルダーボール２０６がプリント回路ボードに付着すると、熱応力が発生する恐れがある。但し、上述する通り導電層２０４が保護層２０２に直接隣り合うため、温度の影響が低減する。   In the layout of the package structure disclosed in the present invention, the protective layer 202 described above closely captures the conductive layer 204. Therefore, the conductive layer 204 in the fixing region 210 of the adjacent package structure does not directly receive the force from the bonding pad 201 of the interconnector of the integrated circuit element 200. If the solder balls 206 adhere to the printed circuit board, thermal stress may occur. However, since the conductive layer 204 is directly adjacent to the protective layer 202 as described above, the influence of temperature is reduced.

また、パッケージ構造の緩衝領域２０９において導電層２０４が、保護層２０２の上面と部分的に付着する弾性誘電層２０３上に部分的に付着する。このため導電層２０４は彎曲したパターンを形成する。導電層２０４のパターンと、彎曲した構造によって導電層２０４は熱応力を解放する緩衝物としての作用を有する。従って温度の変化によって発生する応力が分散される。導電層２０４と弾性誘電層２０３との間の結合性は好ましくない。外部からの力を受けると導電層２０４は弾性誘電層２０３の表面において軽微な剥離が発生する。但し、屈折したレイアウトの彎曲導電層パターンによって導電層の展開性が増加するため、軽微な剥離によって熱応力を吸収する。このため、上述する構造は特にボンディングパッドから離れたソルダーボール２０６使用寿命が長くなる。 Further, in the buffer region 209 of the package structure, the conductive layer 204 partially adheres on the elastic dielectric layer 203 that partially adheres to the upper surface of the protective layer 202. Therefore, the conductive layer 204 forms a curved pattern. Due to the pattern of the conductive layer 204 and the bent structure, the conductive layer 204 acts as a buffer to release thermal stress. Therefore, the stress generated by the temperature change is dispersed. The bonding between the conductive layer 204 and the elastic dielectric layer 203 is not preferable. When an external force is applied, the conductive layer 204 is slightly peeled off on the surface of the elastic dielectric layer 203. However, since the expandability of the conductive layer is increased by the bent conductive layer pattern having a refracted layout, thermal stress is absorbed by slight peeling. For this reason, especially the structure mentioned above prolongs the service life of the solder ball 206 apart from the bonding pad.

上述する導電層２０４の屈折構造は、ボンディングパッド２０１からソルダーボール２０６下のソルダーパッドに延伸する。実施例において線と半径方向（ｒａｄｉｕｓｏｒｉｅｎｔａｔｉｏｎ）との間に形成される夾角φは４５°より大きくなる。図３に開示するように該線はチップの中心ＣＩからソルダーボール２０６の中心Ｃ２に至り、半径方向はソルダーボール２０６の中心Ｃ２から屈折構造の導電層２０４に至り、ソルダーボール２０６から離れる方向である。第一と第二の弾性誘電層である弾性誘電層２０３、２０５自身の作用、及び誘電層２０３、２０５と、導電層２０４との間の付着力が弱いことによってベースの熱膨張がフリップチップの熱膨張より高くなった場合、ソルダーボール２０６は持ち上げられてクラックが発生しない。ソルダーボール２０６からリードに至り延伸する角度と、その配置する形状によって充填物質（ｕｎｄｅｒ−ｆｕｌｌｍａｔｅｒｉａｌ）を省くことができる。従って係るレイアウトによって製造コストを節減し、製造工程を簡略化することができる。   The above-described refractive structure of the conductive layer 204 extends from the bonding pad 201 to the solder pad below the solder ball 206. In an embodiment, the included angle φ formed between the line and the radial direction is greater than 45 °. As shown in FIG. 3, the line extends from the center CI of the chip to the center C 2 of the solder ball 206, and the radial direction extends from the center C 2 of the solder ball 206 to the conductive layer 204 having a refractive structure and away from the solder ball 206. is there. Due to the weak action of the elastic dielectric layers 203 and 205, which are the first and second elastic dielectric layers, and the adhesive force between the dielectric layers 203 and 205 and the conductive layer 204, the thermal expansion of the base is reduced. When it becomes higher than the thermal expansion, the solder ball 206 is lifted and no crack is generated. An under-full material can be omitted depending on the angle extending from the solder ball 206 to the lead and the shape of the lead. Therefore, the manufacturing cost can be reduced by the layout and the manufacturing process can be simplified.

図３に開示する平面図によれば、ボンディングパッドはソルダーパッドのソルダーボールＡ１３に延伸し、Ｘ／Ｙ方向（紙面）のリードは既に修正されている。ベースの熱膨張がフリップチップの熱膨張より高くなると、弾性誘電層材料の弾性と、高い展開性の作用、及び金属とシリカゲルとの間の付着力の弱さによってソルダーボールＡ１３が持ち上げられ、接合の個所にクラックが発生しない。 According to the plan view disclosed in FIG. 3, the bonding pad extends to the solder ball A13 of the solder pad, and the lead in the X / Y direction (paper surface) has already been corrected. When the thermal expansion of the base becomes higher than the thermal expansion of the flip chip, the solder ball A13 is lifted and bonded by the elasticity of the elastic dielectric layer material, the high deployability, and the weak adhesion between the metal and the silica gel. Cracks do not occur at this point.

この発明はパターン化された弾性誘電層２０８を含む。該弾性誘電層２０８は弾性誘電層２０３と導電層２０４との間に形成され、ソルダーボール下の導電層の屈折の程度（即ち上述する屈折形状の数量を増加させる）を高める。弾性誘電層２０８はＢＣＢ、シリカゲル、エポキシ化物、ポリイミド、もしくは樹脂等の誘電材質によって形成する。 The present invention includes a patterned elastic dielectric layer 208. The elastic dielectric layer 208 is formed between the elastic dielectric layer 203 and the conductive layer 204 and enhances the degree of refraction of the conductive layer under the solder ball (that is, increases the number of the refraction shapes described above). The elastic dielectric layer 208 is formed of a dielectric material such as BCB, silica gel, epoxidized material, polyimide, or resin.

図４にこの発明によるフリップチップ・ボールグリッドアレイパッケージの他の形態による構造を開示する。図面によれば図２に開示するパッケージ構造に類似し、充填物質４０４をチップ４００上の複数のソルダーバンプ４０２の間に充填する。再配置する導電層４０１は、彎曲、もしくは屈折した導電層パターンを具え、ソルダーバンプ４０２と電気的にカップリングする。弾性誘電層４０３は導電層４０１を隔離するために形成する。ベース４０５のリード４０８と、コンタクトパッド４０７は、ソルダーバンプ４０２とソルダーボール４０６とにそれぞれ電気的にカップリングする。また、ベース４０５上に形成されるソルダーボール４０６はプリント回路ボードか、もしくは外部接続装置に電気的にカップリングする。   FIG. 4 discloses a structure according to another embodiment of the flip chip ball grid array package according to the present invention. According to the drawing, similar to the package structure disclosed in FIG. 2, a filling material 404 is filled between a plurality of solder bumps 402 on the chip 400. The rearranged conductive layer 401 has a bent or refracted conductive layer pattern and is electrically coupled to the solder bump 402. The elastic dielectric layer 403 is formed to isolate the conductive layer 401. The lead 408 of the base 405 and the contact pad 407 are electrically coupled to the solder bump 402 and the solder ball 406, respectively. The solder balls 406 formed on the base 405 are electrically coupled to a printed circuit board or an external connection device.

図５に他の形態のフリップチップボールグリッドアレイパッケージ構造を開示する。図面に開示するフリップチップ・ボールグリッドアレイパッケージ構造は、図２に開示するパッケージ構造と同様に充填物質を省略する。即ち、チップ５００上の複数のソルダーバンプ５０２の間を充填する必要がない。再配置する導電層５０１は、湾曲、もしくは屈折する導電層パターンを具え、ソルダーバンプ５０２と電気的にカップリングする。ベース５０３のコンタクト５０４、５０５はソルダーバンプ５０２とソルダーボール５０６とにそれぞれ電気的に接続する。ベース５０３上に形成するソルダーボール５０６は、ソルダーボール５０６とカップリングするコンタクト５０８を介してプリント回路ボード５０７に電気的に接続する。 FIG. 5 discloses another type of flip chip ball grid array package structure. The flip chip and ball grid array package structure disclosed in the drawing omits the filling material, similar to the package structure disclosed in FIG. That is, it is not necessary to fill between the plurality of solder bumps 502 on the chip 500. The conductive layer 501 to be rearranged has a conductive layer pattern that is curved or refracted, and is electrically coupled to the solder bump 502. The contacts 504 and 505 of the base 503 are electrically connected to the solder bump 502 and the solder ball 506, respectively. Solder balls 506 formed on the base 503 are electrically connected to the printed circuit board 507 through contacts 508 coupled to the solder balls 506.

この発明によるパッケージ構造は、フリップチップボールグリッドアレイパッケージ構造であって、ソルダーボールとプリント回路ボードとを結合した後、温度の変化によって発生する位置のずれの応力が増大し、ソルダーボールに亀裂とオープンサーキットが発生する状況を改善することができる。また、余剰の材料によって、ソルダーボールの固定を増強する必要がない。 The package structure according to the present invention is a flip chip ball grid array package structure, and after joining the solder ball and the printed circuit board, the stress of misalignment caused by temperature change increases, and the solder ball is cracked. The situation where an open circuit occurs can be improved. Moreover, it is not necessary to increase the fixing of the solder balls by the surplus material.

以上はこの発明の好ましい実施例であって、この発明の実施の範囲を限定するものではない。よって、当業者のなし得る修正、もしくは変更であって、この発明の精神の下においてなされ、この発明に対して均等の効果を有するものは、いずれも本発明の特許請求の範囲に属するものとする。   The above are preferred embodiments of the present invention, and do not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made within the spirit of the present invention and have an equivalent effect on the present invention, shall belong to the scope of the claims of the present invention. To do.

従来のウェハレベルパッケージ構造説明図である。It is conventional wafer level package structure explanatory drawing. この発明によるパッケージ構造の説明図である。It is explanatory drawing of the package structure by this invention. この発明のウェハレベルパッケージ構造におけるチップの導電層パターンと、ソルダーバンプとの関係を示した平面説明図である。It is plane explanatory drawing which showed the relationship between the conductive layer pattern of the chip | tip in the wafer level package structure of this invention, and a solder bump. この発明によるフリップチップボールグリッドアレイパッケージ構造の説明図である。It is explanatory drawing of the flip chip ball grid array package structure by this invention. 他の形態によるフリップチップボールグリッドアレイパッケージ構造の説明図である。It is explanatory drawing of the flip chip ball grid array package structure by another form.

符号の説明Explanation of symbols

５００ チップ
５０１ 誘電層
５０２ ソルダーバンプ
５０３ ベース
５０４、５０５、５０８ コンタクト
５０６ ソルダーボール
５０７ プリント回路ボード 500 chip 501 dielectric layer 502 solder bump 503 base 504, 505, 508 contact 506 solder ball 507 printed circuit board

Claims (11)

複数リードを具えるベースと、
該リードに電気的に接続する複数のソルダーバンプと、
フリップチップ上の保護層の一部領域を被覆するパターン化された第一弾性誘電層と、
該第一弾性誘電層上に形成され、該第一誘電層のパターンによって発生する屈折したパターンを具え、かつ該屈折したパターンが保護層上と、該パターン化された第一弾性誘電層上の一部に付着する導電層と、
該誘電層を被覆、かつ複数の開口を形成し、該開口に該複数のリードにカップリングする複数のソルダーバンプを設ける第二弾性誘電層と、を含むことを特徴とするパッケージ構造。 A base with multiple leads,
A plurality of solder bumps electrically connected to the leads;
A patterned first elastic dielectric layer covering a portion of the protective layer on the flip chip; and
Formed on the first elastic dielectric layer, comprising a refracted pattern generated by the pattern of the first dielectric layer, the refracted pattern on the protective layer and on the patterned first elastic dielectric layer A conductive layer adhering to a part;
A package structure comprising: a second elastic dielectric layer covering the dielectric layer, forming a plurality of openings, and providing a plurality of solder bumps coupled to the leads in the openings. 前記パッケージ構造が、さらに該複数のリードに電気的にカップリングするハンダボールを具えるプリント回路ボードを含むことを特徴とする請求項１に記載のパッケージ構造。 The package structure of claim 1, wherein the package structure further comprises a printed circuit board comprising a solder ball that is electrically coupled to the plurality of leads. 前記パッケージシステムが、該複数のソルダーバンプの間に形成される充填物を更に含むことを特徴とする請求項２に記載のパッケージ構造。 The package structure of claim 2, wherein the package system further comprises a filler formed between the plurality of solder bumps. 前記ソルダーバンプを該ベースに設けた場合、該パッケージ構造の固定領域における該導電層が、該チップのボンディングパッド上の力を直接受けることないように、該屈折した導電パターンを該パッケージ構造の緩衝物として応力を吸収するように構成することを特徴とする請求項１に記載のパッケージ構造。 When the solder bump is provided on the base, the refracted conductive pattern is buffered in the package structure so that the conductive layer in the fixed region of the package structure does not directly receive the force on the bonding pad of the chip. The package structure according to claim 1, wherein the package structure is configured to absorb stress. 前記パターン化された第一弾性誘電層と該導電層との間に、パターン化された第三絶縁層を形成し、該第三絶縁層の材質がＢＣＢか、シリカゲルか、エポキシ化物か、ポリイミド、もしくは樹脂から選択されることを特徴とする請求項１に記載のパッケージ構造。 A patterned third insulating layer is formed between the patterned first elastic dielectric layer and the conductive layer, and the third insulating layer is made of BCB, silica gel, epoxidized material, polyimide, The package structure according to claim 1, wherein the package structure is selected from resin. 前記第一弾性誘電層と、第二誘電層の材質がＢＣＢか、シリカゲルか、エポキシ化物か、ポリイミド、もしくは樹脂から選択されることを特徴とする請求項１に記載のパッケージ構造。 The package structure according to claim 1, wherein the material of the first elastic dielectric layer and the second dielectric layer is selected from BCB, silica gel, epoxidized material, polyimide, or resin. 前記導電層の材質が金属の合金であって、該金属の合金がスパッタリングで形成されるチタン銅（Ｔｉ／Ｃｕ）合金か、もしくは電気メッキで形成される銅ニッケル金（Ｃｕ／Ｎｉ／Ａｕ）合金であり、且つ該金属合金の厚さが１０μｍから２０μｍであることを特徴とする請求項１に記載のパッケージ構造。 The material of the conductive layer is a metal alloy, and the metal alloy is a titanium copper (Ti / Cu) alloy formed by sputtering, or copper nickel gold (Cu / Ni / Au) formed by electroplating. 2. The package structure according to claim 1, wherein the package structure is an alloy and the thickness of the metal alloy is 10 μm to 20 μm. 前記パッケージ構造がウェハレベルパッケージの構造であって、該屈折した導電層パターンが、該ボンディングパッドから該ソルダーバンプ下のソルダーパッドに延伸し、且つ線と半径方向との間に形成される夾角が４５°より大きく、該線が該チップの中心から該ソルダーバンプの中心に至る線であって、該半径方向が該ソルダーバンプの中心から該屈折した導電層パターンに至り、該ソルダーバンプから離れる方向であることを特徴とする請求項１に記載のパッケージ構造。 The package structure is a wafer level package structure, and the refracted conductive layer pattern extends from the bonding pad to a solder pad under the solder bump, and a depression angle formed between the line and the radial direction is formed. More than 45 °, the line is a line from the center of the chip to the center of the solder bump, and the radial direction extends from the center of the solder bump to the refracted conductive layer pattern and is away from the solder bump. The package structure according to claim 1, wherein: 前記第一弾性誘電層自身の作用と、該第一弾性誘電層、該第二弾性誘電層と、該導電層との間の比較的弱い付着力によって、該ベースの熱膨張が該チップの熱膨張より高くなった場合、該ソルダーバンプが持ち上げられて亀裂が発生しないように構成することを特徴とする請求項８に記載のパッケージ構造。 Due to the action of the first elastic dielectric layer itself and the relatively weak adhesion between the first elastic dielectric layer, the second elastic dielectric layer and the conductive layer, the thermal expansion of the base causes the heat of the chip. 9. The package structure according to claim 8, wherein the solder bump is lifted to prevent a crack from occurring when it becomes higher than the expansion. ダイ上に形成される複数のボンディングパッドと、
該ダイ上に設けられリードによって該複数のボンディングパッドに接続する複数の金属バンプと、を含むパッケージ構造における導電バンプの配置方法であって、
線と半径方向との間に形成される夾角が４５°より大きく、該線が該チップの中心から該ソルダーバンプの中心に至る線であって、該半径方向が該ソルダーバンプの中心から該屈折した導電層パターンに至り、該ソルダーバンプから離れる方向であることを特徴とするパッケージ構造における導電バンプの配置方法。 A plurality of bonding pads formed on the die;
A plurality of metal bumps provided on the die and connected to the plurality of bonding pads by leads; and a method of arranging conductive bumps in a package structure comprising:
A depression angle formed between the line and the radial direction is larger than 45 °, and the line extends from the center of the chip to the center of the solder bump, and the radial direction is refracted from the center of the solder bump. A method of arranging conductive bumps in a package structure, wherein the conductive layer pattern is in a direction away from the solder bumps. 前記リードが、該ボンディングパッドから該金属バンプ下のパッドに延伸することを特徴とする請求項１０に記載のパッケージ構造における導電バンプの配置方法。 The method of claim 10, wherein the lead extends from the bonding pad to a pad below the metal bump.
JP2005029981A 2004-11-24 2005-02-07 Flip chip ball grid package structure Pending JP2006148037A (en)

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