CN101060088B - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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Publication number
CN101060088B
CN101060088B CN2007100011114A CN200710001111A CN101060088B CN 101060088 B CN101060088 B CN 101060088B CN 2007100011114 A CN2007100011114 A CN 2007100011114A CN 200710001111 A CN200710001111 A CN 200710001111A CN 101060088 B CN101060088 B CN 101060088B
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packaging
base plate
wafer
connector
dielectric layer
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CN101060088A (zh
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卢思维
赵智杰
郭祖宽
邹觉伦
张国钦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体封装结构及其制造方法，特别涉及一种半导体封装的制造方法，包括：提供一封装基板，该封装基板包括一基底材料；形成一内连线结构于该封装基板上，其中该内连线结构包括多个深插塞于该内连线结构的底部；连接至少一晶片至该封装基板的一第一表面；自相对于该第一表面的一第二表面薄化该封装基板，其中至少一部分的该基底材料被移除；以及于薄化该封装基板之后，连接多个球栅阵列球至暴露于该封装基板的该第二表面上的所述深插塞。本发明所提供的半导体封装结构及其制造方法，可有效降低作用于球栅阵列球及低介电常数介电材料的应力，也可增加封装的可靠度，并且提升封装系统的电子性能。

Description

半导体封装结构及其制造方法
技术领域
本发明是有关于一种集成电路的封装，且特别有关于一种可在集成电路封装结构中降低应力的材料及方法。
背景技术
目前集成电路的制造一般包含多个制程步骤，首先，于晶圆上形成集成电路，晶圆包含多个重复的半导体晶片(chip)，而每个晶片皆包含集成电路。接着，半导体晶片自晶圆上切割下来，并进行晶片封装制程。晶片封装具有两个目的：保护脆弱的半导体晶片以及连接内部的集成电路至外部的管脚(pin)。
于已知的封装制程中，半导体晶片通过覆晶(flip-chip)接合或焊线(wire)接合以固定在有机基板上，以覆晶技术而言，即在晶片及封装基板之间的间隙中填入底部填充胶(underfill)，以避免热应力造成在焊接凸块(solder bump)或焊接球(solder ball)中形成裂缝。
然而，已知的封装制程有缺点存在，例如，半导体硅晶片与封装基板之间的热膨胀系数(CTE)失配(mismatch)将会产生应力(stress)，而应力则产生多个重要的可靠度问题。首先，应力对于晶片中的低介电常数与极低介电常数材料的可靠度将造成冲击，再者，应力亦对于使用如无铅焊接凸块的无铅封装系统的可靠度造成冲击。由于无铅焊接凸块的污染性较低，因此已成为目前封装业界的常用材料，然而，无铅焊接凸块却太脆且容易产生裂缝，目前使用的底部填充胶不能对无铅焊接凸块提供足够的保护。
随着封装尺寸的增加更使应力的问题越严重。多个晶片(multi chips)组装在同一基板的组装方式可在元件之间连线路径变短的情况下改善电子性能，然而，较大的封装尺寸亦产生较大的应力，进而在封装制程及可靠度测试中造成封装的问题。
目前封装业界常用如有机基板的先进基底材料，其具有低成本的优点，然而，由于路径选择的限制(routing limitation)，使有机基板的性能降低，而使增加封装尺寸以改善电子性能的目的无法达成。
因此，目前亟需一种系统整合型封装(system in chippackages，SIP)的结构及制造方法，可在集成度上升的趋势下具有优势，并能同时克服已知技术的缺点。
发明内容
有鉴于此，本发明提供一种半导体封装的制造方法包括：提供一封装基板，该封装基板包括一基底材料；形成一内连线结构于该封装基板中，其中该内连线结构包括多个深插塞于该内连线结构的底部；连接至少一晶片至该封装基板的一第一表面；自相对于该第一表面的一第二表面薄化该封装基板，其中至少一部分的该基底材料被移除；以及于薄化该封装基板之后，连接多个球栅阵列球至暴露于该封装基板的该第二表面上的所述深插塞。
本发明所述的半导体封装的制造方法，其中于薄化该封装基板之前，该封装基板是一晶圆的形式。
本发明所述的半导体封装的制造方法，其中该基底材料包括硅。
本发明所述的半导体封装的制造方法，其中形成该内连线结构的步骤包括：形成一介电层于该基底材料上；形成所述深插塞于该介电层内，其中所述深插塞自该介电层的上表面延伸至该介电层的下表面；形成多个额外的介电层于该介电层上；形成多个金属化层及多个插塞于所述额外的介电层内，其中所述金属化层与所述插塞内连线且连接至所述深插塞；以及形成多个连接垫电性连接所述金属化层，其中所述连接垫与该晶片电性连接。
本发明所述的半导体封装的制造方法，其中连接该晶片至该封装基板的该第一表面的步骤包括覆晶接合。
本发明所述的半导体封装的制造方法，其中连接该晶片至该封装基板的该第一表面的步骤包括焊线接合。
本发明所述的半导体封装的制造方法，更包括沿着多个切割道于该封装基板的该第一表面切出多个沟槽，其中所述沟槽的深度小于该封装基板的厚度，且所述沟槽的深度大于该内连线结构的厚度。
本发明所述的半导体封装的制造方法，更包括连接一加强环及一散热片至该晶片。
本发明提供又一种半导体封装的制造方法包括：提供一晶圆，该晶圆包括一基底材料，其中该晶圆包括以多个切割道定义的多个封装基板；形成一内连线结构于各封装基板中，该步骤包括：形成多个深插塞于内连线结构的底部；形成多个介电层于该深插塞上；于所述介电层中形成多个金属化层及连接至所述金属化层的多个插塞，其中所述金属化层及所述插塞连接至所述深插塞；以及形成多个连接垫连接至所述金属化层中的一顶部金属化层。连接一半导体晶片至所述连接垫，所述连接垫位于各封装基板的一第一表面上；于该晶圆的一第一表面沿着所述切割道切割所述封装基板以形成多个沟槽，其中所述沟槽的深度小于所述封装基板的厚度，且所述沟槽的深度大于该内连线结构的厚度；设置一保护带于该晶圆的该第一表面；通过移除至少一部分的该基底材料并暴露所述深插塞，以自相对于该晶圆的该第一表面的一第二表面薄化该晶圆，其中所述封装基板在薄化该晶圆后互相分离；移除该保护带；以及连接多个球栅阵列球至所述封装基板的所述深插塞。
本发明所述的半导体封装的制造方法，其中薄化该晶圆的步骤是选自蚀刻、研磨及化学机械研磨的群组。
本发明所述的半导体封装的制造方法，其中形成所述深插塞的步骤包括自该基底材料的上表面形成所述深插塞至该基底材料中，其中该基底材料是选自半导体材料或介电材料。
本发明所述的半导体封装的制造方法，其中形成所述深插塞的步骤包括：形成一介电层于该基底材料上；以及形成所述深插塞，所述深插塞自该介电层的上表面延伸至该介电层的下表面。
本发明另提供一半导体封装结构，该半导体封装结构包括：一晶粒，固定于一封装基板的一第一表面上，其中该封装基板包括一内连接线结构且厚度小于约50μm，该内连线结构包括多个深插塞于其底部及至少二个导电层于多个介电层内，其中所述深插塞自与该第一表面相对的该封装基板的一第二表面暴露出来。
本发明所述的半导体封装结构，其中该封装基板大致上不具有半导体材料及有机材料。
本发明所述的半导体封装结构，其中该晶粒通过多个凸块以覆晶接合固定于该封装基板上。
本发明所述的半导体封装结构，其中该内连线结构包括双镶嵌结构或单镶嵌结构。
本发明所述的半导体封装结构，其中该内连线结构包括：一基底层；多个深插塞于该基底层中，其中所述深插塞自与该第一表面相对的该封装基底的一第二表面暴露出来；多个介电层于该基底层上；多个金属化层及多个插塞，在所述介电层中所述插塞与所述金属化层相连接，其中所述金属化层互相内连线并连接至所述深插塞；以及多个连接垫连接至所述金属化层，其中所述连接垫通过导线或凸块电性连接至该晶粒。
本发明所述的半导体封装结构，该基底层包括半导体层或介电层。
本发明提供又一种一半导体封装结构包括：一晶粒，固定于一封装基板的一第一表面，其中该晶粒包括至少一介电常数小于约3.0的低介电常数介电层；以及多个球栅阵列球，连接至该封装基板的一第二表面，该第二表面是相对于该封装基板的该第一表面，其中该封装基板的厚度小于约50μm，且该封装基板包括：一介电层；多个深插塞于该介电层中，其中所述深插塞连接至所述球栅阵列球；多个额外的介电层于该介电层上；多个的金属化层及多个插塞在所述额外的介电层中，所述插塞与所述金属化层相连接，其中所述金属化层互相内连线并连接至所述深插塞；以及多个连接垫连接至所述金属化层，其中所述连接垫通过导线或凸块电性连接至该晶粒。
本发明所提供的半导体封装结构及其制造方法，可有效降低作用于球栅阵列球及低介电常数介电材料的应力，也可增加封装的可靠度，并且提升封装系统的电子性能。
附图说明
图1是绘示一般的覆晶接合封装；
图2是绘示以封装基板的厚度为函数的球栅阵列球的标准化应力值；
图3A是绘示以封装基板的厚度为函数的低介电常数材料的标准化应力值；
图3B是绘示以封装基板的厚度为函数的凸块的标准化应力值；
图4至图8B是绘示根据本发明实施例的覆晶封装制程；
图9至图12是绘示根据本发明实施例的焊线封装制程。
具体实施方式
本发明较佳实施例的实施方式将在以下做详细的说明，本发明提供许多合适的发明概念，这些发明概念可实施于若干不同的条件下，以下说明的实施例仅作为实施本发明的示例，然其并非用以限定本发明。
本发明实施例提供一种使用极薄(ultra-thin)封装基板封装半导体晶片的方法。本发明实施例的中间制程阶段将在以下做说明，并且实施例的变化亦接着说明，在实施例中，类似的元件将以类似的标号做为标记。
封装系统中的应力与各种因素相关，例如底部填充胶(underfill)的材料或半导体晶片的厚度等。请参阅图1，其是绘示一般的覆晶(flip-chip)接合封装，半导体晶片2(在封装领域亦称为晶粒，die)至少包括一低介电常数材料4(如层间介电层ILD或金属间介电层IMD)。半导体晶片2通过凸块6以覆晶接合固定于封装基板8上，接着，封装基板8通过球栅阵列(BGA)球10装配至印刷电路板(PCB)12上。封装基板8具有厚度T。
以下将实施模拟操作以揭露封装基板8的厚度与作用于低介电常数材料4、凸块6及球栅阵列球10的应力之间的关系。请参阅图2，其是绘示以封装基板的厚度为函数的球栅阵列球的标准化应力值，其中标准化(normalization)的基数(base)是封装基板厚度为31密尔(mil)时的球栅阵列球的应力。由图中显示，当基板厚度T减少，则作用于球栅阵列球10的应力亦减少，而当基板厚度T自31mils减少至3mils，则作用于球栅阵列球10的应力可减少约52％。
请参阅图3A，其是绘示以封装基板的厚度T为函数的低介电常数材料4的标准化应力值。由图中显示，当基板厚度T自31mils减少至3mils，作用于低介电常数材料4的应力会先增加，且约在厚度T约为14mils时达到峰值(peak)。而当基板厚度T继续减少时，则应力值亦减少。而当基板厚度T自31mils减少至3mils，作用于低介电常数材料4的应力约减少至20％。因此，若要减少作用于低介电常数材料4的应力，则基板厚度T需低于某个临界(threshold)厚度，例如在此模拟操作中基板厚度约为7mils。
请参阅图3B，其是绘示以封装基板的厚度T为函数的凸块6的标准化应力值。由图中显示，当基板厚度T自31mils减少至3mils，作用于凸块6的应力约增加8％，而该增加的应力，相较于球栅阵列球及低介电常数材料所减少的应力(52％、80％)并不算多。
由上述的模拟操作可得到下列结论：厚度薄的封装基板可降低整体封装系统的应力，以及基板厚度T需小于一临界厚度以避免低介电常数材料发生应力的峰值。然而，在传统上，极薄的封装基板并不常被使用，其中一原因是由于极薄的封装材料易破碎。因此，本发明实施例将提供一种新的极薄封装基板结构及其制造方法。
图4至图8B是绘示根据本发明实施例的覆晶封装制程。请参阅图4，其是绘示本发明实施例的制程流程图，其中，步骤20表示一晶粒(或称半导体晶片)自一元件晶圆上切割下来。较佳者，该晶粒至少包含一低介电常数介电层(图5A的介电层47)，而以包含一个以上的低介电常数介电层为更佳，如为层间介电层(ILD)及金属间介电层(IMD)。该低介电常数介电层的介电常数值以小于约3.0为较佳。
如图5A所示，晶粒40通过凸块42覆晶接合至晶圆44上，该晶圆44包含多个封装基板46，每个晶粒40皆连接至作为晶圆44的一部分的封装基板46上。在一较佳实施例，凸块42为无铅的材料，或者，凸块42为铅含量小于约5％的材料，而凸块42亦可为共熔(eutectic)凸块。接着，如图4的步骤22，实施一再熔焊制程使凸块42成形。图5B是绘示图5A结构的俯视图。
请参阅图6A，其是绘示封装基板46及覆晶接合晶粒40的剖面图。封装基板46包含基底层48及内连线结构50，需注意的是，为显示内连线结构的详细构造，在此内连线结构50的比例可能较实际的比例大。较佳者，基底层48包含半导体材料，而以硅为更佳，基底层48亦可包含如为玻璃的介电材料。内连线结构50包含导电性的深插塞(via)52形成于第一介电层54中，深插塞52的排列以栅格(grid)的形式为较佳，且深插塞52的位置是对应于在后续制程中连接至深插塞52的球栅阵列球的位置为较佳。深插塞52的高度H为约1μm至约10μm为较佳，且间距为约300μm至约1000μm为较佳。内连线结构50的厚度小于约50μm为佳，而小于约10μm为更佳。
形成多个介电层56于深插塞52及第一介电层54上，介电层56的数量可部分的取决于深插塞52与连接垫62之间的导电路径，在一较佳实施例中，至少形成两层介电层56。介电层56以具有高机械强度为较佳，其较佳材料为氮化硅(SiN)、二氧化硅(SiO2)、旋涂式玻璃(spin-on glass)及其他材料。在一较佳实施例中，介电层56可通过化学气相沉积(CVD)形成，在其他实施例中，介电层56可通过旋转涂布(spin coating)或印刷(printing)形成。
形成包含多个金属线58的金属化层在各介电层56中。介电层56中形成有插塞60以内连线不同金属化层中的金属线58，插塞60及其上的金属化层可通过已知的双镶嵌制程或单镶嵌制程形成。深插塞52可通过内连线结构50与暴露于封装基板46顶部的连接垫62相连接。较佳者，深插塞52、金属线58及插塞60包含如铜、钨、铝及其组合的导电材料，而深插塞52、介电层56、插塞60及连接垫62可通过已知方法形成，在此不加以叙述。
在一较佳实施例，深插塞可形成在基底层48上的介电层中，如图6A所示。而在其他一实施例中，请参照图6B，深插塞52至少有一部分形成于基底层48中。较佳者，该形成步骤包含以蚀刻法在基底层48中形成沟槽(trench)，并于沟槽中填入如铝、银、钨、钛及其组合的导电材料。基底层48以具有低导电性为较佳，且为半导体材料为较佳，例如为硅、硅锗、其他类似材料或介电材料，后续，可利用如化学机械研磨法去除多余的材料，使留下的导电材料形成深插塞52。金属线58可直接形成于深插塞52上，或形成于基底层48上的金属化层上。还可形成插塞(图中未显示)以连接深插塞52与金属线58。
通过连接垫62与凸块42的连接，可使晶粒40固定于封装基板46上，接着，如图4的步骤24，可使用底部填充胶(underfill)64填入晶粒40、封装基板46及凸块42之间的间隙中，且底部填充胶亦可对凸块42提供结构上的支撑。
请参阅图7A，如图4中的步骤26，放置加强环(stiffenerring)66及散热片(heat spreader)68，加强环66环绕晶粒40、凸块42及底部填充胶64以进一步对晶粒40、凸块42及封装基板46提供结构上的支持。并且，还可在晶粒40上固定散热片68以提供较佳的散热效果。
请参阅图5B，如图4的步骤28，将晶圆44沿着切割道(scribeline)70切割。较佳者，如图7A所示，切割道70上只形成浅沟槽72，且封装基板46仍互相连接。请再次参照图6A、图6B及图7A，浅沟槽72的深度D可依据内连线结构50的厚度决定，D以小于约50μm为较佳，或者，D亦可小于约10μm，而D略大于内连线结构50的厚度为更佳。
在晶圆44的上表面(即与晶粒40连接的表面)形成可提供晶圆44于后续的蚀刻/研磨制程中机械支持的保护带(图中未显示)。接着，自晶圆44的下表面将晶圆薄化，如图4的步骤30。较佳者，晶圆薄化的方法包括蚀刻、研磨(polishing)及化学机械研磨(CMP)。
请再次参照图6A，通过薄化制程将基底层48完全移除。而图6B中，于深插塞52的下表面下方的基底层48被移除。由此，深插塞52自余留的封装基板46的下表面暴露出来，而余留的封装基板46只包含内连线结构50。由于内连线结构50的厚度小于约50μm，因此薄化后的封装基板46以小于约50μm为佳，且小于约10μm为更佳。
由于浅沟槽72的深度D略大于内连线结构50的厚度，因此当基底层48移除后，各封装基板46则可互相分离开来。在保护带移除后，各封装基板46分离为单独的一片。请参阅图7B，其中绘示一片单独的封装基板46。
请参照图8A及图8B，完成后的结构包含晶粒40连接至极薄封装基板46的一面，接着，该事先完成的结构装配至印刷电路板74上，如图4的步骤32及步骤34。球栅阵列(BGA)球76可事先形成于印刷电路板74上或封装基板46上。在一较佳实施例中，封装基板46通过球栅阵列球76固定于印刷电路板74上，且每一球栅阵列球直接的连接至一个深插塞52。在其他实施例中，封装基板46固定于另一封装基板上，之后，该结构被封装于一封装系统中，而该封装系统通过外部管脚连接至印刷电路板。
由于作用于凸块42的应力较少，因此本发明的实施例可适用于系统整合型封装(SIP)。请参照图8B，其是绘示封装基板46上固定有晶粒40及41。SIP制程与前述的实施例类似，因此不再重述，由于SIP的尺寸较大，故一般而言，其具有较大的应力。本发明的较佳实施例提供一种可降低应力的方法。
在其他较佳实施例中，极薄封装基板46可应用于焊线(wire-bonding)封装中，制程流程图如图9所示。步骤120、122表示晶粒140自元件晶圆切割下来，并连接至晶圆144，如图10A所示，晶粒140的后表面与晶圆144的前表面相连接，并且以导线146作为晶粒140与晶圆144之间的电性连接，如图9的步骤124。
在一较佳实施例中，晶粒140以加强环环绕(如图9的步骤126)，而在其他实施例中，则可不使用加强环，原因在于在晶片级封装(CSP)中，后续使用的封胶化合物148已可提供结构上的支持(如图9的步骤128)，其中封胶化合物148覆盖晶粒140及导线(焊线)146。参阅图10B，其是根据图10A的俯视图，晶圆144包含多个封装基板150，且每个晶粒140皆连接至一个封装基板150。
请参阅图11，其是绘示封装基板150的详细结构，封装基板150与使用于覆晶封装的封装基板类似，封装基板150包括基底层154及内连线结构152。内连线结构152包括通过内连线连接至连接垫156的深插塞158，而封装基板150的材料及制程与前述实施例中的封装基板46类似。较佳者，深插塞158的高度H及间距可与覆晶封装的深插塞相同，内连线结构152的厚度以小于约50μm为较佳，且小于约10μm为更佳。
请再次参照图10A，沿着切割道切割出沟槽160，如图9的步骤130。较佳者，沟槽160的深度D可依据内连线结构152的厚度决定，D以小于约50μm为较佳，或者，D亦可小于约10μm，而D略大于内连线结构152的厚度为更佳。
接着，晶圆144以保护带(图中未显示)保护，并进行薄化制程，如图9的步骤132。较佳者，基底层154被移除并暴露出深插塞158，由于内连线结构152的厚度小于约50μm，因此薄化后的封装基板150以小于约50μm为佳，且小于约10μm为更佳。当基底层154移除后，各封装基板150则可互相分离开来。在保护带移除后，各封装基板150分离为单独的一片。
请参照图12，其是绘示将上述完成的结构装配置至印刷电路板162，如图9的步骤134及136。球栅阵列球166可事先形成于印刷电路板162上或封装基板150上。完成的结构包含晶粒140以焊线连接至封装基板150的一面，而封装基板150的另一面则暴露出深插塞158(如图11所示)。在一较佳实施例中，封装基板150通过球栅阵列球166固定于印刷电路板162上，且每一球栅阵列球连接至一个深插塞52。在其他实施例中，封装基板150固定于另一封装基板上，之后，该结构被封装于一封装系统中，而该封装系统通过外部管脚连接至印刷电路板。在其他实施例中，有另一晶粒(图中未显示)固定于封装基板150上以形成SIP的封装结构。
球栅阵列球及低介电常数介电材料是半导体晶片制程中常用的元件，而本发明的实施例所形成的极薄封装基板，可有效降低作用于球栅阵列球及低介电常数介电材料的应力。由于作用于如无铅凸块的凸块的应力减少，使其较不易发生碎裂的情形，而封装的可靠度也因此增加。并且，由于金属化层及低介电常数材料层提供的路径选择方法具有弹性，故封装系统的电子性能亦提升。本发明的实施例可适用于SIP以降低其中的应力。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
2：半导体晶片
4：低介电常数材料
6、42：凸块
8、46、150：封装基板
10、76、166：球栅阵列(BGA)球
20、22、24、26、28、30、32、34：制程步骤
40、140：晶粒
44、144：晶圆
48、154：基底层
50、152：内连线结构
52、158：深插塞
54：第一介电层
56：介电层
58：金属线
60：插塞
62、156：连接垫
64：底部填充胶
66：加强环
68：散热片
70：切割道
72：浅沟槽
74、162：印刷电路板
120、122、124、126、128、130、132、136：制程步骤
146：导线
148：封胶化合物
160：沟槽

Claims (19)

1.一种半导体封装的制造方法，其特征在于，该半导体封装的制造方法包括：
提供一封装基板，该封装基板包括一基底材料；
形成一内连线结构于该封装基板中，其中该内连线结构包括多个深插塞于该内连线结构的底部；
连接至少一晶片至该封装基板的一第一表面；
自相对于该第一表面的一第二表面薄化该封装基板，其中至少一部分的该基底材料被移除；以及
于薄化该封装基板之后，连接多个球栅阵列球至暴露于该封装基板的该第二表面上的所述深插塞。
2.根据权利要求1所述的半导体封装的制造方法，其特征在于，于薄化该封装基板之前，该封装基板是一晶圆的形式。
3.根据权利要求1所述的半导体封装的制造方法，其特征在于，该基底材料包括硅。
4.根据权利要求1所述的半导体封装的制造方法，其特征在于，形成该内连线结构的步骤包括：
形成一介电层于该基底材料上；
形成所述深插塞于该介电层内，其中所述深插塞自该介电层的上表面延伸至该介电层的下表面；
形成多个额外的介电层于该介电层上；
形成多个金属化层及多个插塞于所述额外的介电层内，其中所述金属化层与所述插塞内连线且连接至所述深插塞；以及
形成多个连接垫电性连接所述金属化层，其中所述连接垫与该晶片电性连接。
5.根据权利要求1所述的半导体封装的制造方法，其特征在于，连接该晶片至该封装基板的该第一表面的步骤包括覆晶接合。
6.根据权利要求1所述的半导体封装的制造方法，其特征在于，连接该晶片至该封装基板的该第一表面的步骤包括焊线接合。
7.根据权利要求1所述的半导体封装的制造方法，其特征在于，更包括沿着多个切割道于该封装基板的该第一表面切出多个沟槽，其中所述沟槽的深度小于该封装基板的厚度，且所述沟槽的深度大于该内连线结构的厚度。
8.根据权利要求1所述的半导体封装的制造方法，其特征在于，更包括连接一加强环及一散热片至该晶片。
9.一种半导体封装的制造方法，其特征在于，该半导体封装的制造方法包括：
提供一晶圆，该晶圆包括一基底材料，其中该晶圆包括以多个切割道定义的多个封装基板；
形成一内连线结构于各封装基板中，该步骤包括：
形成多个深插塞于该内连线结构的底部；
形成多个介电层于该深插塞上；
于所述介电层中形成多个金属化层及连接至所述金属化层的多个插塞，其中所述金属化层及所述插塞连接至所述深插塞；以及
形成多个连接垫连接至所述金属化层中的一顶部金属化层；
连接一半导体晶片至所述连接垫，所述连接垫位于各封装基板的一第一表面上；
于该晶圆的一第一表面沿着所述切割道切割所述封装基板以形成多个沟槽，其中所述沟槽的深度小于所述封装基板的厚度，且所述沟槽的深度大于该内连线结构的厚度；
设置一保护带于该晶圆的该第一表面；
通过移除至少一部分的该基底材料并暴露所述深插塞，以自相对于该晶圆的该第一表面的一第二表面薄化该晶圆，其中所述封装基板在薄化该晶圆后互相分离；
移除该保护带；以及
连接多个球栅阵列球至所述封装基板的所述深插塞。
10.根据权利要求9所述的半导体封装的制造方法，其特征在于，薄化该晶圆的步骤是选自蚀刻、研磨及化学机械研磨的群组。
11.根据权利要求9所述的半导体封装的制造方法，其特征在于，形成所述深插塞的步骤包括自该基底材料的上表面形成所述深插塞至该基底材料中，其中该基底材料是选自半导体材料或介电材料。
12.根据权利要求9所述的半导体封装的制造方法，其特征在于，形成所述深插塞的步骤包括：
形成一介电层于该基底材料上；以及
形成所述深插塞，所述深插塞自该介电层的上表面延伸至该介电层的下表面。
13.一半导体封装结构，其特征在于，该半导体封装结构包括：
一晶粒，固定于一封装基板的一第一表面上，其中该封装基板包括一内连线结构且厚度小于50μm，该内连线结构包括多个深插塞于其底部及至少二个导电层于多个介电层内，其中所述深插塞自与该第一表面相对的该封装基板的一第二表面暴露出来。
14.根据权利要求13所述的半导体封装结构，其特征在于，该封装基板不具有半导体材料及有机材料。
15.根据权利要求13所述的半导体封装结构，其特征在于，该晶粒通过多个凸块以覆晶接合固定于该封装基板上。
16.根据权利要求13所述的半导体封装结构，其特征在于，该内连线结构包括双镶嵌结构或单镶嵌结构。
17.根据权利要求13所述的半导体封装结构，其特征在于，该内连线结构包括：
一基底层；
多个深插塞于该基底层中，其中所述深插塞自与该第一表面相对的该封装基底的一第二表面暴露出来；
多个介电层于该基底层上；
多个金属化层及多个插塞，在所述介电层中所述插塞与所述金属化层相连接，其中所述金属化层互相内连线并连接至所述深插塞；以及
多个连接垫连接至所述金属化层，其中所述连接垫通过导线或凸块电性连接至该晶粒。
18.根据权利要求17所述的半导体封装结构，其特征在于，该基底层包括半导体层或介电层。
19.一半导体封装结构，其特征在于，该半导体封装结构包括：
一晶粒，固定于一封装基板的一第一表面，其中该晶粒包括至少一介电常数小于3.0的低介电常数介电层；以及
多个球栅阵列球，连接至该封装基板的一第二表面，该第二表面是相对于该封装基板的该第一表面，其中该封装基板的厚度小于50μm，且该封装基板包括：
一介电层；
多个深插塞于该介电层中，其中所述深插塞连接至所述球栅阵列球；
多个额外的介电层于该介电层上；
多个的金属化层及多个插塞在所述额外的介电层中，所述插塞与所述金属化层相连接，其中所述金属化层互相内连线并连接至所述深插塞；以及
多个连接垫连接至所述金属化层，其中所述连接垫通过导线或凸块电性连接至该晶粒。
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