CN111223819A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN111223819A
CN111223819A CN201910176785.0A CN201910176785A CN111223819A CN 111223819 A CN111223819 A CN 111223819A CN 201910176785 A CN201910176785 A CN 201910176785A CN 111223819 A CN111223819 A CN 111223819A
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Prior art keywords
dielectric layer
die
semiconductor structure
substrate
metal strip
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CN201910176785.0A
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施信益
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Nanya Technology Corp
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Nanya Technology Corp
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Publication of CN111223819A publication Critical patent/CN111223819A/zh
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Abstract

本公开提供一种半导体结构及其制造方法。该半导体结构包括一基底、一晶粒、一封胶、一介电层、一导电通孔以及一金属条带。该晶粒设置在该基底的上方。该封胶围绕该晶粒。该介电层设置在基底的上方并且围绕该晶粒和该封胶。该导电通孔延伸穿过该介电层。该金属条带延伸穿过该介电层并沿该介电层延伸，以至少部分地围绕该晶粒。

Description

半导体结构及其制造方法
本申请主张2018/11/23申请的美国临时申请第62/770,928号及2019/1/10申请的美国正式申请第16/244,870号的优先权及权益，该美国临时申请及该美国正式申请的内容以全文引用的方式并入本文中。
技术领域
本公开关于一种半导体结构，特别是关于一种封装堆叠(package on package，PoP)的结构及其制造方法。在封装堆叠结构中，一个封装体设置在另一个包括金属条带的封装体的上方。此外，半导体结构的制造方法包括去除封装体的介电层的一部分以形成沟槽，并且将导电材料设置到沟槽中以形成金属条带。
背景技术
半导体元件对于许多现代的应用很重要。随着电子技术的进步，半导体元件的尺寸愈来愈小，同时元件具有更多的集成电路和提供更强大的功能。由于半导体元件的小型化，封装堆叠(package on package，PoP)现在被广泛应用做为一种半导体元件的制造方法。在这种封装结构的生产中，执行了许多的制造步骤。
使用封装堆叠来制造半导体元件变得更加地复杂。半导体元件由与许多集成元件组合，包括具有不同热性能的各种材料。由于组合许多具有不同材料的元件，因此半导体元件和制造的操作变得更加复杂。因此，对于半导体元件的结构和工艺的改进在持续进行着。
上文的“先前技术(现有技术)”说明仅是提供背景技术，并未承认上文的“先前技术”说明揭示本公开之目的，不构成本公开的先前技术，且上文的“先前技术”的任何说明均不应作为本申请的任一部分。
发明内容
本公开提供一种半导体结构，包括一基底、一晶粒、一封胶、一介电层、一导电通孔以及一金属条带。该晶粒设置在该基底的上方。该封胶围绕该晶粒。该介电层设置在基底的上方并且围绕该晶粒和该封胶。该导电通孔延伸穿过该介电层。该金属条带延伸穿过该介电层并沿该介电层延伸，以至少部分地围绕该晶粒。
在一些实施例中，该晶粒被该金属条带包围。
在一些实施例中，该金属条带的一表面通过该介电层暴露。
在一些实施例中，该封胶被设置在该晶粒和该介电层之间。
在一些实施例中，该金属条带被设置在该半导体结构的一角落或沿该导体结构的一边缘设置。
在一些实施例中，该金属条带被设置在该导电通孔的上方。
在一些实施例中，该导电通孔被设置在该金属条带和该晶粒之间。
在一些实施例中，该金属条带被设置在该晶粒和该导电通孔之间。
在一些实施例中，该导电通孔的一顶部横截面实质上小于该金属条带一顶部横截面。
在一些实施例中，该导电通孔的一顶部横截面具一有圆形形状，该金属条带的一顶部横截面具有一矩形形状。
在一些实施例中，该半导体结构还包括设置在该基底下方的一第一连接器。
在一些实施例中，该半导体结构还包括在该晶粒和该介电层上方的一封装体，该封装体通过一第二连接器接合。
在一些实施例中，该第二连接器被设置在该导电通孔的上方并且电连接到该导电通孔。
本公开另提供一种半导体结构的制造方法，包括：提供一载体；设置一介电层在该载体的上方；去除该介电层的一第一部分，形成延伸穿过该介电层的一开口；去除该介电层的一第二部分，形成延伸穿过该介电层并且沿该介电层延伸的一沟槽；设置一导电材料在该开口和沟槽内，分别形成一导电通孔和一金属条带；去除该介电层的一第三部分；将该介电层从该载体分开；将该介电层设置在一基底的上方；设置一晶粒在该基底的上方；以及形成一封胶以围绕该晶粒。
在一些实施例中，该沟槽沿该介电层延伸以至少部分地围绕该晶粒。
在一些实施例中，去除该介电层的该第一部分和去除该介电层的该第二部分是同时执行。
在一些实施例中，去除该介电层的该第三部分是在从该载体分开该介电层之前或是在该基底的上方设置该介电层之后执行。
在一些实施例中，在该基底的上方设置该介电层包括通过一连接器将该介电层接合到该基底。
在一些实施例中，通过电镀、物理气相沉积(PVD)、化学气相沉积(CVD)或模板电镀来设置该导电材料。
在一些实施例中，该制造方法还包括通过一连接器将一封装体接合在该晶粒和该介电层的上方。
上文已相当广泛地概述本公开的技术特征及优点，由此使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求书目的之其它技术特征及优点将描述于下文。本公开所属技术领域中的一般技术人员应了解，可相当容易地利用下文揭示的概念与特定实施例以作为修改或设计其它结构或工艺而实现与本公开相同之目的。本公开所属技术领域中的一般技术人员亦应了解，这类等效建构无法脱离随附的权利要求书所界定的本公开的精神和范围。
附图说明
参阅实施方式与权利要求书合并考量附图时，可得以更全面了解本申请的揭示内容，附图中相同的元件符号(附图标记)指代相同的元件。
图1是俯视图，例示本公开一实施例的半导体结构。
图2是剖面图，例示图1的半导体结构沿A-A'剖面线的结构。
图3是俯视图，例示本公开另一实施例的半导体结构。
图4是剖面图，例示本公开一些实施例的封装堆叠结构。
图5是流程图，例示本公开一些实施例的半导体结构的制造方法。
图6至图17是示意图，例示图5的半导体结构的制造方法。
【附图标记说明】
100 半导体结构
101 基底
101a 第一表面
101b 第二表面
101c 第一导电垫
101d 第一连接器
102 晶粒
102a 晶粒接垫
103 封胶
104 介电层
104a 第一层
104b 第二层
104c 第三层
104d 开口
104e 沟漕
104f 孔洞
105 导电通孔
105a 通孔部分
105b 接垫部分
106 金属长条
107 载体
108 导电材料
200 半导体结构
201 封装基底
202 第二导电垫
203 第二连接器
300 方法
301 步骤
302 步骤
303 步骤
304 步骤
305 步骤
306 步骤
307 步骤
308 步骤
309 步骤
310 步骤
具体实施方式
本公开的以下说明伴随纳入且组成说明书的一部分的附图，说明本公开实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以构成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而也可为相同实施例。
本公开关于一种半导体结构，该半导体结构包括至少部分地围绕一晶粒的一金属条带。此外，本公开关于一种半导体结构的制造方法，包括去除一部分的介电层以形成一沟槽，以及将导电材料设置到该沟槽中以形成金属条带。为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制于该领域的技术人员已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的较佳实施例详述如下。然而，除了实施方式之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于实施方式的内容，而是由权利要求书定义。
一个半导体结构是通过若干工艺来制造。将晶粒或晶片设置在基底上以成为第一封装体，然后将第二封装体接合在该第一封装体上以形成一种封装堆叠(package onpackage，PoP)结构。但是，持续进步的技术正在使这种包装的尺寸变得更小和更薄。这种小而薄的封装体容易遭受翘曲或弯曲，因此第一个封装体上的一些连接器可能无法接触到第二个封装体上相对应的连接器。可能发生冷接合缺陷并且导致第一封装体和第二封装体之间的电连接失效。因此降低了半导体结构的可靠性。
本公开提供一种半导体结构。该半导体结构包括：一基底；一介电层，设置在基底的上方；一金属条带，延伸穿过该介电层并沿着该介电层延伸。金属条带可以增强半导体结构，因此防止或减少半导体结构的翘曲。因此，可以提高半导体结构的可靠性。
此外，减少或防止半导体结构的翘曲可以改善半导体结构与另一封装体之间的接合。可以减少或防止半导体结构与另一封装体之间的冷接合缺陷。因此，也改善了半导体结构与另一封装体之间的电连接。
图1是俯视图，例示本公开一实施例的半导体结构100；图2是剖面图，例示图1的半导体结构100沿A-A'剖面线的结构。在一些实施例中，半导体结构100包括基底100、晶粒102、封胶103、介电层104、导电通孔105以及金属条带106。
在一些实施例中，半导体结构100是一半导体封装或该半导体封装的一部分。在一些实施例中，半导体结构100是一覆晶封装(flip chip package)。
在一些实施例中，基底101是一半导体基底。在一些实施例中，基底101是一晶片或一中介层。在一些实施例中，基底101包括半导体材料，例如硅、锗、镓、砷、或其组合。在一些实施例中，基底101包括例如陶瓷、玻璃等材料。在一些实施例中，基底101是一硅基底。在一些实施例中，基底101是一封装基底。在一些实施例中，基底101具有四边形、矩形、正方形、多边形或任何其他合适的形状。
在一些实施例中，在基底101的上方被制造为具有预定功能的电路。在一些实施例中，基底101包括若干导电迹线和设置在基底101内的若干电子元件，例如晶体管、二极管等。在一些实施例中，基底101包括第一表面101a和与第一表面101a相对的一第二表面101b。
在一些实施例中，一第一导电垫101c被设置在基底101的上方或在基底101内。在一些实施例中，第一导电垫101c被设置在基底101的第一表面101a的上方。在一些实施例中，第一导电垫101c电连接到基底101内的电路或电子元件。在一些实施例中，第一导电垫101c电连接到基底101外部的电路，因此基底101中的电路可以通过第一导电垫101c电连接到基底101外部的电路。
在一些实施例中，第一导电垫101c被配置以接收一导电结构。在一些实施例中，第一导电垫101c是一晶粒或一接合垫。在一些实施例中，第一导电垫101c包括金、银、铜、镍、钨、铝、钯或其合金。
在一些实施例中，第一连接器101d被设置在基底101的上方。在一些实施例中，第一连接器101d设置在基底101的第二表面101b的上方。在一些实施例中，第一连接器101d设置在基底101的下方。在一些实施例中，第一连接器101d包括导电材料，例如锡、铜、镍或金。在一些实施例中，第一连接器101d是锡球、球栅阵列(ball grid array，BGA)球、可控塌陷晶片连接(controlled collapse chip connection，C4)凸块，微凸块、支柱等。在一些实施例中，第一连接器101d具有球形、半球形或圆柱形状。
在一些实施例中，晶粒102设置在基底101的上方。在一些实施例中，晶粒102设置在基底101的第一表面101a的上方。在一些实施例中，晶粒102电连接到基底101。在一些实施例中，翻转晶粒102，并且晶粒接垫102a接合到基底101的第一导电垫101c，使晶粒102电连接到基底101。
在一些实施例中，晶粒102被制造为在晶粒102内具有预定功能的电路。晶粒102包括各种元件，例如晶体管、电容器、电阻器、二极管等。在一些实施例中，晶粒102是一逻辑元件晶粒等。在一些实施例中，通过机械或电射光刀片从半导体晶片分割晶粒102。尽管图1和图2示出半导体结构100仅包括一个晶粒102，但是应该理解，并不旨在限制半导体结构100中的晶粒数量，半导体结构100可以包括多个晶粒102。
在一些实施例中，晶粒102被封胶103包围。晶粒102由封胶103封装。在一些实施例中，封胶103设置在基底101的上方。在一些实施例中，晶粒102的所有侧壁都被封胶103覆盖。在一些实施例中，封胶103的一表面通过介电层104暴露。在一些实施例中，封胶103可以是一单个层膜或一复合叠层。在一些实施例中，封胶103包括各种材料，例如模制化合物、液态模制化合物、模制底部填充物、环氧树脂、树脂等。在一些实施例中，封胶103具有高导热率、低吸湿率和高弯曲强度。
在一些实施例中，介电层104设置在基底101的上方。在一些实施例中，介电层104设置在基底101的第一表面101a的上方。在一些实施例中，介电层104围绕晶粒102和封胶103。封胶103设置在晶粒102和介电层104之间。
在一些实施例中，介电层104包括彼此堆叠的若干层(104a，104b，104c)。在一些实施例中，介电层104包括介电质或聚合材料。在一些实施例中，介电层104包括聚合物、聚酰亚胺(PI)、氧化硅、氮化硅等。在一些实施例中，介电层104包括第一层104a、第一层104a上方的第二层104b、以及第一层104a和第二层104b上方的第三层104c。在一些实施例中，第一层104a、第二层104b和第三层104c都包括相同的材料，或者包括不同的材料。
在一些实施例中，导电通孔105延伸穿过介电层104。在一些实施例中，导电通孔105延伸穿过介电层104的第一层104a、第二层104b和第三层104c中的至少一个。在一些实施例中，导电通孔105包括导电材料，例如铜、银、金、铝等。在一些实施例中，导电通孔105具有圆柱形状。在一些实施例中，导电通孔105的一顶部横截面具有圆形、矩形或多边形状。在一些实施例中，半导体结构100包括以规则阵列布置的若干导电通孔105。
在一些实施例中，导电通孔105包括通孔部分105a和接垫部分部分105b。通孔部分105a延伸穿过介电层104的第一层104a、第二层104b和第三层104c中的至少一个。在一些实施例中，通孔部分105a在介电层104内垂直延伸。在一些实施例中，接垫部分105a设置在通孔部分105a的上方或下方，并且在介电层104的第一层104a、第二层104b和第三层104c中的至少一个的上方延伸。在一些实施例中，接垫部分105b通过介电层104暴露。
在一些实施例中，金属条带106延伸穿过并且沿介电层104延伸以至少部分地围绕晶粒102。在一些实施例中，金属条带106在介电层104内垂直延伸。在一些实施例中，金属条带106垂直延伸穿过介电层104的第一层104a、第二层104b和第三层104c中的至少一个。在一些实施例中，金属条带106从基底101的第一表面101a延伸到第一层104a、第二层104b或第三层104c。在一些实施例中，金属条带106从第二层104b延伸到第三层104c。
在一些实施例中，金属条带106沿介电层104并且沿半导体结构100的一边缘延伸。在一些实施例中，金属条带106平行于基底101的第一表面101a延伸。在一些实施例中，金属条带106在介电层104内水平延伸。在一些实施例中，金属条带106设置在导电通孔105的上方。在一些实施例中，金属条带106设置在导电通孔105的上方并且与导电通孔105垂直对齐。
在一些实施例中，导电通孔105设置在金属条106和晶粒102之间。在一些实施例中，金属条带106至少部分地围绕导电通孔105、晶粒102和封胶103。在一些实施例中，金属条带106设置在晶粒102和导电通孔105之间。在一些实施例中，金属条带106至少部分地围绕晶粒102和封胶103。在一些实施例中，晶粒102和封胶103被金属条带106包围。
在一些实施例中，金属条带106的一顶部横截面具有矩形形状。在一些实施例中，金属条带106被配置为一框架以至少部分地围绕晶粒102。在一些实施例中，金属条带106被配置为一封闭框架。在一些实施例中，导电通孔105的一顶部横截面实质上小于金属条带106的一顶部横截面。在一些实施例中，金属条带106的一表面通过介电层104暴露。在一些实施例中，金属条带106连接到一电接地。
图3是俯视图，例示本公开另一实施例的半导体结构100'，具有另一种配置的金属条带106。在一些实施例中，金属条106包括若干区段，并且每一区段至少部分地围绕晶粒102或沿着半导体结构100的边缘延伸。在一些实施例中，金属条带106的区段设置在半导体结构100的角落。在一些实施例中，金属条带106的区段设置在靠近晶粒102的角落。在一些实施例中，金属条带106的区段靠近晶粒102并且沿晶粒102的一边缘延伸设置。
在一些实施例中，金属条带106的一区段的一顶部横截面具有矩形或L形形状。在一些实施例中，导电通路105的一顶部横截面实质上小于金属条106的该区段的一顶部横截面。
图4是剖面图，例示本公开一些实施例的封装堆叠结构200。在一些实施例中，封装堆叠结构200包括在图1至图3中的任何一个半导体结构100。
在一些实施例中，封装堆叠结构200包括设置在半导体结构100上并且电连接到半导体结构100的封装基底201。在一些实施例中，封装基底201被翻转并且接合到半导体结构100。在一些实施例中，封装基底201是晶片或中介层。在一些实施例中，封装基底201包括半导体材料，例如硅、锗、镓、砷、或其组合。在一些实施例中，封装基底201包括例如陶瓷、玻璃等材料。在一些实施例中，封装基底201具有四边形、矩形、正方形、多边形或任何其他合适的形状。
在一些实施例中，在封装基底201的上方被制造为具有预定功能的电路。在一些实施例中，封装基底201包括若干导电迹线和若干电子元件，例如设置在封装基底201内的晶体管、二极管等。
在一些实施例中，第二导电垫202设置在封装基底201的上方或在封装基底201内。在一些实施例中，第二导电垫202电连接到封装基底201内的电路或电子元件。在一些实施例中，第二导电垫202电连接到封装基底201外部的电路，因此封装基底201中的电路可以通过第二导电垫202电连接到封装基底201外部的电路。
在一些实施例中，第二导电垫202被配置以接收一导电结构。在一些实施例中，第二导电垫202是一晶粒或一接合垫。在一些实施例中，第二导电垫202包括金、银、铜、镍、钨、铝、钯或其合金。
在一些实施例中，第二连接器203被设置在封装基底201的上方。在一些实施例中，第二连接器203包括导电材料，例如锡、铜，镍或金。在一些实施例中，第一连接器101d是锡球、球栅阵列(ball grid array，BGA)球、可控塌陷晶片连接(controlled collapse chipconnection，C4)凸块，微凸块、支柱等。在一些实施例中，第二连接器203具有球形、半球形或圆柱形状。
在一些实施例中，封装基底201通过第二连接器203和介电层104上方的晶粒102接合。在一些实施例中，第二连接器203被设置在导电通孔105的上方并且电连接到导电通孔105。在一些实施例中，第二连接器203结合到导电通孔105的接垫部分部分105b。在一些实施例中，金属条带106与封装基底201、第二导电垫202和第二连接器203电隔离。
图5是流程图，例示本公开一些实施例的半导体结构(100，200)的制造方法300；图6至图17是示意图，例示图5的半导体结构的制造方法300。在一些实施例中，半导体结构(100，200)可以通过图5的制造方法300予以制造。制造方法300包括数个操作，并且描述和说明不是为了对操作顺序做限制。制造方法300包括数个步骤(301、302、303、304、305、306、307、308、309和310)。
在制造步骤301中，提供或接收载体107，如图6所示。在一些实施例中，载体107由半导体材料制成。在一些实施例中，载体107包括硅、锗、镓、砷或其组合。在一些实施例中，载体107由玻璃等制成。在一些实施例中，载体107具有四边形、矩形、正方形、多边形或任何其他合适的形状。
在步骤302中，设置介电层104在载体107的上方，如图7所示。在一些实施例中，通过旋涂涂覆、化学气相沉积(CVD)或任何其他合适的操作来设置介电层104。在一些实施例中，介电层104的第一层104a设置在载体107的上方。
在步骤303中，去除介电层104的第一部分以形成开口104d，如图8所示。在一些实施例中，通过光学光刻、蚀刻、激光钻孔或任何其他合适的操作来去除介电层104的第一部分。在一些实施例中，开口104d延伸穿过介电层104的第一层104a。在一些实施例中，开口104d的一顶部横截面具有圆形形状。
在步骤304中，去除介电层104的第二部分以形成沟槽104e，如图8所示。在一些实施例中，通过光学光刻、蚀刻、激光钻孔或任何其他合适的操作来去除介电层104的第二部分。在一些实施例中，沟槽104e延伸穿过并且沿着介电层104的第一层104a延伸。在一些实施例中，沟槽104e的顶部横截面具有矩形形状。
在一些实施例中，去除介电层104的第一部分(步骤303)和去除介电质104的第二部分(步骤304)是同时地执行或分开地执行。在一些实施例中，步骤303在步骤304之前或之后执行。
在步骤305中，设置导电材料108在开口104d和沟槽104e内，以分别形成导电通孔105和金属条带106，如图9所示。在一些实施例中，通过镀、电镀、溅镀，物理气相沉积(PVD)、化学气相沉积(CVD)、模板电镀或任何其他合适的操作来设置导电材料108。在一些实施例中，将导电材料108设置到开口104d内以及将导电材料108设置到沟槽104e内为同时执行或分开执行。
在一些实施例中，导电材料108设置在开口104d内以形成导电通孔105的通孔部分105a。在一些实施例中，导电材料108设置在介电层104的上方以形成导电通孔105的接垫部分105b。
在一些实施例中，导电材料108的设置是在去除介电层104的第一部分(步骤303)之后，但在去除介电层104的第二部分(步骤304)之前执行。换句话说，导电通孔105在步骤304之前形成。在一些实施例中，导电材料108的设置是在去除介电层104的第二一部分(步骤304)之后，但在去除介电层104的第一部分(步骤303)之前执行。换句话说，金属条带106在步骤303之前形成。
在一些实施例中，重复执行步骤302、步骤303、步骤304和步骤305，以形成如图10所示的中间结构。
在一些实施例中，在步骤305之后，介电层104的第二层104b设置在介电层104的第一层104a的上方、去除介电层104的第一部分或第二部分、以及导电材料108设置在开口104d内以形成导电通孔105或导电材料108设置在沟槽104e内以形成金属条带106。
在一些实施例中，在设置介电层104的第二层104b和在第二层104b内形成导电通孔105或金属条带106之后，介电层104的第三层104c设置在介电层104的第二层104b的上方，然后去除介电层104的第一部分或第二部分，然后将导电材料108设置在开口104d内以形成导电通孔105或将导电材料108设置在沟槽104e内以形成金属条106。
在步骤306中，去除介电层104的第三部分，如图11所示。在一些实施例中，通过光学光刻、蚀刻、激光钻孔或任何其他合适的操作来去除介电层104的第三部分。在一些实施例中，在去除介电层104的第三部分之后形成孔洞104f。在一些实施例中，孔洞104f延伸穿过介电层104。在一些实施例中，孔洞104f延伸穿过介电层104的第一层104a、第二层104b和第三层104c。在一些实施例中，介电层104、导电通孔105和金属条106如以上所述的配置安排或是如图1至图4中所示的配置。
在步骤307中，分开介电层104与载体107，如图12所示。载体107通过任何合适的剥离操作来分开。在一些实施例中，例如接垫、凸块、柱等的连接器设置在导电通孔105的端点的上方或金属条带106的端部的上方。连接器被配置为与一导电结构结合。
在步骤308中，设置介电层104(与载体107分开)在基底101的上方，如图13和14所示。在一些实施例中，介电层104接合在基底101的上方。在一些实施例中，介电层104与基底101垂直对齐。在一些实施例中，导电通孔105和金属条带106设置在基底101的第一导电垫101c的上方。在一些实施例中，基底101如以上所述的配置安排或是如图1至图4中所示的配置。
在一些实施例中，导电通孔105通过第一导电垫101c电连接到基底101。在一些实施例中，金属条带106不与基底101电连接。在一些实施例中，诸如接垫、凸块、柱等的连接器将介电层104结合到基底101。连接器设置在导电通孔105和第一导电垫101c之间。连接器接合到第一导电垫101c。
在一些实施例中，去除介电层104的第三部分(步骤306)是在将介电层104从载体分开(步骤307)和在基底101的上方设置介电层104(步骤308)之后执行。如图13所示，将介电层104与载体107分开，然后设置在基底101的上方。在基底101的上方设置介电层104之后，去除介电层104的第三部分以形成孔洞104f，如图14所示。
在步骤309中，设置晶粒102在基底101的上方，如图15所示。将晶粒102翻转并且黏合到基底的上方。在一些实施例中，晶粒102的晶粒接垫102a接合到基底101的第一导电垫101c。晶粒102电连接到基底101。在一些实施例中，金属条带106至少部分地围绕晶粒102。在一些实施例中，沟槽104e至少部分地围绕晶粒102。在一些实施例中，晶粒102如以上所述的配置安排或是如图1至图4中所示的配置。
在步骤310中，形成封胶103以围绕晶粒102，如图16所示。在一些实施方案中，封胶103通过传递成型、射出成型或任何其它合适的操作形成。在一些实施例中，封胶103覆盖晶粒102并且被介电层104围绕。在一些实施例中，封胶103如以上所述的配置安排或是如图1至图4中所示的配置。在一些实施例中，形成半导体结构100。
在一些实施例中，封装体在晶粒102和介电层104的上方接合，如图17所示。在一些实施例中，封装基底201通过第二连接器203接合到介电层104和晶粒102。在一些实施例中，设置在封装基底201和导电通孔105上方的第二导电垫202通过第二连接器203电连接。第二连接器203设置在第二导电垫202和导电通孔105之间。
在一些实施例中，封装基底201通过第二导电垫202、第二连接器203和导电通孔105电连接到基底101。在一些实施例中，封装基底201、第二导电垫202和第二连接器203如以上所述的配置安排或是如图1至图4中所示的配置。在一些实施例中，形成半导体结构200。
虽然已详述本公开及其优点，然而应理解的是可进行各种变化、取代与替代而不脱离权利要求书所定义的本公开的精神与范围。例如，可用不同的方法实施上述许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本申请的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该领域的技术人员可从本公开的揭示内容理解的是，可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，此等工艺、机械、制造、物质组成物、手段、方法、或步骤包含于本申请的专利范围内。

Claims (20)

1.一种半导体结构，包括：
一基底；
一晶粒，设置在该基底的上方；
一封胶，围绕该晶粒；
一介电层，设置在该基底的上方并且围绕该晶粒和该封胶；
一导电通孔，延伸穿过该介电层；以及
一金属条带，延伸穿过该介电层并沿该介电层延伸，以至少部分地围绕该晶粒。
2.如权利要求1所述的半导体结构，其中该晶粒被该金属条带包围。
3.如权利要求1所述的半导体结构，其中该金属条带的一表面通过该介电层暴露。
4.如权利要求1所述的半导体结构，其中该封胶被设置在该晶粒和该介电层之间。
5.如权利要求1所述的半导体结构，其中该金属条带被设置在该半导体结构的一角落或沿着该导体结构的一边缘设置。
6.如权利要求1所述的半导体结构，其中该金属条带被设置在该导电通孔的上方。
7.如权利要求1所述的半导体结构，其中该导电通孔被设置在该金属条带和该晶粒之间。
8.如权利要求1所述的半导体结构，其中该金属条带被设置在该晶粒和该导电通孔之间。
9.如权利要求1所述的半导体结构，其中该导电通孔的一顶部横截面小于该金属条带一顶部横截面。
10.如权利要求9所述的半导体结构，其中该导电通孔的一顶部横截面具一有圆形形状，该金属条带的一顶部横截面具有一矩形形状。
11.如权利要求1所述的半导体结构，还包括设置在该基底下方的一第一连接器。
12.如权利要求1所述的半导体结构，还包括在该晶粒和该介电层上方的一封装体，该封装体通过一第二连接器接合。
13.如权利要求12所述的半导体结构，其中该第二连接器被设置在该导电通孔的上方并且电连接到该导电通孔。
14.一种半导体结构的制造方法，包括：
提供一载体；
在该载体的上方设置一介电层；
去除该介电层的一第一部分，形成延伸穿过该介电层的一开口；
去除该介电层的一第二部分，形成延伸穿过该介电层并且沿该介电层延伸的一沟槽；
在该开口和沟槽内设置一导电材料，分别形成一导电通孔和一金属条带；
去除该介电层的一第三部分；
将该介电层从该载体分开；
将该介电层设置在一基底的上方；
在该基底的上方设置一晶粒；以及
形成一封胶以围绕该晶粒。
15.如权利要求14所述的制造方法，其中该沟槽沿该介电层延伸以至少部分地围绕该晶粒。
16.如权利要求14所述的制造方法，其中去除该介电层的该第一部分和去除该介电层的该第二部分是同时执行。
17.如权利要求14所述的制造方法，其中去除该介电层的该第三部分是在将该介电层从该载体分开之前或是将该介电层设置在该基底的上方之后执行。
18.如权利要求14所述的制造方法，其中将该介电层设置在该基底的上方包括通过一连接器将该介电层接合到该基底。
19.如权利要求14所述的制造方法，其中通过电镀、物理气相沉积(PVD)、化学气相沉积(CVD)或模板电镀来设置该导电材料。
20.如权利要求14所述的制造方法，还包括通过一连接器将一封装体接合在该晶粒和该介电层的上方。
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