TWI407539B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI407539B
TWI407539B TW095131381A TW95131381A TWI407539B TW I407539 B TWI407539 B TW I407539B TW 095131381 A TW095131381 A TW 095131381A TW 95131381 A TW95131381 A TW 95131381A TW I407539 B TWI407539 B TW I407539B
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Taiwan
Prior art keywords
holes
semiconductor device
film
wafer
main surface
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TW095131381A
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English (en)
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TW200725865A (en
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Toshio Saito
Satoshi Moriya
Morio Nakamura
Goichi Yokoyama
Tatsuyuki Saito
Nobuaki Miyakawa
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Hitachi Ltd
Honda Motor Co Ltd
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Publication of TW200725865A publication Critical patent/TW200725865A/zh
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Publication of TWI407539B publication Critical patent/TWI407539B/zh

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Description

半導體裝置
本發明係關於一種半導體裝置，尤其係關於一種有效適用於將複數個晶片疊層貼合之3次元構造之半導體裝置的技術。
3次元構造的半導體裝置係以3次元將半導體元件積體化於疊合有複數層半導體活性層之構造，藉此迴避2次元構造之半導體裝置所面臨的各種障礙，例如因微影技術的限制、配線電阻的增加或寄生效果所造成之動作速度的飽和傾向、因元件尺寸之微細化所造成的高電場效果等，作為維持提升積體度之有力構造而備受矚目。
關於3次元構造之半導體裝置，例如在日本特開平11-261000號公報(專利文獻1)及日本特開2002-334967號公報(專利文獻2)中已有記載，揭示一種藉由貼合已形成有半導體元件之半導體基板，以製造3次元構造之半導體裝置的方法。而且，在該等文獻中，係揭示一種在貫穿所希望之半導體基板之主背面間的溝內形成稱為垂直相互連接體或埋設連接電極之貫穿電極，以使半導體基板的主背面間成為可導通的構成。
在「DENSO Technical Review Vol.6 No.2 2001」(非專利文獻1)的第15圖中，已揭示一種在3次元構造之半導體裝置之連接孔，以鍍敷法埋設銅(Cu)的技術。
〔專利文獻1〕日本特開平11-261000號公報
〔專利文獻2〕日本特開2002-334967號公報
〔非專利文獻1〕DENSO Technical Review Vol.6 No. 2 2001(第15圖)
一般而言，在半導體裝置之製程中，係採用近接配置複數個直徑較小之正方形連接孔的方法，來作為降低將下層配線與上層配線(或配線與半導體基板)電性連接之連接孔的電阻的方法。
但是，將複數個晶片疊層貼合之3次元構造之半導體裝置的製程中，必須在晶圓形成深寬比(aspect ratio)為20至30左右之較深導電溝，而在其內部埋設連接上下晶片間的導電膜。
如上所述之較深導電溝，若縮小其直徑時，由於難以埋設導電膜，因此必須加大開口面積。但是，若單純加大導電溝之開口面積時，則埋設時所需之導電膜的膜厚(=孔徑的1/2)亦會變大，因此，因成膜後之溫度變化而使導電膜中所產生的應力變大。結果，會造成在導電膜與絕緣膜的界面產生剝離，或在導電膜中產生多數微裂縫(micro crack)的問題。此外，因上述應力而在晶圓產生翹曲，最壞的情形下，亦會有晶圓破裂的情形。
本發明之目的在提供一種可使3次元構造之半導體裝 置的可靠性提升的技術。
本發明之前述內容及其他目的與新穎的特徵可由本說明書之記載及所附圖示明白可知。
以下簡單說明於本案所揭示的發明中具代表性之內容的概要。
本發明係一種半導體裝置，係具備第1半導體基板者，該第1半導體基板具有：形成於主面之複數個第1積體電路元件；以貫穿前述主面及背面的方式所形成的複數個第1貫穿孔；以及具有形成於前述複數個第1貫穿孔之各個的內部，與前述複數個積體電路元件的任一電性連接之第1導電膜，其中，前述主面中之前述複數個第1貫穿孔之各個的開口形狀為長方形。
此外，上述本發明之一態樣中，前述複數個第1貫穿孔係由：其長邊沿著前述主面之第1方向而配向的第1群貫穿孔；以及其長邊沿著與前述主面之前述第1方向不同的第2方向而配向的第2群貫穿孔所構成。
以下簡單說明藉由於本案所揭示的發明中具代表性之內容所得之效果。
在將複數個晶片疊層貼合的3次元構造之半導體裝置的製程中，可防止導電膜剝離或微裂微產生、晶圓翹曲或 破裂等，因此，可使3次元構造之半導體裝置的可靠性提升。
以下根據圖示詳加說明本發明之實施形態。其中，於用以說明實施形態之所有圖示中，原則上係對同一構件標註同一元件符號，並省略反覆說明。
本實施形態之半導體裝置係具有將形成有互異之積體電路的3個半導體晶片(以下簡稱為晶片)C1、C2、C3予以疊層貼合的三次元構造。第1圖係顯示將該半導體裝置安裝在配線基板1且以模塑樹脂2予以封裝之封裝體之一例的剖視圖。
安裝在配線基板1之3個晶片C1、C2、C3中，最下層之晶片C1係透過接著劑3而接著於配線基板1。而中間的晶片C2係透過接著劑3而接著於晶片C1，最上層之晶片C3係透過接著劑3而接著於晶片C2。以下將於後詳加說明，形成於最下層之晶片C1的積體電路與形成於中間層之晶片C2的積體電路係透過形成在晶片C2之複數個貫穿孔4作電性連接，形成於中間的晶片C2的積體電路與形成於最上層之晶片C3的積體電路係透過形成在晶片C3之複數個貫穿孔4作電性連接。亦即，本實施形態之半導體裝置係透過貫穿孔4而將形成在晶片C1、C2、C3之積體電路相互連接，藉此實現所希望的系統。
上述晶片C1、C2、C3與配線基板1係透過在形成於 最上層之晶片C3的複數個接合銲墊5與形成在配線基板1上之複數個電極6之間所接合的複數條Au線7作電性連接。電極6係透過配線基板1內的銅(Cu)配線8而與配線基板1背面的銲錫凸塊9作電性連接。銲錫凸塊9係構成將第1圖所示封裝體安裝在母板(mother board)等時之外部連接端子。
第2圖係顯示本實施形態之半導體裝置之製程流程圖。該半導體裝置之製程係大致分為：在3個半導體晶圓(以下簡稱為晶圓)W1、W2、W3形成不同的積體電路，且在2個晶圓W2、W3形成導電溝之步驟；在晶圓W1、W2形成凸塊電極之步驟；研磨晶圓W2、W3的背面而使導電溝露出，藉此形成貫穿孔4之步驟；貼合晶圓W1、W2、W3，透過貫穿孔4與凸塊電極將積體電路彼此電性連接之步驟；藉由切割晶圓W1、W2、W3，形成三次元構造之晶片C1、C2、C3之步驟；以及將晶片C1、C2、C3封裝(基板安裝、打線接合(wire bonding)、樹脂封裝)之步驟。
以下依步驟順序說明使用3個晶圓(W1、W2、W3)之半導體裝置之製造方法。在各晶圓形成積體電路與貫穿孔4之步驟主要係使用晶圓W2(貼合時位於中間的晶圓)進行說明。
首先，如第3圖所示，備妥由單晶矽構成之厚780μm左右之晶圓W2。然後，將該晶圓W2予以熱處理，在其主面(形成積體電路的面)形成膜厚10nm左右之較薄的 氧化矽膜20，接著在氧化矽膜20上以CVD(Chemical Vapor Deposition，化學氣相沈積)法沈積氮化矽膜21後，利用以光阻膜(未圖示)為遮罩(mask)的乾蝕刻，將元件分離溝形成區域之氮化矽膜21與氧化矽膜20予以去除。形成在晶圓W2與氮化矽膜21之間的氧化矽膜20，係用以緩和在晶圓W2與氮化矽膜21之界面所產生的應力，以防止因該應力而在晶圓W2之表面產生換位等缺陷的緩衝層。
接著，如第4圖所示，藉由以氮化矽膜21為遮罩的乾蝕刻，在元件分離溝形成區域之晶圓W2形成深350nm左右之元件分離溝22，之後在形成貫穿孔4之區域附近的晶圓W2形成深350nm左右之溝23。溝23之平面形狀例如係形成如第5圖所示之四角框狀。
接著，如第6圖所示，在晶圓W2上以CVD法沈積氧化矽膜24後，以CMP(Chemical Mechanical Polishing，化學機械研磨)法研磨、去除元件分離溝22及溝23之各自外部的氧化矽膜24，藉此在元件分離溝22之內部及溝23之內部殘留氧化矽膜24。
接著，將氮化矽膜21予以蝕刻去除後，如第7圖所示，在晶圓W2上以CVD法沈積氮化矽膜25。接著，利用以光阻膜(未圖示)為遮罩的乾蝕刻依序對溝23上部的氮化矽膜25、溝23內部的氧化矽膜24及溝23下方的晶圓W2進行蝕刻，藉此在溝23內側形成深40μm左右的絕緣溝26。如第8圖所示，絕緣溝26係沿著溝23形 成，將其寬度設為比溝23的寬度窄。絕緣溝26的寬度例如為2μm左右。
接著，如第9圖所示，以1000℃左右對晶圓W2進行熱處理，藉此在絕緣溝26的內壁形成氧化矽膜27。接著，如第10圖所示，在晶圓W2上以CVD法沈積多晶矽膜28之後，以回蝕(etch back)去除絕緣溝26外部的多晶矽膜28，藉此在絕緣溝26內部殘留多晶矽膜28。此時，絕緣溝26內部的多晶矽膜28係將其表面高度設為低於晶圓W2的表面。
接著，在晶圓W2上以CVD法沈積氧化矽膜後，以CMP法研磨、去除絕緣溝26外部的氧化矽膜，如第11圖所示，藉此在絕緣溝26內部的多晶矽膜28上形成由氧化矽膜構成的覆蓋絕緣膜29。藉由至此為止的步驟，完成以氧化矽膜27與覆蓋絕緣膜29包圍多晶矽膜28周圍的絕緣溝26。絕緣溝26係在之後步驟中供電性分離形成在晶圓W2主面的積體電路元件與貫穿孔4之用而形成。此外，當在絕緣溝26內壁形成氧化矽膜27時，係以1000℃左右對晶圓W2進行熱處理，因此絕緣溝26最好係比積體電路元件先形成。
接著，將氮化矽膜25蝕刻去除後，如第12圖所示，在晶圓W2的元件形成區域進行n型雜質與p型雜質之離子植入，藉此形成n型阱(well)30與p型阱31。
接著，將晶圓W2表面進行濕蝕刻而去除氧化矽膜20，接著對晶圓W2進行熱處理而在其表面形成閘極氧化膜 32後，如第13圖所示，按照眾所週知的MOS電晶體形成製程在p型阱31形成n通道型MOS電晶體Qn，在n型阱30形成p通道型MOS電晶體Qp。n通道型MOS電晶體Qn主要係由閘極氧化膜32、閘極電極33及n型半導體區域(源極、汲極)34所構成，p通道型MOS電晶體Qp主要係由閘極氧化膜32、閘極電極33及p型半導體區域(源極、汲極)35所構成。閘極電極33係例如在閘極氧化膜32上以CVD法沈積n型多晶矽膜之後，藉由利用以光阻膜(未圖示)為遮罩之乾蝕刻對n型多晶矽膜進行圖案化而形成。n型半導體區域(源極、汲極)34係在p型阱31進行n型雜質(例如磷)之離子植入而形成，p型半導體區域(源極、汲極)35係在n型阱30進行p型雜質(硼)之離子植入而形成。
接著，如第14圖所示，在晶圓W2上以CVD法沈積氧化矽膜36，接著以CMP法研磨氧化矽膜36而將其表面平坦化後，以光阻膜(未圖示)為遮罩而對氧化矽膜36與其下部的晶圓W2進行乾蝕刻，藉此在絕緣溝26內側形成導電溝4A。導電溝4A係在之後的步驟中形成貫穿孔4，自晶圓W2表面至導電溝4A底部為止的深度與絕緣溝26的深度大致相同(40μm左右)。
如第15圖所示，導電溝4A之平面形狀為長方形，其長邊為5.6μm左右，短邊為1.7μm左右。此時，導電溝4A之短邊方向的深寬比為20以上。
導電溝4A係每平均1個由晶圓W2所得晶片(C2) 各形成數千個。此外，雖未特別限定，但在本實施形態中係採用以下構成：將上述長方形導電溝4A各排列配置2個在1個絕緣溝26的內側，將該等2個導電溝4A連接在同一積體電路。
一般而言，在半導體裝置之製程中，係採用近接配置複數個直徑較小之正方形連接孔的方法，來作為降低將下層配線與上層配線(或配線與半導體基板)電性連接之連接孔的電阻的方法。但是，當為具有深度40μm左右之高深寬比的導電溝4A時，當縮小其直徑時，會難以埋設導電膜，因此必須加大開口面積。但是，若單純加大導電溝4A之開口面積時，由於埋設時所需之導電膜的膜厚(=孔徑的1/2)亦會變大，因此，因成膜瞬後之溫度變化而使導電膜中所產生的應力變大。結果，會造成在導電膜與絕緣膜的界面產生剝離，或在導電膜中產生多數微裂縫(micro crack)的問題。此外，因上述應力而在晶圓W2產生翹曲，最壞的情形下，亦會有晶圓W2破裂的情形。
因此，在本實施形態中，將導電溝4A之開口形狀設為長方形。如上述之情形，與近接配置複數個直徑較小之正方形導電溝的情形相比較，變得較容易埋設導電膜，而且開口面積亦變得較大，因此亦可降低電阻。此外，因將導電溝4A之開口形狀設為長方形，因此埋設時所需之導電膜的膜厚為短邊之1/2的厚度即可。因此，因成膜瞬後之溫度變化而使膜中所產生的應力變小，故可抑制上述問題產生。
再者，在本實施形態中，如第16圖所示，形成在由晶圓W2所得之各晶片(C2)內的導電溝4A中，將長邊朝向Y方向之導電溝4A的數量、以及朝向與Y方向正交之X方向之導電溝4A的數量設為大致相同。亦即，形成在晶圓W2之主面整體之導電溝4A中，將長邊朝向Y方向之導電溝4A的數量、以及朝向與Y方向正交之X方向之導電溝4A的數量設為大致相同。
當將導電溝4A之開口形狀設為長方形時，在沈積導電膜後晶圓W2變回常溫時，導電溝4A內之導電膜的收縮量在長邊方向與短邊方向不同。因此，當形成在晶圓W2之導電溝4A的長邊全部朝向同一方向(例如Y方向)時，導電膜的收縮量在Y方向(長邊方向)與X方向(短邊方向)不同，因此會在晶圓W2產生翹曲。相對於此，如第16圖所示，當長邊朝向Y方向之導電溝4A的數量以及朝向X方向之導電溝4A的數量在整個晶圓W2設為大致相同時，導電溝4A內之導電膜的收縮量在Y方向與X方向變得大致相同，因此可抑制晶圓W2翹曲。
第17圖係將導電溝4A之各長邊配向在各相互偏移45度的4個方向之例。此外，第18圖係在1個絕緣溝26之內側各排列配置1個導電溝4A，且將各長邊配向在偏移90度的2方向(X方向及Y方向)之例。該等情形下，亦將朝向各方向之導電溝4A的數量在整個晶圓W2設為大致相同，藉此可抑制晶圓W2翹曲。此外，將導電溝4A配向在如第19圖至第21圖所示之方向時，亦獲得相 同的效果。
接著，使用以下方法在導電溝4A內部充填以鎢(W)為主成分之導電膜。首先，如第22圖所示，在晶圓W2上以濺鍍法沈積膜厚100nm左右之氮化鈦(TiN)膜40。氮化鈦膜40係具有使由氧化矽膜構成之氧化矽膜36與導電膜之接著性提升之功能。以濺鍍法沈積之氮化矽膜40的階梯覆蓋率(step coverage)較低，因此幾乎不會沈積在導電溝4A的內部，而主要沈積在氧化矽膜36表面及導電溝4A之開口部附近。氮化鈦膜40亦具有作為將鎢膜回蝕時之蝕刻擋止件(etching stopper)的功能，因此以較厚的膜厚(100nm左右)沈積。
接著，如第23圖所示，在氮化鈦膜40表面及露出在導電溝4A內部之晶圓W2表面，以CVD法沈積膜厚10至30nm左右的鈦(Ti)膜41。鈦膜41係在之後的熱處理步驟中與露出在導電溝4A內部的晶圓W2(矽)反應而形成鈦矽化物層，因此具有使晶圓W2與導電膜之接著性提升之功能。
接著，如第24圖所示，在鈦膜41表面以CVD法沈積膜厚20至30nm左右之氮化鈦膜42。氮化鈦膜42係具有使在之後步驟中沈積之鎢膜與鈦膜41的接著性提升之功能。此外，氮化鈦膜42亦具有作為防止鎢膜與晶圓W2(矽)反應之阻障層的功能。
接著，將上述晶圓W2插入如第25圖所示之成膜裝置的腔室50內。在腔室50的內部係設有：將晶圓W2保 持為水平之基座(susceptor)(晶圓保持手段)51；將保持在基座51之晶圓W2予以固定之夾環(clamp ring)(晶圓固定手段)52；以及將來源氣體(source gas)及蝕刻氣體供給至晶圓W2表面之噴氣板(shower plate)53等。在腔室50的下部係設有將晶圓W2加熱至所希望之溫度的燈54。
接著，將晶圓W2加熱至390℃左右後，通過噴氣板53將來源氣體(WF6 )供給至腔室50，且在晶圓W2的表面附近使來源氣體熱分解，藉此在氮化鈦膜42的表面沈積鎢膜43a(第26圖)。此時，最好不要以鎢膜43a將導電溝4A的內部完全埋設。亦即，當欲以一次成膜將導電溝4A的內部完全埋設時，鎢膜43a的膜厚會變厚，因此因自成膜步驟至下一個回蝕步驟為止之溫度變化，而使在鎢膜43a所產生的應力變大。因此，如前所述，造成鎢膜43a剝離或微裂縫，或晶圓W2發生翹曲或破裂。此外，如前所述，在本實施形態中，為了減小在鎢膜43a所產生的應力，亦提出將導電溝4A之開口形狀設為長方形的對策。此外，將長邊朝向Y方向之導電溝4A的數量與朝向X方向之導電溝4A的數量在整個晶圓W2設為大致相同，來作為降低晶圓W2翹曲的對策。
接著，如第27圖所示，將導電溝4A外部的鎢膜43a予以回蝕去除。該回蝕係藉由以乾蝕刻裝置將蝕刻氣體(SF6 )供給至晶圓W2表面且施加RF來進行。此外，該回蝕係將覆蓋氧化矽膜36表面的氮化鈦膜40用於蝕刻擋止 件來進行，以使氮化鈦膜40不會完全被去除。當完全去除氮化鈦膜40而露出氧化矽膜36表面時，接著在沈積鎢膜時，容易在氧化矽膜36與鎢膜的界面產生剝離。
接著，將保持在基座51之晶圓W2再度加熱，通過噴氣板53而將來源氣體(WF6 )供給至腔室50，藉此沈積鎢膜43b(第28圖)。藉此方式，以2層鎢膜43a、43b將導電溝4A的內部大致完全埋設。
接著，以乾蝕刻裝置將蝕刻氣體(SF6 )供給至晶圓W2的表面且施加RF，以將導電溝4A外部的鎢膜43a予以回蝕去除(第29圖)。當進行該回蝕時，導電溝4A內部的鎢膜43a亦受到回蝕，而使其表面後退至下方。因此，在腔室50內進一步沈積鎢膜43c，接著將導電溝4A外部的鎢膜43c與氮化鈦膜40予以回蝕去除，藉此將鎢膜43(43a、43b、43c)埋設於導電溝4A的內部(第30圖)。
如上所述，反覆進行複數次沈積與回蝕而將鎢膜43埋設於導電溝4A內部，藉此可使以1次成膜步驟予以沈積的鎢膜43(43a、43b、43c)膜厚變薄，因此可確實迴避鎢膜43剝離、產生微裂縫、及晶圓W2發生翹曲或破裂等問題。其中，在上述說明中，雖已反覆進行3次鎢膜43的沈積與回蝕，但亦可反覆進行4次以上鎢膜43的沈積與回蝕，而使以1次成膜步驟予以沈積的鎢膜43膜厚更加變薄。
此外，以其他方法而言，有在同一腔室50內連續進 行鎢膜43a之成膜與回蝕的方法。由於可藉由成膜瞬後之溫度變化而使鎢膜43a中所產生的應力變小，因此可更加確實減少晶圓W2翹曲。此外，成膜中係以夾環52予以固定，因此晶圓的翹曲受到抑制。該回蝕係藉由將蝕刻氣體(ClF3 或NF3 )供給至保持在前述腔室50之基座51的晶圓W2表面來進行。此外，該回蝕係將覆蓋氧化矽膜36表面的氮化鈦膜40用於蝕刻擋止件來進行，以使氮化鈦膜40不會完全被去除。鎢膜43a的回蝕最好係在鎢膜43a的溫度降到常溫之前來進行。此外，自成膜開始至回蝕完成為止之間，最好以夾環52確實固定晶圓W2。
之後，以CMP研磨法將表面的鎢膜及氮化鈦膜40去除。
接著，如第31圖所示，以CVD法將氧化矽膜37形成在氧化矽膜36上之後，在氧化矽膜37上形成將n通道型MOS電晶體Qn與p通道型MOS電晶體Qp相連接的第1層鋁(Al)配線38。此外，同時形成將導電溝4A內部的鎢膜43與MOS電晶體之一部分(例如p通道型MOS電晶體Qp)相連接的第1層鋁配線39。形成第1層鋁配線38、39時，係在以濺鍍法將鋁合金膜沈積在氧化矽膜37上之後，利用以光阻膜(未圖示)為遮罩之乾蝕刻將鋁合金膜進行圖案化。
接著，如第32圖所示，在第1層鋁配線38、39之上層依序形成：由氧化矽膜構成之第1層間絕緣膜44、第2層鋁配線45、由氧化矽膜構成之第2層間絕緣膜46、第 3層鋁配線47、由氧化矽膜與氮化矽膜之疊層膜構成的表面保護膜48。
以下以與上述相同的方法在其他2個晶圓(W1、W3)分別形成不同的積體電路。接著，使用眾所週知的方法將3個晶圓W1、W2、W3疊層貼合之後，將該等晶圓W1、W2、W3切割，而個片化成三次元構造的晶片C1、C2、C3，將該等晶片安裝在配線基板1且以模塑樹脂2封裝，藉此完成如前述第1圖所示之封裝體。
以上由本發明人所研創之發明係根據實施形態而具體說明，惟本發明並非限定於上述實施形態，在不脫離其要旨的範圍內可為各種變更，自不待言。
(產業利用可能性)
本發明係可適用於將複數個晶片予以疊層貼合之三次元構造之半導體裝置。
1‧‧‧配線基板
2‧‧‧模塑樹脂
3、3a、3b、3c‧‧‧接著劑
4‧‧‧貫穿孔
4A‧‧‧導電溝
5‧‧‧接合銲墊
6‧‧‧電極
7‧‧‧Au線
8‧‧‧銅(Cu)配線
9‧‧‧銲錫凸塊
20‧‧‧氧化矽膜
21‧‧‧氮化矽膜
22‧‧‧元件分離溝
23‧‧‧溝
24‧‧‧氧化矽膜
25‧‧‧氮化矽膜
26‧‧‧絕緣溝
27‧‧‧氧化矽膜
28‧‧‧多晶矽膜
29‧‧‧覆蓋絕緣膜
30‧‧‧n型阱
31‧‧‧p型阱
32‧‧‧閘極氧化膜
33‧‧‧閘極電極
34‧‧‧n型半導體區域(源極、汲極)
35‧‧‧p型半導體區域(源極、汲極)
36、37‧‧‧氧化矽膜
38、39‧‧‧第1層鋁配線
40‧‧‧氮化鈦膜
41‧‧‧鈦膜
42‧‧‧氮化鈦膜
43、43a、43b、43c‧‧‧鎢膜
44‧‧‧第1層間絕緣膜
45‧‧‧第2層鋁配線
46‧‧‧第2層間絕緣膜
47‧‧‧第3層鋁配線
48‧‧‧表面保護膜
50‧‧‧腔室
51‧‧‧基座(晶圓保持手段)
52‧‧‧夾環(晶圓固定手段)
53‧‧‧噴氣板
54‧‧‧燈
C1、C2、C3‧‧‧半導體晶片
Qn‧‧‧n通道型MOS電晶體
Qp‧‧‧p通道型MOS電晶體
W1、W2、W3‧‧‧半導體晶圓
第1圖係顯示將本發明之一實施形態之半導體裝置安裝在配線基板且予以樹脂封裝之封裝體之一例的剖視圖。
第2圖係顯示本發明之一實施形態之半導體裝置之製程的流程圖。
第3圖係顯示本發明之一實施形態之半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第4圖係接續第3圖之顯示半導體裝置之製程的半導 體晶圓的主要部位剖視圖。
第5圖係顯示槽構之平面形狀之半導體晶圓的主要部位俯視圖。
第6圖係接續第4圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第7圖係接續第6圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第8圖係顯示絕緣溝之平面形狀之半導體晶圓的主要部位俯視圖。
第9圖係接續第7圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第10圖係接續第9圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第11圖係接續第10圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第12圖係接續第11圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第13圖係接續第12圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第14圖係接續第13圖之顯示半導體裝置之製程的半導體晶圓的主要部位剖視圖。
第15圖係顯示導電溝之平面形狀之半導體晶圓的主要部位俯視圖。
第16圖係顯示導電溝之平面佈局之半導體晶圓的主 要部位俯視圖。
第17圖係顯示導電溝之平面佈局之其他例之半導體晶圓的主要部位俯視圖。
第18圖係顯示導電溝之平面佈局之其他例之半導體晶圓的主要部位俯視圖。
第19圖係顯示導電溝之平面佈局之其他例之半導體晶圓的主要部位俯視圖。
第20圖係顯示導電溝之平面佈局之其他例之半導體晶圓的主要部位俯視圖。
第21圖係顯示導電溝之平面佈局之其他例之半導體晶圓的主要部位俯視圖。
第22圖係接續第14圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第23圖係接續第22圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第24圖係接續第23圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第25圖係顯示成膜裝置之腔室構造之模式圖。
第26圖係接續第24圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第27圖係接續第26圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第28圖係接續第27圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第29圖係接續第28圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第30圖係接續第29圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第31圖係接續第30圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
第32圖係接續第31圖之顯示半導體裝置之製程的半導體晶圓的主要部位放大剖視圖。
4A‧‧‧導電溝
26‧‧‧絕緣溝
C2‧‧‧半導體晶片
W2‧‧‧半導體晶圓

Claims (14)

  1. 一種半導體裝置，係具備第1半導體基板者，該第1半導體基板具有：形成於主面之複數個第1積體電路元件；以貫穿前述主面及背面的方式所形成的複數個第1貫穿孔；以及形成於前述複數個第1貫穿孔之各個的內部，與前述複數個積體電路元件的任一電性連接之第1導電膜，其特徵為：前述主面中之前述複數個第1貫穿孔之各個的開口形狀為長方形，前述複數個第1貫穿孔係包含：長邊沿著前述主面之第1方向而配向的第1群貫穿孔；以及前述長邊沿著與前述主面之第1方向不同的第2方向而配向的第2群貫穿孔，且前述第1群貫穿孔及第2群貫穿孔為電氣獨立。
  2. 如申請專利範圍第1項之半導體裝置，其中，前述主面中之前述第1方向與前述第2方向所成角度為90度。
  3. 如申請專利範圍第1項之半導體裝置，其中，前述主面中之前述第1方向與前述第2方向所成角度為45度。
  4. 如申請專利範圍第2項之半導體裝置，其中，前述主面中之前述第1群第1貫穿孔數與前述第2群第1貫穿孔數相等。
  5. 如申請專利範圍第1項之半導體裝置，其中，前述複數個第1貫穿孔係包含：前述長邊沿著前述主面之n( n為自然數)個方向而配向的n群貫穿孔，前述n個方向係於前述主面中，按每(180/n)度偏移。
  6. 如申請專利範圍第1項之半導體裝置，其中，前述複數個第1貫穿孔，係藉由將各個長邊配向為同一方向，而且沿著各個短邊方向排列成一行的2個第1貫穿孔設為1組的複數組貫穿孔所構成。
  7. 如申請專利範圍第1項之半導體裝置，其中，復具備在主面形成有複數個第2積體電路元件的第2半導體基板；在前述第2半導體基板上疊層前述第1半導體基板，形成於前述第1半導體基板之主面的前述第1積體電路元件的任一，與形成於前述第2半導體基板之主面的前述第2積體電路元件的任一，係透過前述複數個第1貫穿孔而彼此電性連接。
  8. 如申請專利範圍第7項之半導體裝置，其中，前述第1半導體基板的厚度與前述第2半導體基板的厚度不同。
  9. 如申請專利範圍第7項之半導體裝置，其中，前述第2半導體基板復具有：以貫穿其主面及背面的方式所形成的複數個第2貫穿孔；以及形成於前述複數個第2貫穿孔的各個的內部，與前述複數個第2積體電路元件的任一電性連接之第2導電膜。
  10. 如申請專利範圍第7項之半導體裝置，其中，前述第1貫穿孔之短邊長度為1μm以上，深度比短邊長度的1/2還深。
  11. 如申請專利範圍第1項之半導體裝置，其中，前述第1導電膜係由鎢膜構成。
  12. 如申請專利範圍第1項之半導體裝置，其中，前述第1貫穿孔係具有由第1半導體基板之前述主面貫穿前述背面之絕緣溝，在前述絕緣溝內形成有絕緣膜。
  13. 如申請專利範圍第12項之半導體裝置，其中，前述絕緣溝在平面視圖中係以包圍前述複數個第1貫穿孔的方式來配置。
  14. 如申請專利範圍第13項之半導體裝置，其中，前述絕緣膜係由氧化矽膜構成。
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