CN104347529A - 半导体装置及其制造方法、以及半导体装置的安装方法 - Google Patents

半导体装置及其制造方法、以及半导体装置的安装方法 Download PDF

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Publication number
CN104347529A
CN104347529A CN201410334655.2A CN201410334655A CN104347529A CN 104347529 A CN104347529 A CN 104347529A CN 201410334655 A CN201410334655 A CN 201410334655A CN 104347529 A CN104347529 A CN 104347529A
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China
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film
distribution
dielectric film
thickness
semiconductor device
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CN201410334655.2A
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一之濑一仁
村中诚志
大森和幸
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN104347529A publication Critical patent/CN104347529A/zh
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Abstract

本发明公开了可靠性能够得以改善的半导体装置。所述半导体装置包括：经由第一绝缘膜在半导体衬底之上形成的第一配线；第二绝缘膜，包括覆盖所述第一配线的无机膜并具有已执行CMP处理的平坦表面；第三绝缘膜，形成在所述第二绝缘膜之上并且包括具有比所述第二绝缘膜的抗湿性高的抗湿性的无机膜；以及第二配线，形成在所述第三绝缘膜之上。所述第二配线的厚度比所述第一配线的厚度大10倍或10倍以上，并且所述第二配线位于所述第三绝缘膜之上，而在所述第二配线自身和所述第三绝缘膜之间没有有机绝缘膜插入。

Description

半导体装置及其制造方法、以及半导体装置的安装方法
相关申请的交叉引用
在此通过引用并入2013年8月1日提交的日本专利申请第2013-160544号的全部公布内容，包括说明书、附图和摘要。
技术领域
本发明涉及半导体装置及其制造方法，以及半导体装置的安装方法，并且本发明可优选地应用于包括厚的含有例如铜的最上层配线的半导体装置及其制造方法，以及半导体装置的安装方法。
背景技术
近些年，存在使一个半导体芯片与各种不同安装配置兼容的需求。例如，当以小间距布置的用于引线接合的外部端子转换为以较大间距布置的用于诸如凸电极(例如WPP)的外部端子时，厚的含有铜的重配线(重配线层，最上层配线)被用于半导体芯片的顶表面之上。
这样的重配线层还用于除了上述应用(其中外部端子的间距被转换)之外的其他应用，例如，在日本未审查专利申请公开2007-73611号(专利文献1)中，公开了一种技术，其中无源元件和与其连接的配线通过使用重配线形成在半导体晶片(衬底)之上。具体而言，形成包括二氧化硅膜、氮化硅膜和聚酰亚胺树脂膜的三层绝缘膜以覆盖在衬底之上形成的含有铝(Al)的下层配线。在三层绝缘膜中形成的开口的底部，所述下层配线具有焊盘部，含有铜的重配线的一端与所述焊盘部连接，而另一端在三层绝缘膜之上延伸以与凸电极连接。为了减小施加于凸电极的应力，在包括二氧化硅膜和氮化硅膜的层压结构之上形成的聚酰亚胺膜的厚度比所述层压结构的厚度相对更大。
同样，在日本未审查专利申请公开1998-92817号(专利文献2)中，公开了：具有低介电常数的嵌入式绝缘膜和具有高介电常数和高抗吸湿性的钝化膜依次沉积，通过上述两种膜的复合膜形成配线的表面保护膜。还公开了：通过等离子CVD法沉积的TEOS膜用作具有低介电常数的嵌入式绝缘膜，通过等离子CVD法沉积的氮化硅膜用作钝化膜；在氮化硅膜的沉积之前，通过执行CMP处理使TEOS膜变平。在专利文献2中，描述了：在钝化膜中，不需要考虑台阶部分的覆盖差、针孔或裂缝的发生、局部应力的增加等；因此钝化膜的厚度可以设置为必要的最小值。这就是说，执行通过CMP处理使TEOS膜变平以使在其上形成的钝化膜的厚度小。
本发明的发明人研究了如何通过使用重配线层作为配线来改善半导体装置的运行速度。根据发明人的研究，揭示了：难以在聚酰亚胺树脂膜配设在重配线下方的结构中(如专利文献1中的描述)高密度布置重配线层。还揭示了：如果采用简单地省略聚酰亚胺树脂膜的结构，在重配线层下方的绝缘膜中会产生裂缝，因而从抗湿性角度而言，降低了半导体装置的可靠性。
发明内容
根据本说明书的描述和附图，其它问题和新的特征将会变得清楚。
根据一种实施方式的半导体装置，包括：第一配线，该第一配线经由第一绝缘膜在半导体衬底之上形成；第二绝缘膜，该第二绝缘膜包括覆盖所述第一配线的无机膜并具有在其上已经执行过CMP处理的平坦上表面；第三绝缘膜，该第三绝缘膜形成在所述第二绝缘膜之上并且包括抗湿性比所述第二绝缘膜的抗湿性高的无机膜；第二配线，该第二配线形成在所述第三绝缘膜之上。第二配线的厚度比第一配线的厚度大10倍或10倍以上，第二配线位于第三绝缘膜之上，而在该第二配线自身和第三绝缘膜之间没有有机绝缘膜插入。
根据上述实施方式，半导体装置的可靠性能够得以改善。
附图说明
图1为实施方式的半导体装置的主要部分的平面图；
图2为图示所述实施方式的半导体装置的整个结构的截面图；
图3为所述实施方式的半导体装置的主要部分的截面图；
图4为制造步骤期间所述实施方式的半导体装置的主要部分的截面图；
图5为在图4之后的制造步骤期间所述半导体装置的主要部分的截面图；
图6为在图5之后的制造步骤期间所述半导体装置的主要部分的截面图；
图7为在图6之后的制造步骤期间所述半导体装置的主要部分的截面图；
图8为在图7之后的制造步骤期间所述半导体装置的主要部分的截面图；
图9为在图8之后的制造步骤期间所述半导体装置的主要部分的截面图；
图10为在图9之后的制造步骤期间所述半导体装置的主要部分的截面图；
图11为在图10之后的制造步骤期间所述半导体装置的主要部分的截面图；
图12为在图11之后的制造步骤期间所述半导体装置的主要部分的截面图；
图13为图示所述实施方式的半导体装置的晶片的平面图；
图14为图示所述实施方式的半导体装置的安装方法的工艺流程图；
图15为图示所述实施方式的半导体装置中技术挑战的主要部分的截面图；以及
图16为示出涉及所述实施方式的半导体装置的晶片厚度和晶片弯曲量之间关系的图表。
具体实施方式
在下文中，将基于附图详细描述优选实施方式。在描述实施方式的各附图中，具有相同功能的元件采用相同的附图标记标识，其重复的描述将省略。在以下实施方式中，相同或相似部件的描述原则上不重复，除非尤为必要。
在实施方式中使用的附图中，甚至可以在截面图中省略影线以使这些附图更容易观察。作为选择，甚至可以在平面图中添加影线以使这些附图更容易观察。
(第一实施方式)
参考附图对本实施方式的半导体装置进行描述。图1为实施方式的半导体装置的主要部分的平面图。图1图示了重配线层的平面图案，该重配线层是半导体装置(半导体芯片)的最上层配线，并且图示了仅半导体装置的一角落部分的平面图案。
如图1所示，重配线层(重配线)WM具有矩形形状的焊盘BP部分和从所述焊盘BP延伸的配线WMW部分。焊盘沿着半导体装置SD的端部布置，配线WMW部分从焊盘BP向半导体装置SD的内侧延伸。稍后描述的未图示的MISFET(金属绝缘体半导体场效应晶体管)，在半导体装置SD中形成，配线WMW部分的一端与MISFET电气连接。配线WMW部分的另一端连接至将与之集成的焊盘BP。稍后描述的未图示的连接线，与焊盘BP电气连接。
图2为图示本实施方式的半导体装置SD的整个结构的截面图。半导体装置SD安装在包括Cu引线框架的芯片安装板(die pad)DP之上，多个引线端子LT(每个引线端子均包括Cu引线框架)围绕芯片安装板DP放射状地布置。半导体装置SD中的焊盘BP和引线端子LT通过含有Cu的连接线BW电气连接在一起。半导体装置SD、连接线BW、芯片安装板DP、和引线端子LT通过含有环氧树脂的密封体RB密封。包括半导体装置SD、连接线BW、芯片安装板DP、引线端子LT以及密封体RB的半导体装置SD的整体结构称为密封型半导体装置，但密封型半导体装置可以简单地称为半导体装置SD。密封型半导体装置具有矩形形状，并且在其底部，各引线端子LT的一部分和芯片安装板DP的一部分从密封体RB露出。引线端子LT还从密封型半导体装置SD的侧表面之上的密封体RB露出。
图3为本实施方式的半导体装置SD的主要部分的截面图。在含有硅的p型半导体衬底SB的主表面(顶表面)之上形成多个p型阱区域PW和多个n型阱区域NW，在p型阱区域PW中形成n型MISFET，在n型阱区域NW中形成p型MISFET。包括诸如二氧化硅膜之类的绝缘膜的元件隔离膜(元件隔离区域)STI部分地形成在半导体衬底SB的顶表面之上。在p型阱区域PW和n型阱区域NW，元件隔离膜STI限定了n型MISFET的形成区域和p型MISFET的形成区域。这就是说，在p型阱区域PW的区域形成一个或一个以上n型MISFET，当平面地观察时，该p型阱区域PW的区域由元件隔离膜STI围绕。同样地，在n型阱区域NW的区域形成一个或一个以上p型MISFET，当平面地观察时，该n型阱区域NW的区域由元件隔离膜STI围绕。n型MISFET包括：接触元件隔离膜STI的n型源极区域NSD和n型漏极区域NSD；位于源极区域NSD和漏极区域NSD之间的通道形成区域NCH；以及通过栅极绝缘膜NGI在通道形成区域NCH之上形成的栅极电极NG。p型MISFET包括：接触元件隔离膜STI的p型源极区域PSD和p型漏极区域PSD；位于源极区域PSD和漏极区域PSD之间的通道形成区域PCH；以及通过栅极绝缘膜PGI在通道形成区域PCH之上形成的栅极电极PG。
n型MISFET、p型MISFET、以及元件隔离膜STI由包括氮化硅膜的蚀刻阻止(etching stopper)膜EST覆盖。在蚀刻阻止膜EST之上进一步形成第一层间绝缘膜INS1，所述第一层间绝缘膜INS1包括由子层间绝缘膜SINS11和子层间绝缘膜SINS12形成的层压结构。子层间绝缘膜SINS11包括在蚀刻阻止膜EST之上形成的BP(硼、磷)-TEOS膜，而子层间绝缘膜SINS12包括通过等离子CVD方法在子层间绝缘膜SINS11之上形成的P-SiO膜。在子层间绝缘膜SINS12、子层间绝缘膜SINS11以及蚀刻阻止膜EST中形成多个接触孔CT，各接触孔CT由具有钨膜的第一塞电极PLUG1填塞。第一塞电极PLUG1例如与n型MISFET的源极区域NSD和漏极区域NSD电气连接以及与p型MISFET的源极区域PSD电气连接。在对接触孔CT进行开口时，可以通过下述方式减少当形成接触孔CT时可能发生的对半导体衬底SB的切割：在蚀刻阻止膜EST上以比在子层间绝缘膜SINS11和子层间绝缘膜SINS12上的蚀刻选择比大的蚀刻选择比执行蚀刻。
多个第一配线M1形成在第一层间绝缘膜INS1之上。第一配线M1为含有铜(Cu)的铝(Al)配线，具有在Al配线之下的钛(Ti)和氮化钛(TiN)的层压膜和在Al配线之上的TiN。这就是说，第一配线M1具有层压的结构，从最低层开始包括Ti、TiN、含有Cu的Al以及TiN。顺便提一下，第一配线M1的厚度大约400nm到500nm，含有Cu的Al配线的厚度大约350nm到450nm。第一配线M1位于将与其电气连接的第一塞电极PLUG1之上。
此处，第一配线M1具有多个第一虚拟配线MD1。第一虚拟配线MD1不与第一塞电极PLUG1连接并且是电气浮动的。在不存在第一配线M1的区域，各第一虚拟配线MD1布置为具有彼此相等的预定间距的矩阵模式。当平面地观察时，各第一虚拟配线MD1具有矩形形状。
形成第二层间绝缘膜INS2以便覆盖第一配线M1和第一虚拟配线MD1。第二层间绝缘膜INS2包括由子层间绝缘膜SINS21和子层间绝缘膜SINS22形成的层压结构。下层的子层间绝缘膜SINS21为二氧化硅膜，即，通过具有优良的阶梯覆盖性能的高密度等离子CVD方法形成的USG(未掺杂的硅酸盐玻璃)膜(HDP-USG)，而上层的子层间绝缘膜SINS22为通过等离子CVD方法形成的TEOS膜(P-TEOS)。第二层间绝缘膜INS2具有通过CMP处理变平的平坦表面。在第二层间绝缘膜INS2中形成多个第一过孔V1，第一过孔V1由具有钨膜的第二塞电极PLUG2填塞。第二塞电极PLUG2与第一配线M1电气连接。
多个第二配线M2形成在第二层间绝缘膜INS2之上。第二配线M2包括与第一配线M1相同的部件和相同的结构，并且经由第二塞电极PLUG2与第一配线M1电气连接。与第一虚拟配线MD1相同的第二虚拟配线MD2形成在第二层间绝缘膜INS2之上。
形成第三层间绝缘膜INS3以便覆盖第二配线M2和第二虚拟配线MD2。第三层间绝缘膜INS3包括由子层间绝缘膜SINS31和子层间绝缘膜SINS32形成的层压结构。第三层间绝缘膜INS3具有与第二层间绝缘膜INS2相同的配置，并且具有已执行CMP处理的平坦表面。在第三层间绝缘膜INS3中形成多个第二过孔V2，第二过孔V2由具有钨膜的第三塞电极PLUG3填塞。第三塞电极PLUG3与第二配线M2电气连接。
多个第三配线M3形成在第三层间绝缘膜INS3之上。第三配线M3包括与第二配线M2相同的部件和相同的结构，并且经由第三塞电极PLUG3与第二配线M2电气连接。第三虚拟配线MD3，具有与第二虚拟配线MD2相同的结构，形成在第三层间绝缘膜INS3之上。
形成钝化膜PV以便覆盖第三配线M3和第三虚拟配线MD3。钝化膜PV包括层压结构，该层压结构从其最低层起具有第一钝化膜PV1、第二钝化膜PV2以及第三钝化膜PV3，各钝化膜包括无机绝缘膜。第一钝化膜PV1为HDP-USG膜，而第二钝化膜PV2为通过等离子CVD方法形成的膜(P-TEOS)。第一钝化膜PV1和第二钝化膜PV2形成的层压膜具有已执行CMP处理的平坦表面，该层压膜的总厚度(t1)设置为900nm≤t1≤3000nm。此处，假设：两个第三配线M3之间的第一钝化膜PV1和第二钝化膜PV2的层压膜的厚度为d1；上述层压膜在第三配线M3之上的厚度为d2；第三配线M3的厚度为d3。因为第三层间绝缘膜INS3具有平坦表面，d1几乎等于d2和d3的总和，从而满足此处，“几乎等于”是指满足下面的公式：(d2+d3-d1≤d3×20％)。
第三钝化膜PV3，其包括厚度为600nm到2000nm的氮化硅膜，形成在第一钝化膜PV1和第二钝化膜PV2的层压膜的表面之上，所述表面通过在其上执行CMP处理而变平，如上所述。氮化硅膜具有500MPa到1GPa范围内的压缩应力和大约3×10-6/K的线性膨胀系数。所述压缩应力是指半导体衬底SB由氮化硅膜施加的压缩应力。在第一钝化膜PV1和第二钝化膜PV2的层压膜中形成第三过孔V3，而在第三钝化膜PV3中形成第四过孔V4。在第三过孔V3中、在第四过孔V4中以及直接在包括无机绝缘膜的钝化膜PV上形成重配线层WM。这就是说，在重配线层WM和包括无机绝缘膜的钝化膜PV之间不插入有机绝缘膜。重配线层WM包括由电镀种子膜MSD、镀Cu膜CM以及镀Ni膜NM形成的层压结构。此处，电镀种子膜MSD包括由铬(Cr)膜和Cu膜形成的层压膜，铬(Cr)膜和Cu膜均是通过溅射方法形成，并且该层压膜的厚度为400nm到500nm。镀Cu膜CM为通过电镀方法形成的Cu膜并且具有大约8μm的厚度，而镀Ni膜NM为通过电镀方法形成的Ni膜并且具有大约4μm的厚度。形成镀Ni膜NM以防止镀Cu膜CM的氧化。因为重配线层WM的厚度大约12.5μm，第三配线M3的厚度大约500nm，可以说重配线层WM是厚度比第三配线M3的厚度大10倍或10倍以上的低阻抗配线。
在镀Ni膜NM之上部分地形成通过电镀方法形成的镀Ni薄膜NTM和通过电镀方法形成的镀Au膜AUM。进一步形成保护膜PRO，包括例如聚酰亚胺膜，以覆盖钝化膜PV的上表面、重配线层WM的上表面和侧表面、以及镀Ni薄膜NTM和镀Au膜AUM的层压膜的上表面和侧表面。用于露出镀Au膜AUM的一部分的开口OP配设于保护膜中，含有例如铜的连接线BW与开口OP中的镀Au膜AUM连接。镀Au膜AUM从开口OP露出的那一部分，充当焊盘BP。
图4至图12为主要部分的截面图，图示了根据本实施方式的制造半导体装置SD的方法。图4为处于已形成第三配线M3和第三虚拟配线MD3的阶段的主要部分的截面图，将简要描述一直到此阶段的制造方法。首先，提供p型半导体衬底SB，在该半导体衬底SB的顶表面之上形成n型MISFET(N-MISFET)和p型MISFET(P-MISFET)。接下来，在该半导体衬底SB的顶表面之上形成蚀刻阻止膜EST和第一层间绝缘膜INS1，通过在第一层间绝缘膜INS1上执行CMP处理使第一层间绝缘膜INS1的表面变平。接下来，在第一层间绝缘膜INS1和蚀刻阻止膜EST中开设接触孔CT，在接触孔CT中形成导电的第一塞电极PLUG1。第一塞电极PLUG1例如通过下述方法形成：在接触孔CT中和第一层间绝缘膜INS1之上形成钨膜；并且通过在钨膜上执行CMP处理去除在第一层间绝缘膜INS1之上的钨膜使得钨膜仅选择性地留在接触孔CT中。接下来，在第一层间绝缘膜INS1和第一塞电极PLUG1之上形成第一配线M1和第一虚拟配线MD1。第一配线M1和第一虚拟配线MD1是通过形成第一层金属配线层并且随后通过使用光刻法执行图案化处理形成的，这些步骤未示出。第一层金属配线层具有层压结构，该层压结构从其最低层开始包括Ti、TiN、含有Cu的Al配线以及TiN，各层的金属膜通过溅射方法形成。
接下来，形成第二层间绝缘膜INS2以便覆盖第一配线M1和第一虚拟配线MD1，第二层间绝缘膜INS2的表面通过在其上执行CMP处理而变平。接下来，在第二层间绝缘膜INS2中开设第一过孔V1，在第一过孔V1中形成导电的第二塞电极PLUG2。第二塞电极PLUG2由与第一塞电极PLUG1相同的部件和以相同的方式形成。相应地，第二塞电极PLUG2也通过钨膜形成。接下来，在第二层间绝缘膜INS2和第二塞电极PLUG2之上形成第二配线M2和第二虚拟配线MD2。第二配线M2由与第一配线M1相同的材料和相同的结构形成。
接下来，形成第三层间绝缘膜INS3以覆盖第二配线M2和第二虚拟配线MD2，第三层间绝缘膜INS3的表面通过在其上执行CMP处理而变平。接下来，在第三层间绝缘膜INS3中开设第二过孔V2，在第二过孔V2中形成导电的第三塞电极PLUG3。第三塞电极PLUG3由与第一塞电极PLUG1相同的部件和以相同的方式形成。相应地，第三塞电极PLUG3也通过钨膜形成。接下来，在第三层间绝缘膜INS3和第三塞电极PLUG3之上形成第三配线M3和第三虚拟配线MD3。第三配线M3由与第二配线M2相同的材料和相同的结构形成。
接下来，如图5所示，形成厚度在500nm到2000nm范围内的HDP-USG膜作为第一钝化膜PV1，以覆盖第三配线M3和第三虚拟配线MD3。期望的是使HDP-USG膜的厚度大于或等于第三配线M3的厚度，从而使两个第三配线M3之间的HDP-USG膜的厚度与第三配线M3之上的HDP-USG膜的厚度之间的差变小。这就是说，随着HDP-USG膜的厚度的增加，可以减少HDP-USG膜的表面之上的高低差；然而，如果所述HDP-USG膜的厚度太大，会产生不利的效果，其中HDP-USG膜自身发生断裂等，因此，期望的是使所述厚度为2000nm或更小。此处，考虑到形成HDP-USG膜的时间，所述HDP-USG膜的厚度设置为500nm。
通过使用等离子CVD方法在HDP-USG膜之上形成厚度为1200nm的TEOS膜作为第二钝化膜PV2。考虑到稍后描述的TEOS膜的CMP研磨量，TEOS膜的厚度设置在1200nm到2000nm的范围内。
接下来，如图6所示，通过在第二钝化膜PV2上执行CMP处理去除大约800nm的TEOS膜，使第二钝化膜PV2的表面变平。考虑到磨光面的平坦度，期望的是将CMP研磨量设置为大约800nm到1000nm。因此，第二钝化膜PV2具有平坦的表面，上述公式：(d2+d3-d1≤d3×20％)得以满足。接下来，通过等离子CVD方法在第二钝化膜PV2的平坦表面之上形成具有压缩应力并包括氮化硅膜的第三钝化膜PV3。第三钝化膜PV3同样具有与第二钝化膜PV2的表面一样平坦的表面(上表面)。氮化硅膜的厚度设置在600nm到2000nm的范围内。
接下来，如图7所示，在第三钝化膜PV3之上形成具有第一图案的第一光阻膜PR1，以便通过将第一光阻膜PR1作为掩膜在第三钝化膜PV3中形成第四过孔V4以及在第一钝化膜PV1和第二钝化膜PV2中形成第三过孔V3。通过在第三钝化膜PV3上执行干式蚀刻形成第四过孔V4，随后通过在第二钝化膜PV2和第一钝化膜PV1上执行干式蚀刻形成第三过孔V3。第四过孔V4的开口直径制作成比第三过孔V3的开口直径大。第三配线M3的表面通过第四过孔V4和第三过孔V3从钝化膜PV中露出。
接下来，如图8所示，在钝化膜PV之上并且沿着第四过孔V4和第三过孔V3的侧壁形成电镀种子膜MSD。电镀种子膜MSD为包括下层Cr膜和上层Cu膜的层压膜，各层膜通过溅射方法形成。通过使第四过孔V4的直径比第三过孔V3的直径大可以减少电镀种子膜MSD的断开。电镀种子膜MSD接触待电气连接的第三过孔V3中的第三配线M3。
接下来，如图9所示，在电镀种子膜MSD之上形成具有第二图案的第二光阻膜PR2。第二光阻膜PR2具有第二图案，其中形成重配线层WM的那一部分是开口的。接下来，通过使用电镀种子膜MSD的电镀方法在第二光阻膜PR2的开口部分形成镀Cu膜CM和镀Ni膜NM。镀Cu膜CM也形成在第三过孔V3和第四过孔V4中。
接下来，如图10所示，在第二光阻膜PR2和镀Ni膜NM之上形成具有第三图案的第三光阻膜PR3。第三光阻膜PR3具有第三图案，其中形成焊盘的那一部分是开口的。接下来，通过使用电镀种子膜MSD的电镀方法在第三光阻膜PR3的开口部分中依次形成镀Ni薄膜NTM和镀Au膜AUM。
接下来，如图11所示，去除第三光阻膜PR3和第二光阻膜PR2。接下来，通过使用湿式蚀刻去除由第二光阻膜PR2覆盖的区域(即，不存在镀Cu膜CM和镀Ni膜NM的区域)中的电镀种子膜MSD，能够形成包括电镀种子膜MSD、镀Cu膜CM和镀Ni膜NM的层压结构的重配线层WM。
接下来，如图12所示，形成包括聚酰亚胺膜的保护膜PRO以便覆盖钝化膜PV的上表面、重配线层WM的上表面和侧表面、以及镀Ni薄膜NTM和镀Au膜AUM的上表面和侧表面。在保护膜PRO的形成焊盘BP的区域中形成开口，并且镀Au膜AUM的上表面从保护膜PRO露出。通过上述的步骤，半导体装置SD完成。
图13为图示涉及本实施方式的半导体装置SD的晶片的平面图。如图13所示，多个半导体装置SD形成为在晶片WF的顶表面(主表面)之上以矩阵模式布置，在半导体装置SD之间设置呈格子图案的切割区域DR。在参照图4至图12描述的制造步骤中使用的晶片WF的厚度在晶片WF的直径为300mm的情形下大约775μm。
图14为示出半导体装置SD的安装方法的工艺流程。换而言之，它是示出密封型半导体装置SD的制造步骤的工艺流程图。在下文中，将参照图14描述半导体装置SD的安装方法。在步骤S1中，提供晶片WF，在晶片WF之上布置了通过参照上述的图4至图12描述的制造方法制造出的半导体装置SD。在此阶段，晶片WF在其直径为例如300mm的情形下具有大约775μm的厚度。在步骤S2中，将由树脂膜形成的背面研磨(BG)带(支承部件)附着至晶片WF的主表面以在接下来的晶片BG步骤中保护晶片的主表面。在步骤S3中，在BG带附着于晶片WF的主表面的同时，通过使用磨石研磨晶片WF的背表面，晶片WF的厚度减小至例如大约300mm。在步骤S4中，BG带从厚度已减小的晶片WF上剥离。在步骤S5中，清洗厚度已减小的晶片WF。执行此步骤以去除，例如，在晶片BG步骤中粘接至晶片WF顶表面的BG带的粘合剂以及粘接至晶片WF的研磨沉积物等。在步骤S6中，厚度已减小的晶片WF的背表面侧附着至通过树脂膜形成的切割带(支承部件)。期望的是，在晶片WF的背表面和切割带之间插入带状粘合剂层，其将在执行稍后描述的球式接合时充当粘合剂。在步骤S7中，通过沿着晶片WF顶表面之上以格子图案布置的切割区域DR运行切割刀片来切割晶片WF。通过上述切割将在晶片WF的主表面之上形成的半导体装置SD分割成单个的半导体装置。同样在上述切割中，布置在晶片WF的背表面之上的带形粘合剂层同时被切割。步骤S8为芯片接合步骤，其中已经被单独分割的半导体装置SD和粘合剂层被安装在例如图2中的待粘接半导体装置SD的芯片安装板DP之上。步骤S9为配线接合步骤，其中半导体装置SD的焊盘BP和图2中的引线端子通过含有例如Cu的连接线BW连接在一起。步骤S10为树脂密封步骤，其中半导体装置SD、连接线BW、芯片安装板DP和引线端子LT例如通过环氧树脂密封，如图2所示。通过上述步骤，密封型半导体装置完成。
接下来，将描述已经采用本实施方式的发展以及本实施方式的主要特征和优势。
本发明的发明人研究了如何通过使用重配线层作为配线改善半导体装置SD的运行速度和性能。结果，揭示了：例如，如专利文献1所述，在聚酰亚胺树脂膜配设在重配线层之下的结构中，重配线层的高密度布置是困难的。这是因为聚酰亚胺树脂膜的厚度比诸如二氧化硅膜或氮化硅膜之类的无机绝缘膜的厚度大得多。例如在聚酰亚胺膜中配设的开口的直径大于在无机绝缘膜中配设的开口的直径。此外，当考虑到在开口中的聚酰亚胺膜的侧壁之上形成的电镀种子膜的断开时，所述开口的形状具有如下结构：聚酰亚胺树脂膜的侧壁是倾斜的。当重配线层的端部与倾斜部分重叠时，难以在对重配线层进行图案化中控制重配线层的尺寸，因而重配线层的端部具有完全覆盖所述倾斜部分的形状以便不与聚酰亚胺树脂膜的倾斜部分重叠。尽管这可能是部分原因，但已揭示了：这些因素阻碍了重配线层的高密度布置。因此，本发明的发明人研究了除掉重配线层之下的聚酰亚胺膜。
图15为图示了除去重配线层之下的聚酰亚胺膜时发生的技术挑战的视图。为了简化，省略了第三层间绝缘膜INS3之下的层。两个第三配线M3，以在彼此之间有预定空间的方式彼此相邻，布置在第三层间绝缘膜INS3之上，并且形成钝化膜PV以覆盖第三配线M3。钝化膜PV包括下层的二氧化硅膜和上层的氮化硅膜两层，重配线层WM形成在钝化膜PV之上。本发明的发明人的研究已认识到存在如下挑战：在钝化膜PV的表面存在凹部。据揭示，所述凹部存在于第三配线M3不存在的区域；当重配线层WM的端部与所述凹部重叠时，在钝化膜PV中产生裂缝，这降低了半导体装置SD在抗湿性方面的可靠性。可以认为：例如，重配线层WM在其端部的收缩应力大于在其内部发生的收缩应力；因而当重配线层的端部位于钝化膜PV的凹部时，非常大的应力施加于凹部，导致裂缝。为了防止裂缝，需要采用重配线层WM覆盖钝化膜PV的凹部的结构，或者重配线层的端部不到达钝化膜的凹部的结构。第三配线M3的端部和重配线层WM的端部必须彼此间隔开预定的距离，这成为布置重配线层WM时的主要限制，使得不能实现重配线层WM的高密度布置。据揭示，发生断裂的问题不仅成为半导体装置SD的可靠性降低的原因，还成为阻碍重配线层WM的高密度布置的原因。
在本实施方式中，通过在包括第一钝化膜PV1(第一钝化膜PV1覆盖第三配线M3)和第二钝化膜PV2二者的层压膜上执行CMP处理使第二钝化膜PV2的表面变平，随后形成第三钝化膜PV3。并且，通过采用在第三钝化膜PV3之上形成重配线层WM的结构，能够防止钝化裂缝发生，这能够改善半导体装置SD在抗湿性方面的可靠性。此处，上面已描述了一个例子，其中在包括第一钝化膜PV1和第二钝化膜PV2的层压膜上执行CMP处理；然而，可以在第一钝化膜PV1或第二钝化膜PV2中的单个层上执行CMP处理。
进一步地，采用下述的结构：钝化膜PV包括无机绝缘膜并且重配线层WM布置在钝化膜PV之上。这就是说，因为在第三配线M3和重配线层WM之间未插入有机绝缘膜，所以能够实现重配线层WM的高密度布置，这能够改善半导体装置SD的运行速度。
而且，因为第三虚拟配线MD3布置在与第三配线M3相同的层中，平面地观察时，钝化膜PV的表面在整个半导体装置SD范围内是变平的；因此通过防止钝化断裂能够改善半导体装置SD的可靠性并且能够实现重配线层WM的高密度布置。
接下来，将描述当实现重配线层WM的高密度布置时发生的、引出了本实施方式的另一挑战，以及本实施方式的特征和优势。
当实现重配线层WM的高密度布置时，在晶片WF产生弯曲，例如，由与重配线层WM的收缩有关的应力产生所述弯曲，这导致例如在图14的步骤S4之后的步骤中，晶片WF的处理变得困难的问题。这是因为：如上所述，在图14的晶片背面研磨步骤中，晶片WF的厚度从原始的775μm减小为300μm，因而晶片WF的弯曲通过重配线层WF的收缩应力而变大。例如，在图14的步骤S5的晶片清洗步骤和步骤S6的切割带附着步骤中，执行下述操作：厚度已减小的晶片WF通过由真空镊子或真空吸盘真空吸附和保持来输运。然而，当晶片WF的弯曲变大时，真空吸附和保持晶片变得困难。还据揭示，当厚度已减小的晶片WF弯曲时，产生上述的钝化裂缝。
在本实施方式中，在具有已执行CMP处理的平坦表面的第二钝化膜PV2之上形成具有比第二钝化膜PV2的抗湿性高的抗湿性的第三钝化膜PV3。进一步地，通过使用具有重配线层WM配设在第三钝化膜PV3之上的结构的晶片WF来执行图14中步骤S4之后的步骤，因而即使在厚度已减小的晶片WF中也不产生钝化裂缝，这能够改善半导体装置SD的可靠性。
在本实施方式中，通过使用具有下述结构的晶片WF执行图14中步骤S4之后的步骤晶片：包括氮化硅膜的第三钝化膜PV3形成在具有已执行CMP处理的平坦表面的第二钝化膜之上；重配线层WM设置在第三钝化膜PV3之上，因而即使在减小了晶片WF的厚度之后也能够减少弯曲，这使得晶片的处理成为可能。期望的是，形成第三钝化膜PV3的氮化硅膜具有500MPa到1000GPa的压缩应力和600nm或以上的厚度。因为形成第三钝化膜PV3的氮化硅膜的应力取向为与施加于半导体衬底SB的应力相反的方向，后一个应力由重配线层WM的收缩产生，即使在减小了晶片WF的厚度之后也能够防止弯曲。进一步地，形成第三钝化膜PV3的氮化硅膜具有与含有硅的半导体衬底SB几乎相同的线性膨胀系数，因而即使在晶片WF的厚度减小之后也能够防止弯曲。顺便言之，硅的线性膨胀系数(×10-6/℃)为2.6，氮化硅膜的线性膨胀系数为3.0，Cu的线性膨胀系数为16.8，Ni的线性膨胀系数为12.8。这就是说，尽管在图14的步骤S3的晶片背面研磨步骤中，含有硅且厚度为775μm的晶片WF被研磨至厚度300μm，但通过形成上述的氮化硅膜作为钝化膜PV的一部分能够防止厚度已减小的晶片WF被大幅弯曲。
图16为示出晶片的厚度与晶片的弯曲量之间的关系的图表，所述晶片涉及本实施方式的半导体装置SD并且已经历过背面研磨。此处，半导体装置SD具有图3所示的结构，具有500MPa压缩应力和600nm厚度的氮化硅膜用作第三钝化膜PV3。已经证实，即使在经历背面研磨之后的晶片WF的厚度为300μm时，晶片WF的弯曲量为2.0mm或更小，这在可以处理的范围内。
(第二实施方式)
本发明的第二实施方式对应上述第一实施方式的变形。
参考图4，已经描述了第三配线M3和第二配线M2形成为包括与第一配线M1相同的部件和相同的结构。这就是说，第三配线M3具有层压结构，从最低层起包括：Ni、TiN、含有Cu的Al配线以及TiN，各层的金属膜通过溅射方法形成。
在本第二实施方式中，位于铝配线上层的TiN膜通过高定向溅射方法形成。作为高定向溅射方法，使用公众已知的长抛溅射方法或准直溅射方法。因为通过这样的方法形成的TiN膜的内应力比通过普通溅射方法形成的膜的内应力高，能够获得减小晶片WF弯曲的优势。
参考图8，已描述了电镀种子膜MSD包括下层Cr膜和上层Cu膜的层压膜。在本第二实施方式中，通过高定向溅射方法形成的TiN膜可以用于替代下层的Cr膜。通过TiN膜具有的内部应力能够获得进一步减小晶片WF的弯曲的优势。
在一个例子中，通过高定向溅射方法形成位于Al配线上层的TiN膜，在一个例子中，通过高定向溅射方法形成的TiN膜形成在电镀种子膜MSD的一部分中，上述两个例子可以同时应用。
上文已基于本发明优选的实施方式对由本发明人作出的发明进行了具体描述；然而，本发明不应限于所述实施方式，无需说明，本发明可以在不脱离其主旨的范围了进行各种各样的修改。

Claims (20)

1.一种半导体装置，包括：
半导体衬底；
第一绝缘膜，形成在所述半导体衬底之上；
多个具有第一厚度的第一配线，形成在所述第一绝缘膜之上；
第二绝缘膜，包括覆盖所述第一配线的无机绝缘膜并且具有已执行CMP处理的平坦表面；
第三绝缘膜，包括形成在所述第二绝缘膜的平坦表面之上的无机绝缘膜；以及
多个具有第二厚度的第二配线，形成在所述第三绝缘膜之上；
其中，所述第三绝缘膜具有比所述第二绝缘膜的抗湿性高的抗湿性；以及
其中，所述第二厚度比所述第一厚度大10倍或10倍以上；以及
其中，所述第二配线位于所述第三绝缘膜之上，并且没有有机绝缘膜插入在所述第二配线自身和所述第三绝缘膜之间。
2.根据权利要求1所述的半导体装置，
其中，位于两个所述第一配线之间的区域的所述第二绝缘膜的厚度几乎等于位于所述第一配线之上的所述第二绝缘膜的厚度和所述第一厚度的总和。
3.根据权利要求2所述的半导体装置，
其中，假设在两个所述第一配线之间的区域的所述第二绝缘膜的厚度为d1；在所述第一配线之上的所述第二绝缘膜的厚度为d2；以及所述第一厚度为d3,
则满足下述公式：d2+d3-d1≤d3×20％。
4.根据权利要求1所述的半导体装置，
其中，所述第三绝缘膜具有与施加于所述半导体衬底上的应力方向取向相反的应力，所述施加于半导体衬底上的应力由所述第二配线的收缩产生。
5.根据权利要求4所述的半导体装置，
其中，所述第三绝缘膜具有压缩应力。
6.根据权利要求5所述的半导体装置，
其中，所述第三绝缘膜包括氮化硅膜，该氮化硅膜的厚度t2为600nm≤t2≤2000nm。
7.根据权利要求4所述的半导体装置，
其中，所述第三绝缘膜包括氮化硅膜，而所述第二配线包括Cu膜。
8.根据权利要求7所述的半导体装置，
其中，所述第二配线包括Cu膜和Ni膜的层压膜。
9.根据权利要求7所述的半导体装置，
其中，连接线与所述第二配线连接。
10.一种制造半导体装置的方法，包括下述步骤：
a：经由第一绝缘膜在半导体衬底之上形成多个具有第一厚度的第一配线；
b：在所述第一配线之上形成包括无机绝缘膜并具有第一表面的第二绝缘膜；
c：通过在所述第二绝缘膜的第一表面执行CMP处理形成变平的第二表面；
d：在所述第二表面之上形成第三绝缘膜，所述第三绝缘膜包括具有比所述第二绝缘膜的抗湿性高的抗湿性的无机绝缘膜；以及
e：在所述第三绝缘膜之上形成多个第二配线，所述第二配线具有比所述第一厚度大10倍或10倍以上的第二厚度。
11.根据权利要求10所述的制造半导体装置的方法，
其中，在所述步骤b中形成所述第二绝缘膜的步骤包括下述步骤：
b-1：通过HDP-CVD方法在所述第一配线之上形成第一子绝缘膜；以及
b-2：在所述第一子绝缘膜之上形成包括P-TEOS膜的第二子绝缘膜。
12.根据权利要求10所述的制造半导体装置的方法，
其中，所述步骤e包括下述步骤：
e-1：通过溅射方法在所述第三绝缘膜之上形成Cu种子膜；
e-2：在所述Cu种子膜之上形成光阻膜，所述光阻膜在形成所述第二配线的区域具有开口；以及
e-3：通过电镀方法在所述光阻膜的开口形成Cu配线膜。
13.根据权利要求12所述的制造半导体装置的方法，包括下述步骤：
在所述步骤e-3之后的e-4：通过电镀方法在所述Cu配线膜之上形成Ni配线膜。
14.根据权利要求10所述的制造半导体装置的方法，
其中，所述第三绝缘膜包括氮化硅膜并且具有与施加于所述半导体衬底的应力方向取向相反的应力，所述施加于半导体衬底的应力由所述第二配线的收缩产生。
15.根据权利要求10所述的制造半导体装置的方法，
其中，在所述第一绝缘膜之上形成虚拟配线以便与所述第一配线相邻，并且当平面地观察时所述虚拟配线与所述第二配线重叠。
16.根据权利要求12所述的制造半导体装置的方法，进一步包括下述步骤：在所述步骤e-1之前的e-5：通过高定向溅射方法在所述第三绝缘膜之上形成氮化钛膜。
17.一种半导体装置的安装方法，包括下述步骤：
a：提供半导体晶片，该半导体晶片包括具有主表面和背表面并具有第三厚度的半导体衬底，所述主表面由多个半导体装置形成，
每个半导体装置包括：
第一绝缘膜，形成在所述半导体衬底之上；
多个具有第一厚度的第一配线，形成在所述第一绝缘膜之上；
第二绝缘膜，包括覆盖所述第一配线的无机绝缘膜并且具有已执行CMP处理的平坦表面；
第三绝缘膜，包括形成在所述第二绝缘膜的平坦表面之上的无机绝缘膜；以及
多个具有第二厚度的第二配线，形成在所述第三绝缘膜之上；
所述第三绝缘膜具有比所述第二绝缘膜的抗湿性高的抗湿性；
所述第二厚度比所述第一厚度大10倍或10倍以上；
所述第二配线位于所述第三绝缘膜之上，并且没有有机绝缘膜插入在所述第二配线自身和所述第三绝缘膜之间；
b：通过将第一带附着在所述半导体晶片的主表面侧以及通过研磨所述半导体晶片的背表面形成具有比所述第三厚度小的第四厚度的半导体晶片；
c：在所述第一带从具有第四厚度的半导体晶片剥离之后，通过将第二带附着至所述具有第四厚度的半导体晶片的背表面以在所述具有第四厚度的半导体晶片的主表面侧执行切割，以分割各个半导体装置。
18.根据权利要求17所述的半导体装置的安装方法，
其中，所述第三绝缘膜包括氮化硅膜并且具有与施加于所述半导体衬底的应力方向取向相反的应力，所述施加于半导体衬底的应力由所述第二配线的收缩产生。
19.根据权利要求17所述的半导体装置的安装方法，包括下述步骤：
在所述步骤c之后，
d：在第一引线之上安装所述半导体装置；以及
e：通过连接线将所述第二配线和第二引线连接在一起。
20.根据权利要求19所述的半导体装置的安装方法，包括下述步骤：
在所述步骤e之后的f：通过树脂密封所述半导体装置、所述第一引线、所述第二引线和所述连接线。
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