CN1367533A - 与安装基片有可靠连接的半导体器件 - Google Patents
与安装基片有可靠连接的半导体器件 Download PDFInfo
- Publication number
- CN1367533A CN1367533A CN02102451A CN02102451A CN1367533A CN 1367533 A CN1367533 A CN 1367533A CN 02102451 A CN02102451 A CN 02102451A CN 02102451 A CN02102451 A CN 02102451A CN 1367533 A CN1367533 A CN 1367533A
- Authority
- CN
- China
- Prior art keywords
- resin
- lead
- resin bed
- semiconductor device
- axis body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 229920005989 resin Polymers 0.000 claims abstract description 189
- 239000011347 resin Substances 0.000 claims abstract description 189
- 229910000679 solder Inorganic materials 0.000 claims abstract description 43
- 230000004907 flux Effects 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 44
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 238000010992 reflux Methods 0.000 claims description 19
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 238000003466 welding Methods 0.000 claims description 15
- 239000000470 constituent Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 230000002708 enhancing effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000003014 reinforcing effect Effects 0.000 claims 1
- 230000008878 coupling Effects 0.000 abstract description 5
- 238000010168 coupling process Methods 0.000 abstract description 5
- 238000005859 coupling reaction Methods 0.000 abstract description 5
- 230000002787 reinforcement Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 11
- 230000014509 gene expression Effects 0.000 description 9
- 229920001187 thermosetting polymer Polymers 0.000 description 8
- 230000008901 benefit Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 239000007767 bonding agent Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000011342 resin composition Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
被缩减尺寸的半导体器件包括形成在半导体芯片表面上的多个键合焊盘。多个导线连接到键合焊盘上并从半导体芯片的表面伸出。半导体芯片的表面和多个导线的周边被涂敷树脂层。每个导线和覆盖导线周边的树脂层形成同轴体。多个焊球安装在同轴体的上端部并与导线电连接。提供增强树脂部分,每个增强树脂部分粘接于从同轴体的上端部到焊球的区域上,以便增强焊球与同轴体的连接。
Description
发明的领域
本发明一般涉及半导体器件和工艺,特别涉及具有网格焊球阵列(BGA)型、芯片尺寸封装(CSP)型等的缩减封装结构并与安装基片有可靠连接的半导体器件。
发明的背景
图7是表示具有常规封装结构的半导体器件的截面图,该半导体器件公开在日本专利特许公开公报No.11-243160中,以下称为现有技术1。在图7所示的结构中,半导体芯片2经过包括粘接树脂层3和4的两层粘接并固定到载带自动键合(TAB)带1。设置在TAB带1上的焊盘5经过形成在TAB带1中的通孔与从TAB带1的下表面突出的焊球6连接。而且,半导体芯片2的每个电极(图中未示出)经过键合线8与形成在TAB带1上的键合焊盘7连接。焊盘5和键合焊盘7经过形成在TAB带1上的布线图形(图中未示出)互相连接。此外,半导体芯片2用封装树脂部分9密封或封装。参考标号10表示用于蒸发蒸汽或潮气的孔。
图8是表示具有不同凸起结构的另一常规半导体器件的透视图,该半导体器件公开在日本专利特许公开公报No.10-303244中,且以下称为现有技术2。在图8所示的结构中,在半导体芯片11上形成多个焊盘12。而且,提供多个凸起13,每个凸起设置在焊盘12上且从焊盘12向半导体芯片11上方以预定角度突出。每个凸起13具有接触焊盘12的连接部分4、从连接部分14延伸的线部15和形成在线部15的上部并具有球形形状的端部16。凸起13被热固树脂部分17覆盖。热固树脂部分17部分地被抛光掉,以便只露出凸起13的上端部,即端部16。
图8中所示的常规凸起结构如下制造。首先,利用导引线键合器将导线连接到每个焊盘12。在这种情况下,在导线和对应焊盘12连接的每个焊盘12上的部分上形成圆形连接部分14。而且,在每个线部15的上端形成球形端部16。此后,向半导体芯片11上施加热固树脂17,以使热固树脂17填充凸起13之间的空间。然后固化热固树脂17,由此封装半导体芯片11。而后,抛光热固树脂17,以便露出每个凸起13的端部16。由此,形成具有从每个连接部分14到端部16的长度相对长的凸起的半导体器件。
然而,在具有上述现有技术1的封装结构的半导体器件中,需要作为基片1的TAB带和粘接剂,即粘接树脂层3和4。而且,为了从半导体芯片2电连接到作为外部电极的焊球6上,需要利用键合线8、焊盘7、TAB带上的布线图形(图中未示出)和焊盘5。因此,布线结构变得复杂,并且封装的制造成本高。
而且,在具有现有技术1的封装结构的半导体器件中,不可能得到具有与半导体芯片2的尺寸大致相同的尺寸的BGA型封装。因此,很难缩减BGA封装型半导体器件的尺寸。
另一方面,在具有上述现有技术2的封装结构的半导体器件中,不需要基片、粘接剂等。但是,在用热固树脂17填充凸起13之间的空间之后,需要抛光热固树脂17,以便露出在凸起13的上端的球形端部16。因此,制造工艺复杂,制造成本高。
发明的概述
因此,本发明的目的是,提供用简单工艺和低成本制造具有可靠封装结构的半导体器件。
本发明的另一目的是,提供以低成本制造便于缩减半导体器件尺寸的具有可靠封装结构的半导体器件。
本发明的又一目的是,提供可以低成本制造且具有在半导体器件和外部电路之间高度可靠的电连接的封装结构的半导体器件。
本发明的再一目的是,消除常规半导体器件的封装结构的缺点。
根据本发明的一个方案,提供的半导体器件包括:半导体芯片;形成在半导体芯片表面上的多个键合焊盘;各连接到键合焊盘并从半导体芯片的表面伸出的多个导线;覆盖半导体芯片的表面并覆盖多个导线的周边的树脂层,每个导线和覆盖导线周边的树脂层形成同轴体;各安装在同轴体的上端部并与导线电连接的多个焊球;和各固定到从同轴体的上端部到焊球的区域上以便增强焊球与同轴体的连接的增强树脂部分。
在这种情况下,优选增强树脂部分包括树脂材料,该树脂材料被包括在用于将焊球连接到导线的带有树脂的焊剂中并在带有树脂的焊剂的回流工艺之后留下。
各导线的长度优选为300-1000微米。
优选导线从半导体芯片的表面垂直延伸。
优选的是,包括导线和覆盖导线周边的树脂层的同轴体是可变形的。
还优选导线由金或金合金制成。
优选的是,在包括导线和覆盖导线周边的树脂层的同轴体中,覆盖导线的树脂层的上端部被去掉预定深度,以便形成阶梯部分,并且增强树脂部分固定到从阶梯部分到焊球的区域上。
增强树脂部分优选包括树脂材料,该树脂材料被包含在用于将焊球连接到导线的带有树脂的焊剂中并在带有树脂的焊剂的回流工艺之后留下。
各导线的长度优选为300-1000微米。
导线优选从半导体芯片的表面垂直延伸。
包括导线和覆盖导线周边的树脂层的同轴体优选的是可变形的。
根据本发明的又一方案,提供一种制造半导体器件的方法,该方法包括:提供具有形成在半导体芯片表面上的多个键合焊盘的半导体芯片;通过引线键合将多个导线连接到键合焊盘上,以便导线从每个半导体芯片的表面伸出;在半导体芯片表面上和多个导线的周边上施加树脂层,每个导线和覆盖导线周边的树脂层形成同轴体;通过从同轴体的上端部去掉树脂层,露出每个导线的上端部;在同轴体的上端部设置带有树脂的焊剂;和借助于带有树脂的焊剂在同轴体的上端部设置焊球,并利用回流工艺使焊球与同轴体的导线连接;由此使得带有树脂的焊剂的焊剂成分由于回流工艺而消失,带有树脂的焊剂的剩余树脂成分填充到焊球和同轴体之间的间隙,以便增强焊球与同轴体的连接力。
在这种情况下,在通过从同轴体上端部去掉树脂层而露出每个导线的上端部时,优选通过研磨或刻蚀去掉树脂层。
在通过从同轴体上端部去掉树脂层而露出每个导线的上端部时,还优选将同轴体的上端部切掉,以便露出每个导线的上端部。
各导线的长度优选为300-1000微米。
导线优选由金或金合金制成。
根据本发明的再一方案,提供一种制造半导体器件的方法,包括:提供具有形成在半导体芯片表面上的多个键合焊盘的半导体芯片;通过引线键合将多个导线连接到键合焊盘上,以便导线从每个半导体芯片的表面伸出;在半导体芯片表面上施加树脂层,以将多个导线掩埋在树脂层中;去掉树脂层的上部,以露出每个导线的上端部,并从导线之间的部分进一步去掉树脂层,而留下作为上部树脂涂层的在每个导线周边的薄的树脂层;在半导体芯片的整个区域上施加带有树脂的焊剂;借助于带有树脂的焊剂在导线的上端部设置焊球,并利用回流工艺使焊球与导线连接;进一步从导线之间的部分去掉树脂层,而留下作为比上部树脂涂层厚的下部树脂涂层的在每个导线下周边的树脂层,由此在上部树脂涂层和下部树脂涂层之间形成阶梯部分;由此带有树脂的焊剂的焊剂成分由于回流工艺而消失,带有树脂的焊剂的剩余树脂成分填充从焊球到上部树脂涂层的部分,以便增强带有导线的焊球与上部树脂涂层的连接力。
在这种情况下,在去掉树脂层的上部以露出每个导线的上端部,和从导线之间的部分进一步去掉树脂层而留下在每个导线的周边的薄的树脂层作为上部树脂涂层时,优选利用切割器(dicer)或激光光束去掉该树脂层。
在从导线之间的部分进一步去掉树脂层而留下在每个导线的下周边的树脂层作为厚于上部树脂涂层的下部树脂涂层时,还优选利用切割器或激光光束去掉树脂层。
附图的简要说明
从下面结合附图的详细介绍将更清楚地理解本发明的这些和其它特点和优点,附图中相同的参考标号表示相同或对应部分,其中:
图1是表示根据本发明第一实施例的半导体器件的截面图;
图2A和2B是按照工艺步骤顺序表示制造图1中所示的半导体器件的方法中的工艺步骤的截面图;
图3A和3B是按照工艺步骤顺序表示在制造图1所示的半导体器件的方法中,在图2A和2B所示的工艺步骤之后进行的工艺步骤的截面图;
图4是表示根据本发明第二实施例的半导体器件的截面图;
图5A和5B是按照工艺步骤顺序表示制造图4中所示的半导体器件的方法中的工艺步骤的截面图;
图6A和6B是按照工艺步骤顺序表示在制造图4所示的半导体器件的方法中,在图5A和5B所示的工艺步骤之后进行的工艺步骤的截面图;
图7是表示具有现有技术1的常规封装结构的半导体器件的截面图;和
图8是表示具有现有技术2的常规封装结构的另一半导体器件的透视图。
优选实施例的说明
下面参照附图详细介绍本发明的实施例。
图1是表示根据本发明第一实施例的半导体器件的截面图。在图1所示的半导体器件中,在半导体芯片21的表面上形成多个焊盘或键合焊盘22。虽然图中未示出,在半导体芯片21的表面上还形成各种半导体器件的电路元件。例如由金、金合金等制成的连接线23连接到每个焊盘22上,并相对于半导体芯片21的表面垂直伸出。用薄树脂层24a涂敷半导体芯片21的表面,并且也用薄树脂层24b涂敷每个连接线23的周边。每个连接线23和涂敷连接线23的对应树脂层24b形成同轴体27,连接线23构成该同轴体的中心。每个同轴体27的上端面被磨削或被切割,以便该上端面形成平坦表面。在每个同轴体27的上端面,露出连接线23的端面。
向每个同轴体27的上端面粘接焊球26,以便焊球26与连接线23的上端接触,即与之电连接。用树脂部分25填充焊球26和同轴体27之间的各间隙。树脂部分25增强了焊球26和同轴体27之间的键合力,因此增强了焊球26和连接线23之间的键合力。树脂部分25由包含在带有树脂的焊剂中的树脂成分形成,其中带有树脂的焊剂用于焊球26与连接线23的连接或安装。当向连接线23上施加带有树脂的焊剂或含有树脂的焊剂和利用回流工艺将焊球26键合到连接线23上时,焊剂成分因回流工艺而消失,并且只有树脂成分留在焊球26和同轴体27的上端部周围,作为树脂部分25。
具有上述结构的BGA型半导体器件具有制造成本低的优点,而且还具有焊球26与同轴体27的高键合力的优点。而且,根据本发明的半导体器件经过焊球26安装在图中未示出的安装基片上。在这种情况下,与图7和8中所示的常规半导体器件不同,在安装基片和半导体芯片21之间有间隙,就是说,半导体芯片21经过同轴体27安装在安装基片上,每个同轴体27包括连接线23和树脂层24b,且每个同轴体具有预定长度。因此,通过同轴体27的平缓变形,可以减轻或消除由半导体芯片21和安装基片之间的热膨胀系数的差别引起的应力。因而,在安装半导体器件之后,焊球26不会从安装基片上脱落。
现在,将介绍制造上述半导体器件的制造方法。图2A和2B和图3A和3B是按照制造步骤的顺序表示制造图1所示的半导体器件的方法的截面图。首先,如图2A所示,利用引线键合将连接线23键合到设置在半导体芯片21表面上的每个焊盘22上。连接线23具有例如30μm的直径,并由金、金合金等制成。连接线23从半导体芯片21的表面沿垂直方向延伸,并且被切割成例如300-1000μm的长度。
下面如图2B所示,向半导体芯片21表面和连接线23上施加薄树脂层24,以便涂敷半导体芯片21和连接线23。因此,树脂层24包括薄薄地覆盖半导体芯片21表面的树脂层部分24a和薄薄地覆盖连接线23的树脂层部分24b。由此,得到各包括连接线23和树脂层部分24b的同轴体27。
如图3A所示,在每个同轴体27的上端,通过研磨或刻蚀去掉树脂层部分24b的顶部,露出连接线23的上端部。此后,清洗并去掉连接线23的上端部的污垢和废物,在每个同轴体27的上端表面上施加带有树脂的焊剂25a。在这种情况下,代替用研磨或刻蚀去掉树脂层部分24b的上部,可以从同轴体27切除连接线23的上部和树脂层部分24b的上部。由于通过切割形成连接线23的上端面,因此连接线23的上端面洁净,不需要清洗和去掉连接线23的上端面上的污垢和废物。
而后,如图3B所示,用带有树脂的焊剂25a将焊球26粘接于同轴体27的每个连接线23上,并进行回流工艺,以便将焊球26键合到连接线23上。通过这个回流工艺,带有树脂的焊剂25a中的焊剂成分消失,因而只留下树脂成分并构成树脂部分25。树脂部分25至少填充焊球26和同轴体27的上端部之间的间隙。
根据上述方法,BGA型半导体器件如下制造:通过将连接线23引线键合到半导体芯片21的表面上,因而连接线23在垂直于半导体芯片21的表面的方向延伸。用树脂层部分24b涂敷每个连接线23,以便使连接线23之间隔离或绝缘。然后,利用带有树脂的焊剂25a,将焊球26连接到每个连接线23上。因此,可简化制造工艺并降低制造成本。而且,利用带有树脂的焊剂25a将焊球26连接到连接线23上。这样,在焊剂消失之后,树脂部分25留在焊球26和包括连接线23和树脂部分24b的同轴体27之间,由此从树脂部分25增强了焊球26和同轴体27之间的接合力。即,树脂部分25粘接到焊球26和树脂层部分24b上,并增强了焊球26与同轴体27的连接。
接着,将介绍根据本发明第二实施例的半导体器件和制造该第二实施例的半导体器件的方法。图4是表示根据本发明第二实施例的半导体器件的截面图。在图4中,对应图1中所示的那些部分的部分用相同的参考标号表示,并且省略它们的详细说明。在本例中,在薄薄地涂敷连接线23的每个树脂层部分24b的上端部,将外表面削掉预定深度,由此形成阶梯部分30。由带有树脂的焊剂形成的树脂部分25也留在这个阶梯部分30中,并大大增强了连接到连接线23的上端的焊球26和同轴体27之间的接合力。
在本例中,由于用于增强的树脂部分25不仅提供在焊球26和树脂层部分24b之间的间隙中,这类似于图1中所示的结构,而且提供在从焊球26到阶梯部分30的部分中。因此,树脂部分25的相对大量的树脂支撑着焊球26,因而焊球26和同轴体27之间的接合力变得很大。
现在将介绍制造根据本发明第二实施例的上述BGA型半导体器件的方法。图5A和5B和图6A和6B是按照制造步骤顺序表示制造图4中所示的半导体器件的方法的截面图。首先,如图5A所示,利用引线键合将连接线23键合到设置在半导体芯片21表面上的每个焊盘22上。连接线23具有例如30μm的直径,且由金、金合金等制成。连接线23从半导体芯片21的表面沿垂直方向延伸,并且被切割成例如300-1000μm的长度。接着,向半导体芯片21表面上施加厚树脂层31,以便填充连接线23之间的间隙,直到连接线23的上端被树脂层淹没为止。
然后,如图5B所示,利用切割器或利用激光光束去掉树脂层31的上面部分。在这种情况下,大约去掉树脂层31的厚度的三分之一部分。在这种情况下,也可以去掉每个连接线23的一部分和树脂层31的该部分。由此,露出连接线23的上部。而且,从连接线23之间的部分稍稍切掉树脂层31,以便在每个连接线23的上端部的周边薄薄地留下树脂层31。由此,如图5B所示,在每个连接线23的上端部的周边,在树脂层31中形成包括在其中心的连接线23并成为阶梯部分30的柱状突起。
然后,如图6A所示,在工件的整个区域上施加带有树脂的焊剂32。利用带有树脂的焊剂32,将焊球26粘接到同轴体27的每个连接线23上,并进行回流工艺以将焊球26键合到连接线23上。利用该回流工艺,带有树脂的焊剂32中的焊剂成分消失,因而树脂成分留下并构成树脂部分25。由于带有树脂的焊剂32施加在工件的整个区域上,因此相对大量的树脂存在于每个焊球26和柱状突起30的周边上。因此,在本例中,每个焊球26被树脂部分25牢固地固定于同轴体27上。
如图6B所示,利用切割器或激光光束另外去掉连接线23之间的树脂层31和树脂部分25的部分,以便在连接线23之间形成间隙34。由此,形成以下结构:其中树脂层31薄薄地留在半导体芯片21表面上,和树脂层31薄薄地留在每个连接线23的周边周围以同轴地包围连接线23。由此,形成各包括连接线23和树脂层31的同轴体27。而且,在每个同轴体27的上端部,在树脂层31中形成阶梯部分30,并且在阶梯部分30上,留下在带有树脂的焊剂32的焊剂成分由于回流工艺而消失之后产生的树脂部分25。利用该方式所形成的树脂部分25,增强了焊球26与同轴体27的键合力。由于树脂部分25还存在于阶梯部分30上和树脂部分25的大量树脂存在于阶梯部分30上,因此焊球26和同轴体27的接合力变得很强。
如上所述,根据本发明,提供了这样的半导体器件,其可以用简单工艺和低成本制造,并且由于树脂的增强而在半导体芯片一侧上在焊球26和同轴体27之间具有强的接合力。而且,在根据本发明的半导体器件中,焊球粘接于同轴体上,并且它们之间有间隙,每个间隙具有距离半导体芯片的预定长度。因此,通过同轴体的平缓变形减轻或消除了由半导体芯片21和安装基片之间的热膨胀系数的差别产生的应力。因而,在安装半导体器件之后,焊球不会从安装基片脱落。另外,通过在每个同轴体的上周边部分提供阶梯部分,可以在每个阶梯部分上设置用于支撑焊球的大量树脂。因此,可以显著地增强焊球的接合力。
而且,在根据本发明的制造方法中,在用树脂层涂敷连接线之后,露出连接线的上端部,并将焊球粘接到连接线的上端部。因此,简化了制造工艺,并降低了制造成本。
在前述说明中,已经参照具体实施例介绍了本发明。但是,本领域的技术人员将意思到在不脱离在下列权利要求书所要求保护的本发明的范围的情况下可以做出各种修改和改变。因而,说明书和附图只是示意性的而不是限制性的,所有这种修改将被包括在本发明的范围内。因此,本发明意味着包括落入所附权利要求书的范围内的所有改变和修改。
Claims (19)
1.一种半导体器件,包括:
半导体芯片;
形成在所述半导体芯片表面上的多个键合焊盘;
多个导线,每个导线连接到所述键合焊盘并从所述半导体芯片的所述表面伸出;
覆盖所述半导体芯片的所述表面和覆盖所述多个导线的周边的树脂层,每个所述导线和覆盖所述导线周边的所述树脂层形成同轴体;
多个焊球,每个焊球安装在所述同轴体的上端部并与所述导线电连接;和
增强树脂部分,每个增强树脂部分粘接到从所述同轴体的上端部到所述焊球的区域,以便增强所述焊球与所述同轴体的连接。
2.如权利要求1的半导体器件,其特征在于,所述增强树脂部分包括树脂材料,其被包含在用于将所述焊球连接到所述导线上的带有树脂的焊剂中,并在所述带有树脂的焊剂的回流工艺之后留存下来。
3.如权利要求1的半导体器件,其特征在于,每个所述导线的长度为300-1000微米。
4.如权利要求1的半导体器件,其特征在于,所述导线从所述半导体芯片的所述表面垂直延伸。
5.如权利要求1的半导体器件,其特征在于,包括所述导线和覆盖所述导线周边的所述树脂层的所述同轴体是可变形的。
6.如权利要求1的半导体器件,其特征在于,所述导线由金或金合金制成。
7.如权利要求1的半导体器件,其特征在于,在包括所述导线和覆盖所述导线周边的所述树脂层的所述同轴体中,覆盖所述导线的所述树脂层的上端部被去掉预定深度,以便形成阶梯部分,所述增强树脂部分粘接于从所述阶梯部分到所述焊球的区域上。
8.如权利要求7的半导体器件,其特征在于,所述增强树脂部分包括树脂材料,其被包含在用于将所述焊球连接到所述导线上的带有树脂的焊剂中,并在所述带有树脂的焊剂的回流工艺之后留存下来。
9.如权利要求7的半导体器件,其特征在于,每个所述导线的长度为300-1000微米。
10.如权利要求7的半导体器件,其特征在于,所述导线从所述半导体芯片的所述表面垂直延伸。
11.如权利要求7的半导体器件,其特征在于,包括所述导线和覆盖所述导线周边的所述树脂层的所述同轴体是可变形的。
12.一种半导体器件的制造方法,包括:
提供半导体芯片,该半导体芯片具有形成在所述半导体芯片的表面上的多个键合焊盘;
利用引线键合将多个导线连接到所述键合焊盘上,以便所述导线从所述半导体芯片的所述表面伸出;
在所述半导体芯片的所述表面上和在所述多个导线的周边上施加树脂层,每个所述导线与覆盖所述导线周边的所述树脂层形成了同轴体;
通过从所述同轴体的上端部去掉所述树脂层,露出每个所述导线的上端部;
在所述同轴体的上端部设置带有树脂的焊剂;和
借助于所述带有树脂的焊剂在所述同轴体的上端部设置焊球,并利用回流工艺将所述焊球与所述同轴体的所述导线连接;
由此所述带有树脂的焊剂中的焊剂成分因回流工艺而消失,并且所述带有树脂的焊剂的留下的树脂成分填充所述焊球和所述同轴体之间的间隙,以便增强所述焊球与所述同轴体的连接力。
13.如权利要求12的半导体器件的制造方法,其特征在于,在通过从所述同轴体的上端部去掉所述树脂层而露出每个所述导线的上端部时,所述树脂层是利用研磨或刻蚀去掉的。
14.如权利要求12的半导体器件的制造方法,其特征在于,在通过从所述同轴体的上端部去掉所述树脂层而露出每个所述导线的上端部时,所述同轴体的上端部被切掉以露出每个所述导线的上端部。
15.如权利要求12的半导体器件的制造方法,其特征在于,每个所述导线的长度为300-1000微米。
16.如权利要求12的半导体器件的制造方法,其特征在于,所述导线由金或金合金制成。
17.一种半导体器件的制造方法,包括:
提供半导体芯片,该半导体芯片具有形成在所述半导体芯片的表面上的多个键合焊盘;
利用引线键合将多个导线连接到所述键合焊盘上,以便所述导线从所述半导体芯片的所述表面伸出;
在所述半导体芯片的所述表面上施加树脂层,以便所述多个导线被掩埋在所述树脂层中;
去掉所述树脂层的上部,露出每个所述导线的上端部,并且从所述导线之间的部分进一步去掉所述树脂层,而留下在每个所述导线的周边的薄薄的所述树脂层,作为上部树脂涂层;
在所述半导体芯片的整个区域上施加带有树脂的焊剂;
借助于所述带有树脂的焊剂将焊球设置在所述导线的上端部,并利用回流工艺将所述焊球与所述导线连接;
从所述导线之间的部分进一步去掉所述树脂层,而留下在每个所述导线的下周边的所述树脂层,作为比所述上部树脂涂层厚的下部树脂涂层,由此在所述上部树脂涂层和所述下部树脂涂层之间形成阶梯部分;
因此所述带有树脂的焊剂中的焊剂成分因所述回流工艺而消失,所述带有树脂的焊剂的留下的树脂成分填充从所述焊球到所述上部树脂涂层的部分,以便增强带有所述导线的所述焊球与所述上部树脂涂层的连接力。
18.如权利要求17的半导体器件的制造方法,其特征在于,在去掉所述树脂层的上部以露出每个所述导线的上端部,和从所述导线之间的部分进一步去掉所述树脂层而留下在每个所述导线的周边的薄的树脂层作为上部树脂涂层时,所述树脂层是利用切割器或激光光束去掉的。
19.如权利要求17的半导体器件的制造方法,其特征在于,在从所述导线之间的部分进一步去掉所述树脂层而留下在每个所述导线的下周边的薄的树脂层作为下部树脂涂层时,所述树脂层是利用切割器或激光光束去掉的。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001019298A JP3486872B2 (ja) | 2001-01-26 | 2001-01-26 | 半導体装置及びその製造方法 |
JP019298/2001 | 2001-01-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1367533A true CN1367533A (zh) | 2002-09-04 |
Family
ID=18885197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN02102451A Pending CN1367533A (zh) | 2001-01-26 | 2002-01-22 | 与安装基片有可靠连接的半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6690090B2 (zh) |
JP (1) | JP3486872B2 (zh) |
KR (1) | KR20020063120A (zh) |
CN (1) | CN1367533A (zh) |
TW (1) | TW535268B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10045534B4 (de) * | 2000-09-13 | 2005-03-17 | Infineon Technologies Ag | Elektronisches Bauteil mit Außenanschlußelementen ausgebildet als Kapillarelement, Verfahren zur Herstellung und Anordnung |
US7285867B2 (en) * | 2002-11-08 | 2007-10-23 | Casio Computer Co., Ltd. | Wiring structure on semiconductor substrate and method of fabricating the same |
KR100625021B1 (ko) * | 2004-08-30 | 2006-09-20 | 김봉환 | 가변형 열교환 환기장치 |
JP4619223B2 (ja) * | 2004-12-16 | 2011-01-26 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
WO2007080863A1 (ja) * | 2006-01-16 | 2007-07-19 | Nec Corporation | 半導体装置、該半導体装置を実装するプリント配線基板、及びそれらの接続構造 |
US9978654B2 (en) | 2012-09-14 | 2018-05-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
US9443797B2 (en) | 2012-09-14 | 2016-09-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device having wire studs as vertical interconnect in FO-WLP |
US9818734B2 (en) | 2012-09-14 | 2017-11-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over a temporary substrate |
US9893017B2 (en) | 2015-04-09 | 2018-02-13 | STATS ChipPAC Pte. Ltd. | Double-sided semiconductor package and dual-mold method of making same |
WO2018043129A1 (ja) * | 2016-08-31 | 2018-03-08 | 株式会社村田製作所 | 回路モジュールおよびその製造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5476211A (en) * | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
US5917707A (en) * | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
US4926241A (en) * | 1988-02-19 | 1990-05-15 | Microelectronics And Computer Technology Corporation | Flip substrate for chip mount |
JPH0855856A (ja) | 1994-08-11 | 1996-02-27 | Shinko Electric Ind Co Ltd | 半導体装置とその製造方法 |
JPH08236575A (ja) | 1995-02-22 | 1996-09-13 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH09260428A (ja) | 1996-03-19 | 1997-10-03 | Toshiba Corp | 半導体装置及びその実装方法 |
JP3644189B2 (ja) | 1997-04-25 | 2005-04-27 | ソニー株式会社 | バンプ構造及びその製造方法 |
KR100244504B1 (ko) | 1997-11-15 | 2000-02-01 | 김영환 | 칩 사이즈 반도체 패키지의 제조방법 |
JP3481117B2 (ja) | 1998-02-25 | 2003-12-22 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP3570229B2 (ja) | 1998-07-13 | 2004-09-29 | 松下電器産業株式会社 | 半田接合方法および半田接合用の熱硬化性樹脂 |
JP3825181B2 (ja) * | 1998-08-20 | 2006-09-20 | 沖電気工業株式会社 | 半導体装置の製造方法及び半導体装置 |
US6268662B1 (en) | 1998-10-14 | 2001-07-31 | Texas Instruments Incorporated | Wire bonded flip-chip assembly of semiconductor devices |
JP2000200804A (ja) | 1998-10-30 | 2000-07-18 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2000243874A (ja) | 1999-02-23 | 2000-09-08 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP4809957B2 (ja) * | 1999-02-24 | 2011-11-09 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
US6495916B1 (en) * | 1999-04-06 | 2002-12-17 | Oki Electric Industry Co., Ltd. | Resin-encapsulated semiconductor device |
JP4526651B2 (ja) * | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2001332658A (ja) * | 2000-03-14 | 2001-11-30 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP4356183B2 (ja) | 2000-03-27 | 2009-11-04 | 住友ベークライト株式会社 | 半田接合用レジスト、半導体パッケージ及びその製造方法 |
-
2001
- 2001-01-26 JP JP2001019298A patent/JP3486872B2/ja not_active Expired - Fee Related
-
2002
- 2002-01-22 CN CN02102451A patent/CN1367533A/zh active Pending
- 2002-01-23 TW TW91101118A patent/TW535268B/zh active
- 2002-01-23 KR KR1020020003869A patent/KR20020063120A/ko not_active Application Discontinuation
- 2002-01-28 US US10/056,035 patent/US6690090B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2002222824A (ja) | 2002-08-09 |
JP3486872B2 (ja) | 2004-01-13 |
KR20020063120A (ko) | 2002-08-01 |
US6690090B2 (en) | 2004-02-10 |
US20020100977A1 (en) | 2002-08-01 |
TW535268B (en) | 2003-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1106691C (zh) | 堆叠式半导体芯片封装及其制造方法 | |
CN1194408C (zh) | 以晶片级形成堆积管芯集成电路芯片封装件的方法 | |
US7605476B2 (en) | Stacked die semiconductor package | |
KR100938970B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US7125751B2 (en) | Semiconductor device and method for the fabrication thereof grinding frame portion such that plural electrode constituent portions | |
US20060049528A1 (en) | Semiconductor chip stack structure and method for forming the same | |
US20030045072A1 (en) | Methods of thinning microelectronic workpieces | |
US20050146005A1 (en) | Semiconductor device and manufacturing method thereof | |
CN1215921A (zh) | 模压球栅阵列型半导体器件及其制造方法 | |
CN1095197C (zh) | 半导体晶片 | |
CN1836319A (zh) | 半导体封装中芯片衬垫布线的引线框 | |
CN1099710C (zh) | 半导体器件 | |
CN1541053A (zh) | 布线基体和电子部分封装结构 | |
CN1367533A (zh) | 与安装基片有可靠连接的半导体器件 | |
CN1206727C (zh) | 芯片封装及其制造方法 | |
US6900549B2 (en) | Semiconductor assembly without adhesive fillets | |
CN101060117A (zh) | 芯片堆叠结构以及可制成芯片堆叠结构的晶圆结构 | |
CN1282242C (zh) | 芯片比例封装及其制造方法 | |
US20100136747A1 (en) | Method for manufacturing semiconductor package | |
US7821139B2 (en) | Flip-chip assembly and method of manufacturing the same | |
KR20030040644A (ko) | 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그제조 방법 | |
KR100533847B1 (ko) | 캐리어 테이프를 이용한 적층형 플립 칩 패키지 | |
CN101621046B (zh) | 使用具有空隙的穿通电极的半导体封装 | |
CN1256515A (zh) | 具有栅格焊球阵列结构的半导体器件及其制造方法 | |
KR100273275B1 (ko) | 칩사이즈패키지및그제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20030326 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20030326 Address after: Kanagawa, Japan Applicant after: NEC Corp. Address before: Tokyo, Japan Applicant before: NEC Corp. |
|
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |