TW535268B - Semiconductor device having reliable coupling with mounting substrate - Google Patents
Semiconductor device having reliable coupling with mounting substrate Download PDFInfo
- Publication number
- TW535268B TW535268B TW91101118A TW91101118A TW535268B TW 535268 B TW535268 B TW 535268B TW 91101118 A TW91101118 A TW 91101118A TW 91101118 A TW91101118 A TW 91101118A TW 535268 B TW535268 B TW 535268B
- Authority
- TW
- Taiwan
- Prior art keywords
- resin
- wires
- resin layer
- semiconductor device
- coaxial
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 230000008878 coupling Effects 0.000 title abstract 2
- 238000010168 coupling process Methods 0.000 title abstract 2
- 238000005859 coupling reaction Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 title description 11
- 229920005989 resin Polymers 0.000 claims abstract description 181
- 239000011347 resin Substances 0.000 claims abstract description 181
- 229910000679 solder Inorganic materials 0.000 claims abstract description 79
- 230000004907 flux Effects 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 32
- 239000004020 conductor Substances 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 238000003466 welding Methods 0.000 claims description 8
- 229910001020 Au alloy Inorganic materials 0.000 claims description 6
- 239000004744 fabric Substances 0.000 claims description 6
- 239000003353 gold alloy Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000004519 grease Substances 0.000 claims description 5
- 239000003795 chemical substances by application Substances 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 35
- 239000011229 interlayer Substances 0.000 claims 1
- 238000010309 melting process Methods 0.000 claims 1
- 239000002904 solvent Substances 0.000 claims 1
- 230000002787 reinforcement Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 37
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 239000006184 cosolvent Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000004840 adhesive resin Substances 0.000 description 2
- 229920006223 adhesive resin Polymers 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 2
- 150000002632 lipids Chemical class 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000012752 auxiliary agent Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000006258 conductive agent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 210000003000 inclusion body Anatomy 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000003381 solubilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
535268 五、發明說明(1) 【發明領域】 、 本發明一般關於半導體裝置與製程,尤其關於一種半 導體裝置’具有球柵陣列(Ball Grid Array,BGA)型、一 日日片尺寸封裝(Chip Size Package,CSP)型等之一縮小尺 寸的封裝結構,且與一安裝基板作可靠之結合。 【發明背景】
圖I係顯示具有習知的封裝結構之半導體裝置之剖面 ® ’揭露於曰本專利申請案公開公報第1 1 -243 1 60號且在 下文中被稱為先前技藝1。在圖7所示之結構中,一半導體 曰曰$ 2經由包含黏合樹脂層3與4之兩層而焊接且固定於一 卷 f 自動接合(Tape Automated Bonding,TAB)卷帶1 上。 設於ΤΑβ卷帶1上的墊5經由形成於TAB卷帶1中之孔洞而結 合於從JAB卷帶1之下表面突出的焊球6。亦且,半導體晶 片2之ί 一電極(未圖示)經由一焊接配線8結合於一形成於 TAB卷fl上的焊接墊7。墊5與焊接墊7經由形成於ΤΑΒ卷帶 1上的配線圖案(未圖示)相互結合。更且,半導體晶片2藉 由囊封樹脂部9密封或囊封。參考編號1〇表示一孔洞,用 以抽空蒸氣或溼氣。
圖8_係^顯示具有不同隆起部結構之另一習知的半導體 裝置之示意圖,揭露於日本專利申請案公開公報第 1 0-303 244號且在下文中被稱為先前技藝2。在圖8所示之 結構中,複數個墊1 2形成於一半導體晶片i J上。亦且,設 有複數個隆起部13,其中每一個位於墊12上且其中每一個
第5頁 535268 五、發明說明(2) 以一預定的角度從墊1 2突出朝向半導體晶片1 1之上側。每 7隆起部1 3具有一結合部1 4,接觸於墊丨2、一配線部1 5, ^結合部14延伸、以及一終端部16,形成於配線部15之頂 上^呈球形。隆起部1 3由一熱固性樹脂部1 7所覆蓋。熱 ^〖生树脂部1 7被部分拋光以便僅顯露出隆起部丨3之頂端 部,亦即,終端部1 6。 所示的習知的隆起部結構係如下文般製造。首 藉由使用配線接合器連接配線至墊丨2之每一個。在此 中、’球形結合部14形成於墊12之每一個上配線與對應 ^一 1 2連接之部。亦且,球形終端部丨6形成於配線部丨5之 ,個=上端。隨後,熱固性樹脂1 7供應至半導體晶片11 ra w ί侍熱固性樹脂1 7填滿隆起部1 3間之空間。然後,熱 is Ψί: j ^17硬化而藉以囊封半導體晶片1 1。隨後,拋光熱 JL古收知1 7以顯路隆起部1 3之每一個之終端部1 6。藉以、 4之半導體裝置中從每一結合部14至終端部16之 長度係相對地長。 ¥ “、、,在具有前述先前技藝1之封裝結構之半導體裝 脂層3,愈1要ί為基板1的TAB卷帶與黏合物,亦即,黏合樹 界4極的捏且,、為了從半導體晶片2電性結合至作為外 配:S安ί :::必須使用焊接配線8、墊7、TAB卷帶上的 且封裂之造成本』高而’配線結構變得複雜 可能3ΐΐΐί有先前技藝1之結構的半導體裝置中,不 又侍一具有大約相同於半導體晶片2之尺寸的BGA型封
535268 五、發明說明(3) 裝。因而,難以縮小BGA封裝型半導體裝置之尺寸。 另外,在具有前述先前技藝2之封裴結構的半導 置中’不需要基板、黏合物、或類似者、然而, 二 =樹;L7填滿隆起部13間之空間後,必、拋光熱心:ί 出。因而,製造製程變得複雜,且製造成本變高。,‘、、員路 【發明概述】 因而,本 構之半導體裝 本發明之 半導、體裝置, 小化。 本發明之 以低成本製造 連接之封裝結 本發明之 裝結構之缺點 依據本發 一半導體晶片 表面上;複數 該半導體晶片 晶片之該表面 之每一條與覆 發明之一目的在於 置,可由簡單製程 另一目的在於提供 可以低成本製造且 又另一目的在於提 且提供半導體裝置 構0 提供一種具有可靠封裝結 且以低成本製造。 一種具有可靠封裝結構之 促進半導體裝置之尺寸微 供—種半導體裝置,|古 ”外界電路間高可靠性電 _ 再另一目的在於消除羽1 月除習知的半導體裝置 之封 明之一態樣,提供 ;複.數個焊接墊, 條導線,其中每一 之該表面延伸出; 且覆蓋該複數條導 蓋該複數條導線之 二種半導體裝置,包含: 形成於該半導體晶片之一 條皆結合至該焊接墊且從 樹脂層,覆蓋該半導體 線之周圍,該複數條導線 周園的該樹脂層形成一同 發明說明(4) #體;複數個 1且電性結合 其中每一個附 積,以增強該 在此例子 持料,該樹脂 數條導線之含 之重熔流佈製 亦且較佳 微米之長度。 又較佳者 垂直延伸出。 優點為包 同軸體係可變 亦且優點 又優點為 層之該同軸體 除一預定的深 至從該階梯部 優點為增 料,該樹脂材 條導線之含有 重熔流佈製程 亦且優點 含該導線與 形的。 為該複數條 ’在包含該 中’覆蓋該 度’以形成 至該焊球的 強樹脂部該 料係包括於 樹脂的助熔 後存留下來 為遠複數條 導線係由金 導線與覆蓋 導線的該樹 一階梯部, 面積。 複數個增強 用於結合該 劑中且在該 焊球,其中每一個安裝於該同軸體之頂端部 於該複數條導線;以及複數個增強樹脂部, 加至從該同軸體之一上端部至該焊球的面 焊球與該同轴體之結合。 中’較佳者為該複數個增強樹脂部包含樹脂 材料係包括於用於結合該複數個焊球至該複 有樹脂的助熔劑中且在該含有樹脂的助熔劑 程後存留下來。 者為該複數條導線之每一條具有3〇〇至i〇〇〇 為該複數條導線係從該半導體晶片之該表面 覆蓋該導線周圍的該樹脂層之該 或金合金所形成。 該導線周圍的該樹脂 脂層之一上端部被移 且該增強樹脂部附加 樹脂部包含樹脂材 複數個焊球至該複數 含有樹脂的助熔劑之 導線之每一條具有3〇〇至1〇〇〇微
第8頁 535268 五、發明說明(5) 米之長度。 又優點為 直延伸出。 較佳者為 該同軸體係可 依據本發 方法,包含: 複數個焊接墊 法結合複數條 線從該半導體 導體晶片之該 導線之每 體;藉由從該 出該複數條導 劑於該複數個 樹脂的助熔劑 個頂端部上, 該複數個同軸 程使該含有樹 脂的助熔劑之 個同軸體間之 個同軸體之結 在此例子 上端部移除該 樣,提 複數個 半導體 數個焊 面延伸 複數條 線之周 體之上 之頂端 數個頂 焊球於 炫流佈 條導線 之助溶 成分填 ,以增 該複數條導線係從該半導體晶片之該表面垂 與覆蓋該導線周圍的該樹脂層 包含該導線 變形的。 明之另一態 提供一具有 係形成於該 導線至該複 晶片之該表 表面上與該 條與覆蓋該導 複數個同軸 線之每一條 同軸體之複 配置複數個 且藉由一重 體之該複數 脂的助熔劑 殘留的樹脂 複數個間隙 合力。 中,較佳者 樹脂層而_ 供一種半導體 焊接塾的半導 晶之一表面上 # i ’使得 出;塗佈一樹 導線之周圍上 圍的該樹脂層 端部移除該樹 部,配置含有 端部上;以及 該複數個同軸 製程結合該複 ;藉以藉由該 劑成分消失, 滿該複數個焊 強該複數個焊 裝置之製造 體晶片’該 ,·藉由絲焊 該複數條導 脂層於該半 ,該複數條 形成一同軸 脂層,顯露 樹脂的助烙 經由該含有 體之該複數 數個焊球於 重溶流佈製 且該含有樹 球與該複數 球與該複數 為,在藉由從該複數個同轴體之 露出該複數條導線之每一條之頂
第9頁 五、發明說明(β) 端口Ρ :該步驟中,該樹脂層係藉由研 、且車父佳者為,在藉由從該複數 二=t脂層以顯露出該複數條導線之 =驟中/切除該複數個同軸體之複數 複數條導線之每一條之頂端部。 又較佳者為該複數條導線之每一 米之長度。 優點為該複數條導線係由金或金 依據本發明之又另一態樣,提供 k方法,包含:提供一具有複數個焊 該複數個焊接墊係形成於該半導體晶 ¥法結合複數條導線至該複數個焊接 導線從該半導體晶片之該表面延伸出 半導體晶片之該表面上,使得該複數 中,移除該樹脂層之上部以顯露出該 之頂端部,且更從該複數條導線相互 該樹脂層,同時使該樹脂層薄薄地存 每一條之周圍,作為一上部塗覆樹脂 助熔劑於該半導體晶片之整個面積上 助熔劑配置複數個焊球於該複數條導 上,且藉由一重溶流佈製程結合該複 導線;更從該複數條導線間之複數個 同時使該樹脂層存留於該複數條導線 作為一較該上部塗覆樹脂層厚的下部 磨或#刻而移除。 個同軸體之上端部移 每一條之頂端部的該 個頂端部以顯露出該 條具有300至1 000微 合金所形成。 一種半導體裝置之製 接墊的半導體晶片, 之一表面上;藉由絲 塾上’使得該複數條 ;塗佈一樹脂層於該 條導線埋入 複數條導線 間之複數個 留於該複數 層,塗佈含 ;經由該含 線之該複數 數個焊球於 部分移除該 之每一條之 塗覆樹脂層 該樹脂層 之每一條 部分移除 條導線之 有樹脂的 有樹脂的 個頂端部 該複數條 樹脂層, 下周圍, ,藉以形 ^5268
五、發明說明(7) 成一階梯部於 間;藉以藉由 炫韌成分消失 填滿從該複數 以增強該複數 之結合力。 在此例子 露出該複數條 、線晃間之複數 地存留於該複 知f月旨層的該步 而移除。 該上部塗覆樹脂層與該 該重熔流佈製程使該含 ’且該含有樹脂的助溶 個焊球至該上部塗覆樹 個焊球與該複數條導線 中,較佳者為,在移除 導線之每一條之頂端部 個部分移除該樹脂層, 數條導線之每一條之周 驟中,該樹脂層係藉由 下部塗覆樹脂層之 有樹脂的助溶劑之助 劑之殘留的樹脂成分 脂層之複數個部份, 及該上部塗覆樹脂層 該樹脂層之上部以顯 ’且更從該複數條導 同時使該樹脂層薄薄 圍,作為一上部塗覆 使用切割機或雷射束 移除該樹^二者Ϊ L在更從該複數條導線間之複數個部分 一條‘下』ίι,1日守使該樹脂層存留於該複數條導線之每 mr ^1 ,作為一較該上部塗覆樹脂層厚的下部塗覆 移除。 該树知層係籍由使用切割機或雷射束而 【較佳實施例之詳細說明】 之詳==等;其他特徵與優點將從下文中附有圖示 示中π等戈對廄加伯楚,其中類似的參考編號表示全部圖 下甲同#或對應的部分。 丨Μ 參,附圖_ ’兹將詳細說明本發明之實施例如下。 圖1係顯示依據本發明第一實施例之半導體裝置之剖
535268 五 、發明說明(8) -----— 开面二if導所體示曰的;:導體裝置卜複數個塾或焊請2 Ϊΐί各之表面上。雖然未圖示,但半導體 由,舉例而言,全::成於半導體晶片21之表面上。 23結合於墊22之每一 ί合金、或類似者所形成的結合配線 直地向外延伸。相對於半導體晶片21之表面垂 24a,且結合配線之,之表面塗覆有一薄樹脂層 24b。每一結人酡綠^母一個之周圍亦塗覆有一薄樹脂層 ,,.π ° 3與塗覆結合配線2 3之對應的樹脂層 轴體27 ’其中結合配線23構成其中心。同轴 體U:乒:之上端表面係接地或被切除,使得上端表面 形ϋΐί5。在同轴體27之每一個之上端表面中,結合 配線2 3之末端表面顯露出。 在同軸體2 7之每一個之上端表面上,附加一焊球2 6, 使得焊祕接觸,亦即,電連接至結合配線23之上端。焊 球2 6 $ =轴體27間之每一間隙被樹脂部25填滿。樹脂部25 立曰強烊ί/ 2 6與同軸體2 7間之焊接力,因此增強焊球2 6與結 合配線23間之焊接力。樹脂部25係由在用於結合或安裝焊 球26於結合配線23之含有樹脂的助熔劑中所含的樹脂成分 所產生。當塗佈含有樹脂的助熔劑,舉例而言,於結合配 線23上且焊球26藉由使用重熔流佈製程焊接至結合配線23 2,助熔劑成分藉由重熔流佈製程而消失且僅樹脂成分殘 召於焊球26與同軸體27之頂端部周圍,作為樹脂部25。 具有前述結構之BGA型半導體裝置具有低製造成本之 優點,亦且具有焊球26對同軸體27之高焊接力之優點。亦
535268 五、發明說明(9) 且’依據本實施例之半導體裝置經由焊球26安裝於一未圖 示的女裝基板上。在此例子中,不同於圖7與圖8所示之^ 知的半導體裝置,安裝基板與半導體晶片2丨間存有間隙, 亦即’半導體晶片21經由同軸體27安裝於安裝基板上,該 同軸體27之每一個皆包含結合配線23與樹脂層24b且具有 一預定的長度。因而,由半導體晶片21與安裝基板間之熱 膨脹係數差異所造成的應力可藉由同轴體27之溫和變形而' 減緩或消除。所以,在安裝半導體裝置之後,焊球26 ^合 脫離安裝基板。 曰 茲將說明前述半導體裝置之製造方法。圖以與⑼以及 圖3 A與3B係按照製造步驟之順序顯示圖1所示的半導體裝 置之製造方法之剖面圖。首先’ %圖2A所示,藉由絲谭法 將二結合配線23焊接至設於半導體晶片21之表面上的墊2 之母-個上。結合配線23具有’舉例而言,直徑3〇心, ^金 ' 金合金、或_者所形成。結合配線23係形 攸半導體晶片2 1之表面以垂直方& 山 且万向延伸,且於,舉例而 言,於長度300至1000 /ζηι處切斷。 接著,*圖2B所不,一薄樹脂層2 =結合配線23之表面上,以塗覆半導體晶片21與結合i J23。,而’樹脂層24包含-薄薄地覆蓋半導體晶片21之 =樹脂層部24a以及一薄薄地覆蓋結合配線心樹脂之 層424b。猎以,獲得同軸體27,其 配線23與樹脂層部24b。 ° 如圖3A所示,在同轴體27之每一個之頂端,藉由研磨
第13頁 535268
^餘刻移除樹脂層部24b之頂部,且結合配線23之頂端 。隨後,清潔並移除結合配線23之頂端部之。 廢物,且含有樹脂的助熔劑25a塗佈於同軸體27之每一個、 2端表面上。在此例子中,可以將結合配線以之頂部盥 树知層部24b之頂部從同轴體27切除,代替藉由研磨斂、 刻移除樹脂層部24b之頂部。既然結合配線23之頂端表 =切除’故結合配線23之頂端表面清潔並且無須清潔與移 除結合配線2 3之頂端表面處之污塵與廢物。 五 '發明說明(10)
隨後,如圖3B所不,藉由使用含有樹脂的助熔劑25& 附加一焊球26至同軸體27之結合配線23之每一個上,且進 行一重熔流佈製程以焊接焊球2 6至結合配線2 3。藉由此重 熔流佈製程,在含有樹脂的助熔劑2 5a内之助熔劑成分消 失,以致僅剩餘樹脂成分且構成樹脂部25。樹脂部25至少 填滿焊球2 6與同軸體2 7之上端部間之間隙。
依據前述方法,藉由使結合配線2 3絲焊至半導體晶片 21之表面上而製造一BGA型半導體裝置,使得結合配線㈡ 以垂直於半導體晶片21之表面的方向延伸。結合配線2 3之 每一個皆塗覆有樹脂層部24b以使結合配線23相互間隔絕 或絕緣。隨後’藉由使用含有樹脂的助溶劑2 5 a,焊球2 6 聯合至結合配線2 3之每一個上。因而,可簡化製造製程並 降低製造成本。亦且,藉由使用含有樹脂的助熔劑25a使 焊球2 6聯合至結合配線2 3上。因此,在助溶劑消失後,樹 脂部25存留於焊球26與包括結合配線23與樹脂層部24b的 同軸體27間,藉樹脂部25增強焊球26與同軸體27間之聯合
第14頁 535268
力。亦即,樹脂部25黏合至焊球26與樹脂層部24b,且择 強焊球26與同軸體27之黏合。 曰 接著,說明依據本發明第二實施例之半導體裝置與依 據第二實施例之半導體裝置之製造方法。圖4係顯示依據 本發明第二實施例之半導體裝置之剖面圖。在圖4中,董 應於圖1之部份由相同的參考編號表示,且此處省略其詳 細說明。在此實施例中,在薄薄塗覆著結合配線23的每^ 一 ,脂層部24b之上端部處,外表面被刮除一預定的深度, 猎以形成一階梯部30。從含有樹脂的助熔劑所產生的樹脂 部25亦殘留於此階梯部30中,強壯地增強結合於結合配 23之上端的焊球26與同軸體27間之聯合力。 、 在此貝軛例中,既然增強用的樹脂部2 5不僅設於焊球 2 6與樹脂層部2 4 b間之間隙Φ l门m, u丨』< 间I承〒,如同圖1所示之結構, 於從焊球2 6至階梯部3 〇之部a a α 士旦μ似& + Ρ份中。因而,樹脂部25的相對 大ϊ的樹月曰支持著焊球26, . 合力變得非常大。 绞坪竦26與同軸體27間之聯 裝置= :第二實施例之前_型半導體 ^ ^ m ^ ml " ” 5B以及圖6A與6B係按照製造步驟 所示的半導體裝置之製造方法之剖面圖 半導體曰二# I,藉由絲埤法使結合配線23焊接至設於 千等脰曰日片21之表面上的墊2 — 有,舉例而言,直徑30㈣2,::個上。結合配線23具 所形成。結合配線23係形成 *、金合金、或類似者 面的方向上延伸,且於,^為以垂直於半導體晶片21之表 、 牛例而言,長度300至1000 // m
535268 五、發明說明(12) f切斷植=,厚樹脂層31塗佈至半導體晶片21之表面 上端=ί合配線23相互間之間隙,直到結合配線23之 上》儿入知丨月日層。 除核ϋι t „斤示’藉由切割機或藉由使用雷射束移 表面部。在此例子中’大約樹脂層31之厚 ίϊ::ί::皮移除。★此例子中,亦可移除結合配_ 配纟卩分與樹脂層31之一部分。藉以顯露出結合 除樹Ρ # Ή、° :亦且,從結合配線23相互間之部份些微切 二曰f 得樹脂層31薄薄地殘留於結合配線23之每 每一個之周圍。藉以,如圖5B所示,結合配線23之 t 、,上端部之周圍,包括位於中心處之結合配線2 ]曰 隻成$梯部3 0的-柱狀突出部形成於樹脂層31中。 件之:圖6A所示,含有樹脂的助熔劑32塗佈於工作 焊球2二至η鲇t。藉由使用含有樹脂的助熔劑32,附加一 =佈=焊接焊球26至結合配線23。#由此佈重 殘留樹脂助熔劑32内的助熔劑成分消失,以致 塗佈於工樹脂部25。I然含有樹脂的助炼_ 焊球26斑!固面積上’相對大量的樹脂存在於每- 球26之每—固;23°之周圍。因而,在此實施例中,焊 個猎由樹脂部2 5強壯地固定至同轴體2 7。 層31 ΐ ΐ: Ϊ :丄藉由使用切割機或雷射束額外移除樹脂 。配線23相互間。藉以’形成如下之結構:樹脂
第16頁 535268 五、發明說明(13) 層3 1薄薄地殘留於半導體晶片2 1之表 薄地殘留於每一結合配線2 3之周圍, 線23。藉以,同軸體27形成為其中每 23與樹脂層31。亦且,在同軸體27之 形成有階梯部3 0於樹脂層31中,並且 留著在含有樹脂的助熔劑3 2之助炼劑 而消失後所產生的樹脂部2 5。藉由以 部25,增強焊球26與同軸體27之焊接 存在於階梯部3 0上且樹脂部2 5之大量 30上,故焊球26與同軸體27之聯合力 如前所述,依據本發明,提供一 由簡單製程且以低成本製造,且具有 焊球與同軸體間之強壯的聯合力於半 且,在依據本發明之半導體裝置中, 間隙且其中每一個皆具有從半導體晶 同軸體。因而,由半導體晶片21與安 數差異所造成的應力可藉由同轴體之 除。所以,在安裝半導體裝置之後, 板。更且,藉由提供階梯部於同軸體 部,可配置大量的樹脂,用以支持 處。因而,可更強壯地增強、纟曰 、 艰坪球之聯 亦且,在依據本發明之製造方、 結合配線之後’結合配線之頂端部 合配線之頂端部。因而,可銪此如" 」間化製造 面上亦 以同袖 一個皆 母一個 ’在階 成分因 此方式 力。既 的樹脂 變得非 種半導 因藉由 導體晶 焊球附 片起一 裝基板 溫和變 焊球不 之每一 球於階 合力。 中,在 露出且 製程並 且樹脂 地環繞 包含結 之上端 梯部3 0 重熔流 所形成 然樹脂 存在於 常強。 體裝置 樹脂而 片側上 加至其 預定的 間之熱 形而減 會脫離 個之上 梯部之 層31薄 結合配 合配線 部處5 上,殘 佈製程 的樹脂 部2 5亦 階梯部 ,可藉 增強之 。亦 間具有 長度之 膨脹係 缓或消 安裝基 周圍 每一個 以樹脂層塗覆 焊球燁接至結 降低製造成
IH
第17頁 535268 五、發明說明(14) 本0 在前述說明書中,已經參照具體實施例說明本發明。 然而,熟悉此項技藝之人士明瞭可在不偏離下文申請專例 範圍中所述之本發明之範圍下進行各種修改與變化。據 此,說明書與圖示僅為例示性質而非限制性質,並且所有 此類修改皆包括於本發明之範圍中。因而,此發明意圖包 含落於申請專利範圍之範圍内的所有變動與修改。
第18頁 535268 圖式簡單說明 圖1係顯示依據本發明第一實施例 面圖; 圖2A與2B係按照製程步驟之順序 體裝置之製造方法中之製程步驟之叫:$圖1所 圖3A與3B係按照製程步驟之順序印; v +導 體裝置之製造方法中在圖2A與2B所示沾示圖1所条 製程步驟之剖面圖; 、製韃步领、> 的半導 圖 面圖 4係顯示依據本發明第二實施仓 J <半 導體裝薏 行的 圖5A與5B係按照製程步驟之順序〜 體裝置之製造方法中之製程步驟之剖圖4所示 圖6 A與6 B係按照製程步驟之順序:, 、率導 體裝置之製造方法中在圖5A與5B所示的=圖4所示 製程步驟之剖面圖; 、攻稳歩顿、>、率導 圖7係顯示一具有先前技藝丨之習知 锬進 體裝置之剖面圖;以及 的封裝 行的 圖8係顯示另一具有先前技藝2之 半導體裝置之示意圖。 知 【符號說明】 1 卷帶 2 半導體晶片 3 黏合樹脂層 4 黏合樹脂層 的隆 結樽 起部 支半導 結樽
第19頁 535268 圖式簡單說明 5 墊 6 焊球 7 焊接墊 8 焊接配線 9 囊封樹脂部 10 孔洞 11 半導體晶片 12 墊 13 隆起部
14 結合部 15 配線部 16 終端部 17 熱固性樹脂部 21 半導體晶片 22 烊接墊 23 結合配線
24 樹脂層 24a 樹脂層 24b 樹脂層 25 樹脂部 25a 含有樹脂的助熔劑 26 焊球 27 同軸體 30 階梯部
第20頁 535268 圖式簡單說明 31 樹脂層 32 含有樹脂的助熔劑 34 間隙
第21頁 II·!
Claims (1)
- 535268 六、申請專利範圍 一種半導體裝置,包含: 一半導體晶片; 複數個焊接墊,形成於該半導體晶片之一表面上; 、 複數條導線,其中每一條皆結合至該焊接墊且從該 導體晶片之該表面延伸出; 、一樹脂層’覆蓋該半導體晶片之該表面且覆蓋該複 條導線之周圍,該複數條導線之每一條與覆蓋該複數條 線之周圍的該樹脂層形成一同軸體; 複數個焊球,其中每一個安裝於該同軸體之頂端部 且電性結合於該複數條導線;以及 複數個增強樹脂部,其中每一個附加至從該同軸體 一上端部至該焊球的面積,以增強該焊球與該同軸體之 合0 2·如申請專利範圍第1項之半導體裝置,其中該複數個 ^樹脂部包含樹脂材料,該樹脂材料係包括於用於結合 複數個焊球至該複數條導線之含有樹脂的助熔劑中且 含有樹脂的助熔劑之重熔流佈製程後存留下來。 3.如一申請專利範圍扪項之半導體褒置,其中該複數條 線之母一條具有300至1〇〇〇微米之長度。 半 數 導 上 之 結 增 該 該 導 4 ·如申請專利範圍第1項之半導體裝置, 線係從該半導體晶片之該表面垂直延伸出 其中該複數條 導第22頁 535268'申請專利範圍 ^如^申請專利範圍第1項之半導體裝置,其中包含該導線 一覆蓋該導線周圍的該樹脂層之該同軸體係可變形的。 ^ 〃如申請專利範圍第1項之半導體裝置,其中該複數條導 、、泉係由金或金合金所形成。 k @如申請β專利範圍第1項之半導體裝置’其中’在包含該 、、、與覆蓋該導線周圍的該樹脂層之該同軸體中,覆蓋該 的該樹脂層之一上端部被移除—預定的深度,以=成 階梯部,且該增強樹脂部附加至從該階梯部至該焊球 IHJ Jtin ο ^ 8·如申請專利範圍第7項之半導體裝置,i中哕遴 ?樹脂部包含樹脂材料,該樹脂材料係包括於;於社=增 二,個T球至該複數條導線之含有樹脂的助炫劑‘ 了二, 〜3有樹脂的助熔劑之重熔流佈製程後存留下來。 在 9·如申請專利範圍第7項之半導體裝置,其中 線之每一條具有30 0至1〇 〇〇微米之長度。“ "I數條導 1〇·如申請專利範圍第7項之半導體裝置,苴由分乂 * 導線係從該半導體晶片之該表面垂直延伸出、。以旻數條第23頁 535268 六、申請專利範圍 11·如申請專利範圍第7項之半導體裝置,其中包含該導 線與覆盍該導線周圍的該樹脂層之該同軸體係可變形的。 12· 一種半導體裝置之製造方法,包含·· 提供一具有複數個焊接墊的半導體晶片,該複數個焊 接墊係形成於該半導體晶之一表面上; 藉由絲焊法結合複數條導線至該複數個焊接墊上,使 得該複數條導線從該半導體晶片之該表面延伸出; 、塗佈一樹脂層於該半導體晶片之該表面上與該複數條 導線之周圍上,該複數條導線之每一條與覆蓋該導線之周 圍的該樹脂層形成一同軸體; 藉由從該複數個同軸體之上端部移除該樹脂層,顯露 出该複數條導線之每一條之頂端部; 配置含有樹脂的助熔劑於該複數個同軸體之 端部上;以及 K 利用該含有樹脂的助熔劑配置複數個焊球於該 同軸體之該複數個頂端部上,且藉由-重熔流佈製程社1 該複數個焊球於,複數個同軸體之該複數條導線;…口 依上方式,錯由該重熔流佈製程使該含有樹脂的 劑之助熔劑成分消失,且哕冬古姑 助像 脂成分填滿該複數個焊球的助熔劑之殘留的樹 隙,以增強該複數個;同軸體間之複數個間 坪衣與該複數個同軸體之結合力。 13.如申請專利範圍第12項之半導體裝置之製造方法,复535268 六、申請專利範圍 數個同軸體之上端部移除該樹脂層而顯 二數條導線之每—條之頂端部的該步驟中,該樹脂 層係猎由研磨或韻刻而移除。 t申請專利範圍第12項之半導體裝置之製造方法,1 ΐ出數個同軸體之上端部移除該樹脂層以顯 路出5亥複數條V線之每一條之頂端部的該步驟中,切除該 禝^固同軸體之複數個頂端部以顯露出該複^ 一條之頂端部。 ^ 15·如申請專利範圍第1 2項之半導體裝置之製造方法,並 中該複數條導線之每一條具有3〇()至1〇〇〇微米之長度。八 16·如申請專利範圍第12項之半導體裝置之製造方法,其 中該複數條導線係由金或金合金所形成。 17· —種半導體裝置之製造方法,包含: 提供一具有複數個焊接墊的半導體晶片,該複數個 接墊係形成於該半導體晶之一表面上; 藉由絲焊法結合複數條導線至該複數個焊接墊上, 得該複數條導線從該半導體晶片之該表面延伸出; 塗佈一樹脂層於該半導體晶片之該表面上,使得談 數條導線埋入該樹脂層中; 移除該樹脂層之上部以顯露出該複數條導線之每一條535268 六、申請專利範圍 之頂端部,且^該複數條導線相互間之複數個部分移除 該樹脂層,同%使該樹脂層薄薄地存留於該複數條 每一條之周圍,作為一上部塗覆樹脂層; ^,、 塗佈含有樹脂的助熔劑於該半導體晶片之整個面積 上; 、 經由該含有樹脂的助熔劑配置複數 導線之該複數個頂端部上,且藉由一二这,, 複數個焊球㈣複數條導線;猎由^熔㈣製程結合該 時使ΐ=ϊ:条導線間之複數個部分移除該樹脂層,同 ^使=月曰層存留於該複數條導線之每一條之下周圍,作 部塗覆樹脂層厚的下部塗覆樹脂層,藉以形成 1:if上部塗覆樹脂層與該下部塗覆樹脂層之間; 猎以藉由該重炼流你盤由分《人 溶劑成分消失,且該含有樹r的=有M脂的助熔劑之助 填滿從該複數個焊球=劑之殘留的樹脂成分 以捭%诗、—缸/ 卩塗覆樹脂層之複數個部份, 之4合=稷固焊球與該複數條導線及該上部塗覆樹脂層 中,第17項之半導體裝置之製造方法’其 條之頂總都μ对知層之上部以顯露出該複數條導線之每一 該樹r屏"i且更從該複數條導線晃間之複數個部分移除 每一條之3同日守使該樹脂層薄薄地存留於該複數條導線之 脂層# m1圍,作為一上部塗覆樹脂層的該步驟中,該樹 係精由使用切割機或雷射束而移除。I咖 第26頁 535268 六、申請專利範圍 19·如申請專利範圍第17項之半導體裝置之製造方法,其 中,在更從該複數條導線間之複數個部分移除該樹脂層, 同時使該樹脂層存留於該複數條導線之每一條之下周圍, 作為一較該上部塗覆樹脂層厚的下部塗覆樹脂層的步棘 中,該樹脂層係藉由使用切割機或雷射束而移除。第27頁
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001019298A JP3486872B2 (ja) | 2001-01-26 | 2001-01-26 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW535268B true TW535268B (en) | 2003-06-01 |
Family
ID=18885197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW91101118A TW535268B (en) | 2001-01-26 | 2002-01-23 | Semiconductor device having reliable coupling with mounting substrate |
Country Status (5)
Country | Link |
---|---|
US (1) | US6690090B2 (zh) |
JP (1) | JP3486872B2 (zh) |
KR (1) | KR20020063120A (zh) |
CN (1) | CN1367533A (zh) |
TW (1) | TW535268B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10045534B4 (de) * | 2000-09-13 | 2005-03-17 | Infineon Technologies Ag | Elektronisches Bauteil mit Außenanschlußelementen ausgebildet als Kapillarelement, Verfahren zur Herstellung und Anordnung |
US7285867B2 (en) * | 2002-11-08 | 2007-10-23 | Casio Computer Co., Ltd. | Wiring structure on semiconductor substrate and method of fabricating the same |
KR100625021B1 (ko) * | 2004-08-30 | 2006-09-20 | 김봉환 | 가변형 열교환 환기장치 |
JP4619223B2 (ja) * | 2004-12-16 | 2011-01-26 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
WO2007080863A1 (ja) * | 2006-01-16 | 2007-07-19 | Nec Corporation | 半導体装置、該半導体装置を実装するプリント配線基板、及びそれらの接続構造 |
US9443797B2 (en) | 2012-09-14 | 2016-09-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device having wire studs as vertical interconnect in FO-WLP |
US10192796B2 (en) | 2012-09-14 | 2019-01-29 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP |
US9818734B2 (en) | 2012-09-14 | 2017-11-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over a temporary substrate |
US9893017B2 (en) | 2015-04-09 | 2018-02-13 | STATS ChipPAC Pte. Ltd. | Double-sided semiconductor package and dual-mold method of making same |
WO2018043129A1 (ja) * | 2016-08-31 | 2018-03-08 | 株式会社村田製作所 | 回路モジュールおよびその製造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917707A (en) * | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
US5476211A (en) * | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
US4926241A (en) * | 1988-02-19 | 1990-05-15 | Microelectronics And Computer Technology Corporation | Flip substrate for chip mount |
JPH0855856A (ja) | 1994-08-11 | 1996-02-27 | Shinko Electric Ind Co Ltd | 半導体装置とその製造方法 |
JPH08236575A (ja) | 1995-02-22 | 1996-09-13 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH09260428A (ja) | 1996-03-19 | 1997-10-03 | Toshiba Corp | 半導体装置及びその実装方法 |
JP3644189B2 (ja) | 1997-04-25 | 2005-04-27 | ソニー株式会社 | バンプ構造及びその製造方法 |
KR100244504B1 (ko) | 1997-11-15 | 2000-02-01 | 김영환 | 칩 사이즈 반도체 패키지의 제조방법 |
JP3481117B2 (ja) | 1998-02-25 | 2003-12-22 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP3570229B2 (ja) | 1998-07-13 | 2004-09-29 | 松下電器産業株式会社 | 半田接合方法および半田接合用の熱硬化性樹脂 |
JP3825181B2 (ja) * | 1998-08-20 | 2006-09-20 | 沖電気工業株式会社 | 半導体装置の製造方法及び半導体装置 |
JP2000311915A (ja) | 1998-10-14 | 2000-11-07 | Texas Instr Inc <Ti> | 半導体デバイス及びボンディング方法 |
JP2000200804A (ja) | 1998-10-30 | 2000-07-18 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2000243874A (ja) | 1999-02-23 | 2000-09-08 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP4809957B2 (ja) * | 1999-02-24 | 2011-11-09 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
US6495916B1 (en) * | 1999-04-06 | 2002-12-17 | Oki Electric Industry Co., Ltd. | Resin-encapsulated semiconductor device |
JP4526651B2 (ja) * | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2001332658A (ja) * | 2000-03-14 | 2001-11-30 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP4356183B2 (ja) | 2000-03-27 | 2009-11-04 | 住友ベークライト株式会社 | 半田接合用レジスト、半導体パッケージ及びその製造方法 |
-
2001
- 2001-01-26 JP JP2001019298A patent/JP3486872B2/ja not_active Expired - Fee Related
-
2002
- 2002-01-22 CN CN02102451A patent/CN1367533A/zh active Pending
- 2002-01-23 TW TW91101118A patent/TW535268B/zh active
- 2002-01-23 KR KR1020020003869A patent/KR20020063120A/ko not_active Application Discontinuation
- 2002-01-28 US US10/056,035 patent/US6690090B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2002222824A (ja) | 2002-08-09 |
US6690090B2 (en) | 2004-02-10 |
KR20020063120A (ko) | 2002-08-01 |
US20020100977A1 (en) | 2002-08-01 |
CN1367533A (zh) | 2002-09-04 |
JP3486872B2 (ja) | 2004-01-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6852564B2 (en) | Semiconductor device and method of fabricating the same | |
TWI328867B (en) | Integrated structure and method for fabricating the same | |
US6043564A (en) | Semiconductor device having ball-bonded pads | |
TWI323931B (en) | Taped lead frames and methods of making and using the same in semiconductor packaging | |
US8133761B2 (en) | Packaged system of semiconductor chips having a semiconductor interposer | |
TWI459505B (zh) | 電互連結構及方法 | |
JP4699353B2 (ja) | 代替のflmpパッケージ設計およびそのパッケージ製造方法 | |
JP5497392B2 (ja) | 半導体装置 | |
CN109637985B (zh) | 一种芯片扇出的封装结构及其制造方法 | |
TWI254425B (en) | Chip package structure, chip packaging process, chip carrier and manufacturing process thereof | |
JPH02123685A (ja) | 金を含むワイヤを半田に接着する方法 | |
TW200845351A (en) | Semiconductor device, leadframe and manufacturing method of semiconductor device | |
TW200416787A (en) | Semiconductor stacked multi-package module having inverted second package | |
DE102013104455A1 (de) | PoP-Gerät | |
US8802554B2 (en) | Patterns of passivation material on bond pads and methods of manufacture thereof | |
EP0460131A1 (en) | Testable ribbon bonding method and wedge bonding tool for microcircuit device fabrication | |
TW535268B (en) | Semiconductor device having reliable coupling with mounting substrate | |
CN102651356B (zh) | 在迹线上凸块结构中延伸的金属迹线 | |
JP2011035302A (ja) | 半導体装置の製造方法 | |
JP2009218576A (ja) | Mcmパッケージ | |
JP2838703B2 (ja) | 半導体パッケージの製造方法 | |
US10872845B2 (en) | Process for manufacturing a flip chip semiconductor package and a corresponding flip chip package | |
US20030099767A1 (en) | Bumping process for chip scale packaging | |
JPS62281435A (ja) | 半導体装置 | |
US20030071354A1 (en) | Wafer level chip scale package and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent |