CN1099710C - 半导体器件 - Google Patents
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Abstract
公开了一种尺寸减小并具有高抗翘曲性能结构的半导体器件。密封树脂由转移模塑工艺形成,以覆盖包括多个焊点电极的整个半导体芯片,多个连接凸点,包括多个芯片连接触点的连线板的上表面,连线板的侧表面,以及连线板的下表面上环绕外电极区所在的区域的外围区。连线板与半导体芯片在平面结构上基本上是在空间上共同扩张的。多个外电极区所在的区较之多个芯片连接触点所在的区域要小。
Description
本发明涉及安装有半导体芯片的半导体器件。
图6所示是一种常规的BGA(网格焊球阵列)型半导体器件。如图所示,在半导体芯片1的下表面上形成有多个焊点电极2。多个连接凸点5分别直接与相应的焊点电极2相连接。
在连线板23的上表面上形成有多个芯片连接触点(pattern)4,而在其下表面上形成有多个外电极区30。每个外电极区30包含一个基板连接触点27和一个连接端子28。基板连接触点27直接在连线板下表面上形成,而连接端子则分别在基板连接触点27上形成。芯片连接触点4与相应的外电极区30(基板连接触点27)电气连接,并且分别直接与连接凸点5相应各点连接。
密封树脂26用来覆盖包括焊点电极2的半导体芯片1的下表面,多个连接凸点5,以及包括芯片连接触点4的连线板23的上表面。
在平面结构上连线板23的面积比半导体芯片1的面积大。形成外电极区30的区域A1比形成芯片连接触点4的区域A2的面积大。
在上述的常规半导体器件中,外电极区30所在的区域A1较之芯片连接触点4所在的区域A2为大,于是有的外部电极区30所在的那部分区域的对应区域中没有芯片连接触点4形成。因此,从平面结构来看,连线板23的面积比半导体芯片1的面积大。
结果是面积比半导体芯片1要大的连线板23的平面结构妨碍器件尺寸的减小并易于导致半导体芯片1及连线板23的结合面发生翘曲而影响器件在安装基板上的安装。
因此本发明的一个目的就是提供一种具有高抗翘曲结构的半导体器件并且减小半导体器件的尺寸。
根据本发明,一种半导体器件,包括:具有第一和第二主表面的半导体芯片,它包括在其上的第一或第二主表面上形成的多个焊点电极;具有第一和第二主表面的连线板,半导体芯片叠放于此连线板的第一主表面之上,该连线板包括在它的第一主表面上形成的多个芯片连接触点和在它的第二主表面上形成的多个外电极区,分别电气连接于相应的多个外电极区和相应的多个焊点电极;以及树脂,它用来覆盖整个包括多个焊点电极的半导体芯片和包括多个芯片连接触点的连线板的第一主表面,其中多个外电极区所在的区域较之有多个芯片连接触点形成的区域为小。
根据本发明的第一点,最好是这多个焊点电极形成于半导体芯片的第二主表面之上,并且该半导体器件进一步包括多个分别直接连接于相应多个焊点电极的连接电极,该多个芯片连接触点分别直接连接于多个连接电极的相应各点,而该树脂用来覆盖包括该多个连接电极的连线板的第一主表面。
根据本发明的第二点,最好是这多个焊点电极形成于半导体芯片的第一主表面之上;并且该多个芯片连接触点环绕该半导体芯片并分别通过金属线连接于相应的多个焊点电极。
根据本发明的第三点,最好树脂是通过转移模塑工艺(transfermold process)形成。
根据本发明的第四点,最好是连线板一端与形成多个芯片连接触点的区域间的距离小于连线板该端与形成有多个外电极区的区域间的距离;并且树脂还覆盖连线板的侧表面及此连线板第二主表面的一部分,但形成多个外电极区的部分除外。
如上所述,根据本发明第一点的半导体器件,连线板与半导体芯片在平面结构上基本上是在空间上共同扩张(coextensive)的,并且多个外电极区所在的区域较之多个芯片连接触点所在的区域为小。这就可以对应于半导体芯片的尺寸来减小器件的尺寸。
本发明第一点的半导体器件所用的树脂是用来覆盖包括多个芯片连接触点的连线板的整个第一主表面,从而可有效地消除半导体芯片与连线板通过多个焊点电极、多个连接电极及多个芯片连接触点的结合面的翘曲。
加之,因为连线板在平面结构上基本上与半导体芯片是在空间上共同扩张的,结合面的翘曲在连线板的端部并未扩大。
因为多个外电极区所在的区域较之多个芯片连接触点所在的区域为小,可以毫无阻碍地形成在平面结构上基本上与半导体芯片在空间上共同扩张的连线板。
根据本发明第二点的半导体器件,采用树脂来覆盖包括多个芯片连接触点的连线板的整个第一主表面,可有效地消除半导体器件和连线板的结合面的翘曲。
根据本发明第三点的半导体器件,转移模塑树脂具有强大的消除结合面的翘曲的特性。
根据本发明第一点及第三点,如果多个芯片连接触点(焊点电极及连接电极)在空间上相隔很近,则转移模塑树脂可以精确地填充半导体芯片与连线板的结合部。
根据本发明第四点的半导体器件,使用树脂也可以覆盖连线板的侧表面和连线板的第二主表面的一部分,但形成多个外电极区的区域除外。这可以提供更高的树脂和连线板的结合强度,更有效地消除结合面的翘曲并提高器件的可靠性。
本发明的这些及其他的目的、特点、方面及优点由下面的结合附图对本发明的详细叙述会看得更加明显。
图1是根据本发明第一最佳实施例的半导体器件的剖视图;
图2是根据本发明第二最佳实施例的半导体器件的剖视图;
图3及图4是本发明第一最佳实施例的变例的剖视图;
图5是本发明第二最佳实施例的一种变例的剖视图;并且
图6是现有技术的半导体器件的剖视图。
<第一最佳实施例>
图1是根据本发明第一最佳实施例的半导体器件的剖视图。如图所示,在半导体芯片1的下表面上形成有多个焊点电极2。多个连接凸点5分别直接与多个焊点电极2的相应电极相连。在连线板3的上表面上形成有多个芯片连接触点4,而在其下表面上有多个外电极区20形成。每个外电极区20包含一个基板连接触点7和一个基本上是球形的连接端子8。基板连接触点7直接在连线板3的下表面上形成,而连接端子8分别在基板连接触点7上形成。芯片连接触点4电气连接于多个外电极区20的相应各点(基板连接触点7),并且分别直接连接于多个连接凸点5的相应各点。连线板3可以但不限于包括玻璃纤维增强环氧树脂基板,聚酰亚胺带和诸如此类。
密封树脂6用来覆盖整个包括多个焊点电极2的半导体芯片1,多个连接凸点5,包括多个芯片连接触点4的连线板3的上表面,连线板3的侧表面,以及连线板3下表面上环绕外电极区20所在区域A1的外围区14。
密封树脂6通过转移模塑工艺形成。在连线板3的下表面上形成树脂的方法公开于,例如,日本特许公开6-209054(1994)中。
连线板3在平面结构上与半导体芯片1基本上是在空间上共同扩张的。多个外电极区20所在的区域A1较之多个芯片连接触点4所在的区域A2要小。
具有这种第一最佳实施例结构的半导体器件放置于图中未示出的安装基板上,然后加热使外电极区20的连接端子8与安装基板上多个连接端子的相应端子熔合而实现连接。这样就可以将半导体器件安装于安装基板上。
在第一最佳实施例的半导体器件中,连线板3在平面结构上基本与半导体芯片1在空间上共同扩张,并且多个外电极区20所在的区域A1较之多个芯片连接触点4所在的区域A2要小。区域A1能纳入区域A2的相应区域之内。于是,这一半导体器件的尺寸就可以相应于半导体芯片1的尺寸而减小。
外电极区20(基板连接触点7)所在区域A1的减小可缩短基板连接触点7的连线总长,从而减小连线产生的电感。这就可以使半导体器件的电特性获得改善。
此外,因为多个外电极区20所在的区域A1较之多个芯片连接触点4所在的区域A2要小,可以毫无阻碍地形成在平面结构上基本上与半导体芯片1在空间上共同扩张的连线板3。
第一最佳实施例半导体器件的密封树脂6是用来覆盖包括芯片连接触点4的连线板3的整个上表面,从而可以有效地消除半导体芯片1和连线板3通过多个焊点电极2、多个连接凸点5及多个芯片连接触点4的结合面的翘曲。
在连线板3的端部,结合面的翘曲并未扩大,因为连线板3与半导体芯片1在平面结构上基本上是在空间上共同扩张的。
第一最佳实施例中半导体器件的密封树脂6也存在于连线板3的侧表面及连线板3下表面上环绕有外电极区20存在的区域A1的外围区14。还可以提供更高的密封树脂6与连线板3的结合强度,更有效地消除结合面的翘曲,并进一步提高器件的可靠性。
第一最佳实施例的半导体器件用的密封树脂6是通过转移模塑成形,具有更强的消除结合面翘曲的性能。
如果多个芯片连接触点4(焊点电极2和连接凸点5)在空间上相隔很近,则通过转移模塑过程形成密封树脂6时可以使之精确地填充半导体芯片1与连线板3的结合部。
<第二最佳实施例>
图2为根据本发明第二最佳实施例的半导体器件的剖视图。如图所示,半导体芯片11放置于连线板3上并通过胶合层10与之结合。多个焊点电极12形成于半导体芯片11的上表面上。
在连线板3的上表面围绕半导体芯片11形成多个芯片连接触点4,而在其下表面上通过与第一最佳实施例相同的方式形成多个外电极区20。该多个芯片连接触点4电气连接于外电极区20(基板连接触点7)的相应各点,并利用细金属丝15分别与多个焊点电极12的相应各点键合。连线板可以但不限于包括玻璃纤维增强环氧树脂基板,聚酰亚胺带和诸如此类。
密封树脂16用来覆盖包括多个焊点电极12的整个半导体芯片11,包括多个芯片连接触点4的连线板3的上表面,连线板3的侧表面,以及连线板3下表面上环绕外电极区20所在区域A1的外围区14。密封树脂16采用与第一最佳实施例相同的方式由转移模塑过程形成。
多个外电极区20所在的区域A1较之包括半导体芯片11的多个芯片连接触点4所在的区域A2要小。
具有这种第二最佳实施例结构的半导体器件放置于图中未示出的安装基板上,然后加热使外电极区20的连接端子8与安装基板上多个连接端子的相应端子熔合而实现连接。这样就可以将半导体器件安装于安装基板上。
在第二最佳实施例的半导体器件中,多个外电极区20所在的区域A1较之包括半导体芯片11的多个芯片连接触点4所在的区域A2要小。区域A1能纳入区域A2的相应区域之内。于是,这一半导体器件的尺寸可以相应于芯片连接触点4所在的区域A1所确定的尺寸而减小。
外电极区20(基板连接触点7)所在区域A1的减小可缩短基板连接触点7的连线总长,从而减小连线产生的电感。这就可以使半导体器件的电特性获得改善。
第二最佳实施例中半导体器件的密封树脂16是用来覆盖包括芯片连接触点4的连线板3的整个上表面,从而可有效地消除半导体芯片11和连线板3通过胶合层10的结合面的翘曲。
第二最佳实施例中半导体器件的密封树脂16也存在于连线板3的侧表面及连线板3下表面上环绕有外电极区20存在的区域A1的外围区14。这可以提供更高的密封树脂16与连线板3的结合强度,更有效地消除结合面的翘曲,并进一步提高器件的可靠性。
第二最佳实施例的半导体器件采用的密封树脂16是通过转移模塑成形,具有更强的消除结合面翘曲的性能。
<变例>
第一最佳实施例的半导体器件中外电极区20都各包括基板连接触点7和连接端子8。如图3所示,各外电极区20可以包括一枝状连接销9,并且可以采用通常的引线或细结合件。外电极区20的材料及结构没有限制。这一点也适用于第二最佳实施例的半导体器件的外电极区20。
第一最佳实施例中的密封树脂6和第二最佳实施例中的密封树脂16由连线板3的侧表面扩展到其下表面的一部分上。参考图4与图5可见密封树脂6及密封树脂16可以只在连线板3的上表面上形成。但是在图4与图5的结构中密封树脂6(16)与连线板3的结合强度比第一及第二最佳实施例中的半导体器件中的低。
虽然本发明已得到详细介绍,但上面的描述在各方面均是示例性质而非限制性质。不言而喻,在不脱离本发明的范围的条件下仍然可以设计出大量的改型与变例。
Claims (12)
1.一种半导体器件,其构成包括:
具有第一和第二主表面的半导体芯片,上述半导体芯片包括多个位于其第一或第二主表面上的焊点电极;
具有第一和第二主表面的连线板,上述半导体芯片叠置于上述连线板的第一主表面之上,上述连线板包括多个位于其第一主表面之上的芯片连接触点,并且有多个外电极区位于其第二主表面之上,上述多个芯片连接触点分别电气连接于上述多个外电极区的相应各点,并且分别电气连接于上述多个焊点电极的相应各点;以及
用来覆盖包括上述多个焊点电极的整个半导体芯片,和包括上述多个芯片连接触点的上述连线板的第一主表面的树脂,
其中上述多个外电极区所在的区域较之上述多个芯片连接触点所在的区域为小。
2.如权利要求1中的半导体器件,其特征在于:
上述多个焊点电极位于上述半导体芯片的第二主表面上,
上述半导体器件还包括:
分别直接连接于上述多个焊点电极相应各点的多个连接电极,
分别直接连接于上述多个连接电极相应各点的芯片连接触点,
上述树脂用来覆盖包括上述多个连接电极的上述连线板的第一主表面。
3.如权利要求1中的半导体器件,其特征在于:
上述多个焊点电极位于上述半导体芯片的第一主表面上,以及
上述多个芯片连接触点围绕上述半导体芯片并通过金属线分别连接于上述多个焊点电极的相应各点。
4.如权利要求3中的半导体器件,其特征在于:
上述半导体芯片位于并粘合于上述连线板上。
5.如权利要求2中的半导体器件,其特征在于:
上述树脂由转移模塑工艺形成。
6.如权利要求5中的半导体器件,其特征在于:
上述连线板一端与上述多个芯片连接触点所在的区域的距离较之上述连线板该端与上述多个外电极区所在的区域的距离为短,以及
上述树脂也覆盖上述连线板的侧表面和上述连线板中不包括多个外电极区所在部分的第二主表面的一部分。
7.如权利要求6中的半导体器件,其特征在于:
上述多个外电极区的每一个都包括:
直接与上述连线板的第二主表面连接的导电触点;及
直接与上述导电触点连接的基本上是球形的外电极。
8.如权利要求6中的半导体器件,其特征在于:
上述多个外电极区的每一个都包括枝状连接销。
9.如权利要求3中的半导体器件,其特征在于:
上述树脂为通过转移模塑工艺形成。
10.如权利要求9中的半导体器件,其特征在于:
上述连线板一端与上述多个芯片连接触点所在的区域的距离较之上述连线板该端与上述多个外电极区所在的区域的距离为短,并且
上述树脂也覆盖上述连线板的侧表面和上述连线板的不包括多个外电极区所在部分的第二主表面的一部分。
11.如权利要求10中的半导体器件,其特征在于:
上述多个外电极区的构成包括:
与上述连线板的第二主表面直接连接的导电触点;以及
直接与上述导电触点连接的基本上是球形的外电极。
12.如权利要求10中的半导体器件,其特征在于:
上述多个外电极区的每一个都包括枝状连接销。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP072043/96 | 1996-03-27 | ||
JP072043/1996 | 1996-03-27 | ||
JP7204396A JPH09260436A (ja) | 1996-03-27 | 1996-03-27 | 半導体装置 |
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CN1160933A CN1160933A (zh) | 1997-10-01 |
CN1099710C true CN1099710C (zh) | 2003-01-22 |
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CN96119763A Expired - Lifetime CN1099710C (zh) | 1996-03-27 | 1996-12-10 | 半导体器件 |
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US (1) | US5708304A (zh) |
JP (1) | JPH09260436A (zh) |
KR (1) | KR100194747B1 (zh) |
CN (1) | CN1099710C (zh) |
DE (1) | DE19651122C2 (zh) |
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US6407461B1 (en) * | 1997-06-27 | 2002-06-18 | International Business Machines Corporation | Injection molded integrated circuit chip assembly |
US5888850A (en) * | 1997-09-29 | 1999-03-30 | International Business Machines Corporation | Method for providing a protective coating and electronic package utilizing same |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
US6495083B2 (en) * | 1997-10-29 | 2002-12-17 | Hestia Technologies, Inc. | Method of underfilling an integrated circuit chip |
US6324069B1 (en) | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
US6038136A (en) * | 1997-10-29 | 2000-03-14 | Hestia Technologies, Inc. | Chip package with molded underfill |
KR19990040758A (ko) * | 1997-11-19 | 1999-06-05 | 김영환 | 비지에이 패키지 및 그 제조 방법 |
SG71734A1 (en) * | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
US5998876A (en) * | 1997-12-30 | 1999-12-07 | International Business Machines Corporation | Reworkable thermoplastic hyper-branched encapsulant |
US6303408B1 (en) | 1998-02-03 | 2001-10-16 | Tessera, Inc. | Microelectronic assemblies with composite conductive elements |
US6291899B1 (en) * | 1999-02-16 | 2001-09-18 | Micron Technology, Inc. | Method and apparatus for reducing BGA warpage caused by encapsulation |
US6303992B1 (en) * | 1999-07-06 | 2001-10-16 | Visteon Global Technologies, Inc. | Interposer for mounting semiconductor dice on substrates |
US6329220B1 (en) * | 1999-11-23 | 2001-12-11 | Micron Technology, Inc. | Packages for semiconductor die |
US6949822B2 (en) * | 2000-03-17 | 2005-09-27 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
US6559537B1 (en) * | 2000-08-31 | 2003-05-06 | Micron Technology, Inc. | Ball grid array packages with thermally conductive containers |
JP3786103B2 (ja) * | 2003-05-02 | 2006-06-14 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
KR100585163B1 (ko) * | 2004-11-27 | 2006-06-01 | 삼성전자주식회사 | 메모리 카드 및 그 제조방법 |
JP2009099838A (ja) * | 2007-10-18 | 2009-05-07 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US20120217653A1 (en) * | 2009-11-10 | 2012-08-30 | Nec Corporation | Semiconductor device and noise suppressing method |
JP2011176011A (ja) * | 2010-02-23 | 2011-09-08 | Panasonic Corp | 半導体集積回路装置 |
CN102520340B (zh) * | 2012-01-06 | 2016-08-03 | 日月光半导体制造股份有限公司 | 具有测试结构的半导体封装元件及其测试方法 |
US20130341807A1 (en) * | 2012-06-25 | 2013-12-26 | Po-Chun Lin | Semiconductor package structure |
US10468307B2 (en) * | 2017-09-18 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
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US4202007A (en) * | 1978-06-23 | 1980-05-06 | International Business Machines Corporation | Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers |
FR2498814B1 (fr) * | 1981-01-26 | 1985-12-20 | Burroughs Corp | Boitier pour circuit integre, moyen pour le montage et procede de fabrication |
FR2521350B1 (fr) * | 1982-02-05 | 1986-01-24 | Hitachi Ltd | Boitier porteur de puce semi-conductrice |
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-
1996
- 1996-03-27 JP JP7204396A patent/JPH09260436A/ja active Pending
- 1996-09-02 KR KR1019960037793A patent/KR100194747B1/ko not_active IP Right Cessation
- 1996-09-05 US US08/708,615 patent/US5708304A/en not_active Expired - Lifetime
- 1996-12-09 DE DE1996151122 patent/DE19651122C2/de not_active Expired - Lifetime
- 1996-12-10 CN CN96119763A patent/CN1099710C/zh not_active Expired - Lifetime
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US5708304A (en) | 1998-01-13 |
DE19651122A1 (de) | 1997-10-02 |
JPH09260436A (ja) | 1997-10-03 |
CN1160933A (zh) | 1997-10-01 |
KR100194747B1 (ko) | 1999-06-15 |
DE19651122C2 (de) | 2001-05-17 |
KR970067799A (ko) | 1997-10-13 |
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