CN1153579A - 关于表面安装的小型半导体器件 - Google Patents
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Abstract
本发明涉及用带槽形(7)表面的衬底载体(1)进行表面安装的半导体器件，在槽壁(8)上设有导电的布线(9)，导电布线(9)延伸到衬底载体(1)的表面，形成器件的连接导线，其在槽(7)中装有半导体元件(10)，半导体元件(10)的主表面和(11)和壁(8)相互平行，半导体元件(10)和壁(8)上的导电布线(9)相互电连接，用保护材料填充槽(7)。按照本发明，衬底载体1设有侧壁(15)，其和位于半导体元件(10)两侧的槽(7)的相对两壁(8)相互连接。在制造比较小的半导体器件时和以后很少出现废品。
Description
本发明涉及利用衬底载体进行表面安装的半导体器件，该载体具有槽形表面，在槽壁上设置导电的布线，导电布线延伸到衬底载体的表面，形成该器件的连接导线，该器件在与所述槽壁平行的其主表面上设有半导体元件，半导体元件和侧壁导电布线相互电接触，并且用保护材料填充该槽。本发明还涉及适用制造半导体器件的载体杆。
美国专利5,198,886在开篇中叙述了上述那种器件。这种公知的器件是适于表面安装、即，利用衬底载体上面的导电布线实现半导体器件和例如印刷电路板上导电布线之间的连接。对于公知的半导体器件，把半导体元件夹持在楔形槽中。
虽然，这种公知的器件在实际中令人满意，但是对于很小尺寸且仍要进一步小型化的应用，出现了问题，包括在制造器件期间和以后，产生了废品器件。
本发明的目的尤其是提供一种半导体器件，其在涉及小尺寸的制造期间和以后很少出现废品。
按照本发明，为实现上述目的，该器件的特征是，衬底载体提供有一个侧壁，其连接槽的相对的各壁。
因此，在制造小型半导体器件期间和以后，几乎不出现废品。
本发明是根据下述的理解。在公知的器件中利用连续的槽，即实际上把衬底载体等分成两部分，在槽底部下面，在所述两部分之间，衬底载体材料形成机械连接。在制造公知器件期间适当地用夹持配合把半导体元件夹在槽中。因此，把材料机械地装入槽底下面。据发现，在制造小尺寸公知器件期间及以后产生废品、这是因为底部下面的材料不够坚固。按照本发明提供的措施是在衬底载体的两部分之间提供附加的机械连接。除在槽底部下面的材料外，侧壁还在两衬底载体之间提供机械连接，则当因为半导体期间高度小因而槽下部材料数量小时在半导体器件尺寸小的情况下，不产生废品。利用位于半导体元件每个侧面上的各侧壁，借助于两部分和各侧壁之间产生的力，导致于关闭系统。上述由于各力的关闭系统，能够大量地吸收制造期间和以后产生的力。
当槽没有底部时产生另外一种优点。器件的尺寸可以选择得更小。由两个侧壁和两个衬底的力的关闭系统，保证有足够的机械强度，而不管在槽底部下面缺乏材料。
可以把两个衬底部分之间的侧壁作为衬底载体的分离部件。最好，按照本发明的器件的特征是，侧壁和衬底载体是一个整体。这是指各侧壁由与衬底载体的相同材料构成。在制造衬底载体时形成侧壁。侧壁的成本保持很有限。
最好，由合成树脂或者陶瓷材料制造衬底载体。可能用喷射模制或挤压工艺的简单方法来制造带有侧壁的衬底载体。
本发明还涉及适用于制造关于表面安装的半导体器件的载体杆，其具有槽形表面，在槽的侧壁上设有导电布线，该导电布线连续地延伸到载体杆的表面上。美国专利US.5,198,866表示怎样把载体杆用于制造半导体元件之中。适当地用夹持配合把半导体元件夹入到槽中，使半导体元件和各侧壁上的导电布线相互接触。例如，通过焊接工艺，依次固定各半导体元件。在槽中依次用保护材料覆盖各半导体元件。利用锯断或截断方法，把载体杆分成单独的半导体器件。按照本发明，利用侧壁把载体杆中的槽分成相互隔离的分离室。由于利用上述载体杆，在把半导体元件插入槽中时，载体杆具有较大的强度，当载体杆断裂或夹持力不充分时，很少产生废品。
下面参照附图通过实施例，详细地说明本发明。
图1和图2表示按照本发明的器件实施例，图1是剖视图。
图3表示按照本发明制造半导体器件时利用的一部分载体杆。
各图完全是图解的，没有画出刻度。通常，在各图中的相应部分，用相同标号表示。
图1和图2表示利用带有表面的衬底载体1进行表面安装的半导体器件的剖视图和透视图。该表面包括上表面3、下表面4、侧表面5。由带有侧壁8的楔形槽7提供给上表面3，其具有大约13°的角。侧壁8上面的导电布线延伸到表面上，在这种情况下延伸到衬底载体1的上表面3，下表面4和侧表面5上。导电布线9在上表面3，下表面4、侧表面5上形成器件的连接导线。在安装时，例如用下表面4把器件安装在印刷电路板上，通过焊接把导电布线9连接到印刷电路板的导电布线上。显然，可以选择地由侧表面5或者上表面3安装半导体器件。该器件装有半导体元件10，其中，与侧壁8平行的半导体元件的主表面11和槽7相互接触。应该了解，该半导体元件的主表面是指用于制造半导体元件的半导体晶片的主表面。给出这样一个位置，在片子上的半导体元件上面可能设置接触点12，其和侧壁8的导电布线相连接。换句话说，半导体元件10的非主表面相应于断裂半导体片产生的断开的或锯断的表面。在这种情况，利用变形的接触体12，以通过焊接由公知方法制造的所谓块形连接形式，使半导体元件10和侧壁8上面的导电布线9相互电接触。利用诸如环氧树脂漆或玻璃层(未表示)的保护层填充槽7。
按照本发明，在半导体元件10两侧，衬底载体1设有侧壁15和15′，这些侧壁和槽7的相对表面8相互连接。在衬底载体1的两等分部分17和17′以及侧壁15和15′之间产生力关闭系统。上述由力产生的关闭系统可能吸收在制造期间的制造之后产生的力。该例中的槽7没有底。由力产生的关闭系统，具有两侧壁15和15′，两衬底等分部分17和17′，其确保足够大的机械强度，尽管槽7底部下面缺乏材料。可以选择很小的器件尺寸。例如，图1和图2所示的半导体器件具有L×W×H(长×宽×高)为0.6×1.0×0.7的尺寸(在SMD技术中通称为0402)。
利用与美国专利US 5,198,886所述的类似的方法制造半导体器件。本方法利用带有槽7的衬底载体1，在该槽侧壁8上面设有导电布线9(见图3)。这些导电布线包括例如焊接层。半导体元件10在第1主表面上设有焊接层，在另外主表面上设有能变形的金导电体12，接着把半导体元件适当地夹入槽7中，使半导体元件10和侧壁8上面的导电布线9相互电接触。例如，由可形变的导电层12基本上提供夹紧的力。然后通过焊接很牢固地固定半导体元件10。再用公知环氧树脂漆或玻璃悬架覆盖槽7中的半导体元件10，以便保护半导体元件10，使其不受诸如湿气的环境影响。利用如锯割或折断方法把衬底杆1断裂。在美国专利US 5,198,886可能找到关于半导体器件和制造方法的进一步细节。在把半导体元件10装入槽7之前，在衬底杆1上面设置侧壁15。可以在载体杆1上面设置侧壁15作为附加部件。图3表示载体杆的优良实施例，在此处，载体杆1整体地包含侧壁15。载体杆1包含槽7，其被侧壁15分成多个隔离室。侧壁15由与载体杆1相同的材料组成。最好，载体杆1由诸如聚醚嗍(PES)，聚醚酰亚胺(PEI)，碳化硅(SiC)，氮化硅，或氧化铝之类合成树脂或陶瓷材料构成。可能利用喷射模制或挤压工艺，在陶瓷材料情况可能接着进行烧结工艺，用简单的方法，制造带有侧壁的衬底载体。在制造载体杆1时，同时形成侧壁15。制造侧壁15的成本受到一定限制。
本发明不限于上述的实施例。在图1和图2所示的实施例中，该槽没有底。显然，槽7可在其底部设有材料。半导体器件将有稍大的尺寸，例如，覆盖槽7中的半导体元件变为简单，因为只在槽7的上部3需要进行覆盖。在本实施例，侧壁8上面的导电布线9，首先延伸到上表面3，然后到表面5，最后到下表面4，在另一个相对的侧壁5上面的导电布线9，首先延伸到下表面4，然后再到侧表面5。对于下述两种情况可能是相等的，即槽7中侧壁8上面的导电的布线9，首先延伸到衬底载体1的上面3，然后到侧壁5，再到下面4，或者相反，首先延伸到衬底载体1的下面4，然后到侧面5，再到上面3。也有可能使导电布线9只延伸到上表面3或者再到下表面4。这样导电布线9不需覆盖侧表面5。当用导电布线9覆盖衬底载体1的上表面或下表面部分3，4时，则和印刷电路板上的导电布线充分电接触。利用导线焊接制造本实施例的接触层12。可能选择地利用其它技术，例如，电镀，或电化学淀积层，再用光刻工艺对这些层构图，来制造接触层12。在侧7中的半导体元件10可能包括诸如二极管，二极管或者IC的几个半导体元件10。在这种情况，侧壁8包括许多适合于特殊半导体元件10的导电布线9。这样，例如，在有一个二极管的情况，在每个壁8上面有一个导电布线，其实在一个壁8上面有一个导电布线是必要的，在晶体管的情况，需要在另一壁8上面有2个导电布线。半导体器件可以包括几个半导体元件10。用那种方法制造上述器件很简单，在断开装有半导体元件10的载体杆时，不把这个载体杆再细分成只包含一个半导体元件10的半导体器件，而是包含2个或多个半导体元件10的半导体器件。
Claims (5)
1、一种表面安装的半导体器件，具有带槽表面的衬底载体，在槽壁上设有导电布线，导电布线延伸到衬底载体的表面，形成器件的连接导线，该器件装有半导体元件，其主表面和所述槽壁相互平行，半导体元件和侧壁上的导电布线相互电解触，并用保护材料填充槽，其特征是，提供具有侧壁的衬底载体，该侧壁和槽的相对壁相互连接。
2、按照权利要求1的半导体器件，其特征在于，槽没有底。
3、按照前述权利要求中的任何一个权利要求的半导体器件，其特征在于，侧壁和衬底载体组成一个整体。
4、按照前述权利要求中的任何一个权利要求的半导体器件，其特征在于，由陶瓷材料或合成树脂制造衬底载体。
5、一种适用于制造表面安装的半导体器件的载体杆，其具有带槽的表面，在槽壁上设有导电的布线，该导电布线延伸到载体杆的表面，其特征是，把载体杆的槽由侧壁再分成相互隔离的隔离室。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP95201203.7 | 1995-05-10 | ||
| EP95201203 | 1995-05-10 |
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| Publication Number | Publication Date |
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| CN1153579A true CN1153579A (zh) | 1997-07-02 |
| CN1097852C CN1097852C (zh) | 2003-01-01 |
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| CN96190469A Expired - Fee Related CN1097852C (zh) | 1995-05-10 | 1996-05-07 | 表面安装的小型半导体器件和适合于其制造的载体杆 |
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| US (1) | US5703401A (zh) |
| EP (1) | EP0775369B1 (zh) |
| JP (1) | JPH10503330A (zh) |
| KR (1) | KR100372136B1 (zh) |
| CN (1) | CN1097852C (zh) |
| DE (1) | DE69615792T2 (zh) |
| MY (1) | MY112050A (zh) |
| WO (1) | WO1996036075A2 (zh) |
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| US7675145B2 (en) * | 2006-03-28 | 2010-03-09 | Cree Hong Kong Limited | Apparatus, system and method for use in mounting electronic elements |
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| US7635915B2 (en) * | 2006-04-26 | 2009-12-22 | Cree Hong Kong Limited | Apparatus and method for use in mounting electronic elements |
| US8735920B2 (en) * | 2006-07-31 | 2014-05-27 | Cree, Inc. | Light emitting diode package with optical element |
| US8367945B2 (en) * | 2006-08-16 | 2013-02-05 | Cree Huizhou Opto Limited | Apparatus, system and method for use in mounting electronic elements |
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| USD615504S1 (en) | 2007-10-31 | 2010-05-11 | Cree, Inc. | Emitter package |
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| US8791471B2 (en) | 2008-11-07 | 2014-07-29 | Cree Hong Kong Limited | Multi-chip light emitting diode modules |
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Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4147889A (en) * | 1978-02-28 | 1979-04-03 | Amp Incorporated | Chip carrier |
| EP0139029A1 (en) * | 1983-10-19 | 1985-05-02 | Olin Corporation | Improved semiconductor package |
| GB8412674D0 (en) * | 1984-05-18 | 1984-06-27 | British Telecomm | Integrated circuit chip carrier |
| NL9000161A (nl) * | 1990-01-23 | 1991-08-16 | Koninkl Philips Electronics Nv | Halfgeleiderinrichting bevattende een drager en werkwijze voor het vervaardigen van de drager. |
| DE69507924T2 (de) * | 1994-04-15 | 1999-09-16 | Koninklijke Philips Electronics N.V., Eindhoven | Herstellungsverfahren für eine anordnung, wobei ein längsträger mit leiterbahnen zur elektrischen kontaktierung eines halbleiterelements versehen ist |
| KR100380701B1 (ko) * | 1994-07-26 | 2003-07-22 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 표면장착용반도체장치제조방법및표면장착용반도체장치 |
-
1996
- 1996-05-07 CN CN96190469A patent/CN1097852C/zh not_active Expired - Fee Related
- 1996-05-07 JP JP8533916A patent/JPH10503330A/ja active Pending
- 1996-05-07 EP EP96910163A patent/EP0775369B1/en not_active Expired - Lifetime
- 1996-05-07 DE DE69615792T patent/DE69615792T2/de not_active Expired - Fee Related
- 1996-05-07 KR KR1019970700110A patent/KR100372136B1/ko not_active IP Right Cessation
- 1996-05-07 WO PCT/IB1996/000411 patent/WO1996036075A2/en active IP Right Grant
- 1996-05-08 MY MYPI96001746A patent/MY112050A/en unknown
- 1996-05-10 US US08/644,093 patent/US5703401A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10503330A (ja) | 1998-03-24 |
| KR970705181A (ko) | 1997-09-06 |
| KR100372136B1 (ko) | 2003-03-15 |
| WO1996036075A2 (en) | 1996-11-14 |
| US5703401A (en) | 1997-12-30 |
| EP0775369A2 (en) | 1997-05-28 |
| MY112050A (en) | 2001-03-31 |
| DE69615792D1 (de) | 2001-11-15 |
| CN1097852C (zh) | 2003-01-01 |
| EP0775369B1 (en) | 2001-10-10 |
| DE69615792T2 (de) | 2002-05-23 |
| WO1996036075A3 (en) | 1997-02-13 |
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