CN101621046B - 使用具有空隙的穿通电极的半导体封装 - Google Patents

使用具有空隙的穿通电极的半导体封装 Download PDF

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CN101621046B
CN101621046B CN2009101523284A CN200910152328A CN101621046B CN 101621046 B CN101621046 B CN 101621046B CN 2009101523284 A CN2009101523284 A CN 2009101523284A CN 200910152328 A CN200910152328 A CN 200910152328A CN 101621046 B CN101621046 B CN 101621046B
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electrode
conductor
semiconductor chip
substrate
semiconductor
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CN101621046A (zh
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裵汉儁
李雄宣
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明提供一种使用具有空隙的穿通电极的半导体封装。该半导体封装包括具有多个接合衬垫的半导体芯片。穿通电极形成在半导体芯片中并电连接到接合衬垫。穿通电极包括多个导体和由导体定义的多个空隙。每个导体可以包括成组为具有多个空隙的球状的多个纳米线、成组为具有多个空隙的多边形形状的多个纳米线，或者导体可以包括多个微焊料球。穿通电极的空隙吸收在驱动半导体封装的过程中产生的热导致的应力。

Description

使用具有空隙的穿通电极的半导体封装
技术领域
本发明大体涉及一种半导体封装，更具体地，涉及一种使用穿通电极(through electrode)从而改善封装内电连接的可靠性的半导体封装。
背景技术
半导体工业的发展方向是能够以降低的成本制造具有改善的可靠性的轻质(light-weight)、高速、多功能的半导体产品。半导体封装技术被认为是实现半导体工业的目标的重要技术。
半导体封装技术保护半导体芯片(通过晶片装配工艺形成有电路部分)不受外部环境的影响；而且，半导体封装技术可以用于易于将半导体芯片安装到基板，从而保证半导体芯片的运行可靠性。半导体封装技术包括半导体芯片附着工艺、引线接合工艺、模制工艺(molding process)以及修切(trimming)和成型工艺。这些半导体封装工艺可以在芯片级或者晶片级进行。
近来，在半导体封装技术中已经采取努力来开发这样的技术，在该技术中堆叠至少两个半导体芯片或半导体封装从而获得半导体封装的高容量并改进安装效率且增加小型化。通过堆叠封装的使用，可以获得存储能力比使用半导体集成工艺能获得的存储能力更大的产品，以及具有较高安装面积使用效率的产品。
在堆叠封装中，使用金属线、块(bump)或穿通电极将半导体芯片或半导体封装电连接到基板并且将半导体芯片或半导体封装彼此电连接。在堆叠封装中使用穿通电极以形成电连接，使电学恶化(electrical degradation)的发生最小化。而且，将穿通电极用于电连接的堆叠封装可以实现增大的运行速度并能够小型化。刚才描述的益处是近来堆叠封装流行增加的一个原因。
堆叠封装的穿通电极通过在半导体芯片中定义通孔(via hole)并使用镀覆工艺来用金属材料填充该通孔而形成。穿通电极也可以使用焊接工艺形成。
这时，穿通电极(通过镀覆或焊接工艺形成)和半导体芯片具有不同的热膨胀系数。因此，半导体封装中的热变化可能在半导体封装中引起裂化(cracking)，该裂化是由于各自的热膨胀系数之间的差异导致的应力，从而降低半导体封装的可靠性。
当在堆叠多个半导体芯片或晶片之后通过定义通孔来形成穿通电极时，由于通孔的大的(substantial)的深宽比(aspect ratio)而难以适当地形成穿通电极。换言之，当通过镀覆工艺形成穿通电极时，通孔的大的深宽比使得形成穿通电极的金属材料仅仅填充通孔的上部。结果，使用穿通电极的半导体封装中的电信号连接变得不可能。机械实验显示蒸汽(vapor)进入并填充通孔的下部，引起半导体封装的故障(breakdown)。
发明内容
本发明的实施例旨在一种使用穿通电极的半导体封装，以改善封装内电连接的可靠性。
在本发明的一个方面中，半导体封装包括具有多个接合衬垫的半导体芯片；以及形成在半导体芯片中以电连接到各接合衬垫并包括导体和由导体定义的空隙的穿通电极。
每个导体包括纳米线。
每个导体包括以球状成组的多个纳米线并具有由所述纳米线定义的多个空隙。
每个导体具有1～40μm的直径。
每个导体包括以多边形形状成组并具有空隙的多个纳米线。
导体包括微焊料球。
每个微焊料球具有1～40μm的直径。
在本发明的另一方面中，半导体封装包括具有多个连接衬垫的基板；附着到基板并具有接合衬垫的半导体芯片；以及半导体芯片中的将半导体芯片的接合衬垫与基板的相应连接衬垫电连接的多个穿通电极，每个穿通电极包括导体和由导体定义的空隙。
每个导体包括纳米线。
每个导体包括以球状成组的多个纳米线并具有由所述纳米线定义的多个空隙。
每个导体具有1～40μm的直径。
每个导体包括以多边形形状成组并具有空隙的多个纳米线。
导体包括微焊料球。
每个微焊料球具有1～40μm的直径。
半导体封装还包括形成在穿通电极的背向基板的连接衬垫的末端上的盖层。
在本发明的再一方面中，半导体封装包括具有多个连接衬垫的基板；以及堆叠在基板上的至少两个封装单元，其中每个封装单元包括具有接合衬垫和多个穿通电极的半导体芯片，多个穿通电极以将半导体芯片的接合衬垫、基板的相应的连接衬垫以及封装单元彼此电连接的方式形成在半导体芯片中，每个穿通电极包括导体和由导体定义的空隙。
每个导体包括纳米线。
每个导体包括以球状成组的多个纳米线并具有由所述纳米线定义的多个空隙。
每个导体具有1～40μm的直径。
每个导体包括以多边形形状成组并具有空隙的多个纳米线。
导体包括微焊料球。
每个微焊料球具有1～40μm的直径。
半导体封装还包括形成在最上的半导体芯片的穿通电极上的盖层。
附图说明
图1是示出根据本发明第一实施例的半导体封装的截面图；
图2是示出图1的‘A’部分的放大图；
图3是示出根据本发明的构成导体的纳米线的图；
图4是示出根据本发明第二实施例的半导体封装的截面图；
图5是示出根据本发明第三实施例的半导体封装的截面图；
图6是示出根据本发明第四实施例的半导体封装的截面图。
具体实施方式
以下将会参考附图来详细描述本发明的具体实施例。
图1是示出根据本发明第一实施例的半导体封装的截面图，而图2是示出图1的‘A’部分的放大图。
参考图1，根据本实施例的半导体封装100包括半导体芯片110和穿通电极120，半导体芯片110具有形成在其上表面上的多个接合衬垫(bondingpad)112，每个穿通电极120填充多个通孔V之一，每个通孔V定义在半导体芯片110中并通过半导体芯片110延伸。
如图2所示，形成穿通电极120的方式是导体122填充在通孔V中。穿通电极120电连接到半导体芯片110的接合衬垫112。更详细地，每个穿通电极120包括填充在通孔V中的多个导体122。导体122可以具有各种形状并且空隙H可以由导体122定义。
导体122包括微尺寸的微焊料球(solder ball)或者多个纳米线124，每个微焊料球的直径在1～40μm范围内，纳米线124如图3所示成组并具有纳米尺度的直径。当包括纳米线124的导体122形成为多个纳米线124彼此成组时，导体122具有纳米尺度的纳米空隙H′。由成组的纳米线124形成的每个导体122具有多边形状或者直径在1～40μm范围内的球状。穿通电极120由包括成组填充在通孔V中的纳米线124的导体122形成，在各组中从外侧形成的多个纳米线124彼此成组。
穿通电极120可以以纳米线124代替导体122填充在通孔V中的方式形成，纳米线124包括纳米空隙H′并且不定义固定的形状。这时，穿通电极120的形成是通过将液态或气态的纳米线形成材料引入通孔V，随后进行后处理(post-process)来生长纳米线124。
为了确保形成在通孔V中的导体122和接合衬垫112面对通孔V的内表面之间的稳定的电连接，可以施加导电粘合剂(未示出)到接合衬垫112的内表面。
图4是示出根据本发明第二实施例的半导体封装的截面图。
参考图4，包括填充在通孔V中的穿通电极120的半导体芯片110置于基板140上，并随后形成为可以安装在外部电路上的半导体封装130。换言之，根据本实施例的半导体封装130包括基板140、附着到基板140的半导体芯片110以及形成在半导体芯片110中的穿通电极120。
具体来说，基板140在其上表面上具有多个连接衬垫142，并且电极端子(未示出)位于基板140的下表面上以电连接到外部电路。各个半导体芯片110以各穿通电极120对应于连接衬垫142的安置方式通过粘合剂(未示出)附着到基板140。
半导体芯片110具有多个接合衬垫112。穿通电极120形成在半导体芯片110中，使得半导体芯片110的接合衬垫112和基板140的相应的连接衬垫142彼此电连接。如图2所示，穿通电极120具有导体122和由导体122定义的空隙H。
盖层(capping layer)126形成在包括穿通电极120的半导体芯片110的上表面上从而避免构成穿通电极120的导体122从通孔V脱出，该上表面背向基板140的连接衬垫142。
形成密封剂150以覆盖置于基板140上的半导体芯片110。外部连接端子144(诸如焊料球(solder ball))附着到形成在基板140下表面上的电极端子(未示出)。
半导体封装130如下形成。具有通孔V的半导体芯片110附着到基板140，并且随后具有空隙H的穿通电极120通过用导体122填充通孔V形成。基板140的连接衬垫142以及半导体芯片110的接合衬垫112通过穿通电极120彼此电连接。
随后盖层126形成在半导体芯片110上，从而避免构成穿通电极120的导体122从通孔V脱出。这时，如果在半导体封装130的加工中没有导体122脱出的可能，则不需要形成覆层126。
接着，通过将外部连接端子144附着到基板140的下表面上，在基板140上形成密封剂150，从而完成根据本发明的本实施例的半导体封装130的制造。
图5是示出根据本发明第三实施例的半导体封装的截面图。
参考图5，通过将多个半导体芯片彼此堆叠来实现堆叠封装，并且每个半导体芯片都具有包括导体和由导体定义的空隙的穿通电极。
具体来说，在本实施例中，具有堆叠结构的半导体封装160形成为至少两个封装单元170使用粘合剂(未示出)堆叠在基板140上，基板140在其上表面上具有多个连接衬垫142而在其下表面上具有多个电极端子(未示出)。
每个封装单元170包括具有接合衬垫112的半导体芯片110和多个穿通电极120。穿通电极120的作用是将半导体芯片110的接合衬垫112、基板140的连接衬垫142和封装单元170彼此电连接。如图2所示，穿通电极120具有导体122和由导体122定义的空隙H。
盖层126形成在最上的封装单元170，即最上的半导体芯片110的穿通电极120上，以避免构成穿通电极120的导体122从通孔V脱出。
密封剂150形成在基板140上以覆盖半导体芯片110，并且外部连接端子144(诸如焊料球)附着到形成在基板140下表面上的电极端子(未示出)。
图6是示出根据本发明第四实施例的半导体封装的截面图。
参考图6，根据本实施例的具有堆叠结构的半导体封装180的具有这样的构造，在该构造中通过多个堆叠的半导体芯片110同时形成多个穿通电极120。
根据本实施例的半导体封装180形成如下。
首先，多个半导体芯片110堆叠在基板140上，随后通孔V定义在堆叠的半导体芯片110中并透过堆叠的半导体芯片110，从而暴露基板140的连接衬垫142。
具有空隙H的穿通电极120通过在通孔V中填充导体122形成，随后在最上的半导体芯片110上形成盖层126以避免构成穿通电极120的导体122从通孔V脱出。
接着，密封剂150和外部连接端子144形成在基板140上，并且通过进行一系列已知的后续工艺来完成根据本实施例的半导体封装180的制造工艺。
根据本发明的本实施例的各种半导体封装可以在晶片级或者芯片级被制造。
从以上描述明显可见，根据本发明的半导体封装利用穿通电极形成，所述穿通电极通过在通孔中填充导体形成。因此，即使其中形成穿通电极的通孔的深宽比是大的，也能以此方式容易地形成穿通电极以便改善电连接的可靠性。
此外，根据本发明的半导体封装的穿通电极通过将包括具有纳米空隙的成组的纳米线的导体或者包括微焊料球的导体填充到通孔中来形成，使得空隙由导体定义。因此，包括纳米空隙的空隙的作用是吸收由半导体封装的组成部分之间的热膨胀系数差异引起的应力，其是由驱动半导体封装的过程中产生的热导致的。因此，可以避免在驱动具有通过镀覆或焊接工艺形成的穿通电极的传统半导体封装的过程中在半导体芯片中发生由应力导致的裂化，该应力是由于构成半导体芯片的硅和构成穿通电极的金属材料之间的热膨胀系数差异而引起的。结果，改善了根据本发明实施例的半导体封装中电连接的可靠性。
尽管出于说明目的描述了本发明的具体实施例，但本领域的技术人员应该理解的是，可以在不脱离由所附权利要求中所公开的本发明范围和精神的前提下进行各种修改、添加和替换。
本申请要求于2008年6月30日提交的韩国专利申请号10-2008-0062910的优先权，并以参考方式将其全部内容合并在此。

Claims (11)

1.一种半导体封装，包括：
具有接合衬垫的半导体芯片；以及
形成在所述半导体芯片中并电连接到所述接合衬垫的穿通电极，其中所述穿通电极包括多个导体和由所述导体定义的一个或多个空隙，所述导体中的一个或多个包括以球状成组的多个纳米线并具有由所述纳米线定义的多个空隙。
2.根据权利要求1所述的半导体封装，其中每个所述导体的直径在1～40μm的范围内。
3.一种半导体封装，包括：
具有接合衬垫的半导体芯片；以及
形成在所述半导体芯片中并电连接到所述接合衬垫的穿通电极，其中所述穿通电极包括多个导体和由所述导体定义的一个或多个空隙，其中所述导体中的一个或多个包括以多边形形状成组并具有多个空隙的多个纳米线。
4.一种半导体封装，包括：
具有多个连接衬垫的基板；
附着到所述基板并具有多个接合衬垫的半导体芯片；以及
形成在所述半导体芯片中以将所述半导体芯片的接合衬垫电连接到所述基板的连接衬垫的多个穿通电极，其中所述穿通电极中的一个或多个包括多个导体和由所述导体定义的一个或多个空隙，所述导体中的一个或多个包括以球状成组的多个纳米线并具有由所述纳米线定义的多个空隙。
5.根据权利要求4所述的半导体封装，其中每个所述导体的直径在1～40μm的范围内。
6.根据权利要求4所述的半导体封装，还包括：
形成在每个穿通电极的背向所述基板的连接衬垫的末端上的盖层。
7.一种半导体封装，包括：
具有多个连接衬垫的基板；
附着到所述基板并具有多个接合衬垫的半导体芯片；以及
形成在所述半导体芯片中以将所述半导体芯片的接合衬垫电连接到所述基板的连接衬垫的多个穿通电极，其中所述穿通电极中的一个或多个包括多个导体和由所述导体定义的一个或多个空隙，其中所述导体中的一个或多个包括以多边形形状成组并具有多个空隙的多个纳米线。
8.一种半导体封装，包括：
具有多个连接衬垫的基板；以及
堆叠在所述基板上的至少两个封装单元，
其中每个封装单元包括：
具有多个接合衬垫和穿通电极的半导体芯片，所述穿通电极形成在所述半导体芯片中以将所述半导体芯片的接合衬垫、所述基板的相应的连接衬垫以及所述封装单元彼此电连接，其中穿通电极中的一个或多个包括多个导体和由所述导体定义的一个或多个空隙，其中所述导体中的一个或多个包括以球状成组的多个纳米线并具有由所述纳米线定义的多个空隙。
9.根据权利要求8所述的半导体封装，其中每个所述导体的直径在1～40μm的范围内。
10.根据权利要求8所述的半导体封装，还包括：
形成在最上的半导体芯片的所述穿通电极上的盖层。
11.一种半导体封装，包括：
具有多个连接衬垫的基板；以及
堆叠在所述基板上的至少两个封装单元，
其中每个封装单元包括：
具有多个接合衬垫和穿通电极的半导体芯片，所述穿通电极形成在所述半导体芯片中以将所述半导体芯片的接合衬垫、所述基板的相应的连接衬垫以及所述封装单元彼此电连接，其中穿通电极中的一个或多个包括多个导体和由所述导体定义的一个或多个空隙，其中所述导体中的一个或多个包括以多边形形状成组并具有多个空隙的多个纳米线。
CN2009101523284A 2008-06-30 2009-06-30 使用具有空隙的穿通电极的半导体封装 Expired - Fee Related CN101621046B (zh)

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