CN101330076B - 穿透硅通道芯片堆叠封装 - Google Patents

穿透硅通道芯片堆叠封装 Download PDF

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Publication number
CN101330076B
CN101330076B CN2007101407320A CN200710140732A CN101330076B CN 101330076 B CN101330076 B CN 101330076B CN 2007101407320 A CN2007101407320 A CN 2007101407320A CN 200710140732 A CN200710140732 A CN 200710140732A CN 101330076 B CN101330076 B CN 101330076B
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chip
pad
penetrates
silicon
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CN101330076A (zh
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金钟薰
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种穿透硅通道芯片堆叠封装，在器件运行期间能够利于芯片选择。该穿透硅通道芯片堆叠封装包括：基板；多个堆叠在基板上的芯片，其具有芯片选择垫、穿透硅通道和分别连接该芯片选择垫和该穿透硅通道的重布线，该穿透硅通道各自相连；以及贴装在该基板的下表面的外部连接终端，其中形成每个堆叠的芯片中的重布线以作为该芯片选择垫和该穿透硅通道之间的连接结构，其在每个芯片中都与其他的不同。

Description

穿透硅通道芯片堆叠封装
技术领域
本发明涉及一种穿透硅通道芯片堆叠封装，且特别涉及利于芯片选择的穿透硅通道芯片堆叠封装。
背景技术
针对半导体集成器件的封装技术已经持续发展以满足安装效率和小型化的要求。由于在最近电器/电子设备的发展趋势中要求小型化和高性能，所以已发展了多种半导体堆叠技术。
在半导体工业中涉及的“堆叠”为至少两个半导体芯片或封装在垂直方向叠加起来的技术。例如，当这种堆叠技术应用在存储器件的领域中，可以实现封装的产品具有的存储容量是没封装的芯片的存储容量的两倍多，且因此可以提高安装领域使用的效率。
图1为说明传统芯片堆叠封装的截面示意图。如图所示，芯片110通过媒介粘合剂130堆叠在基板120上且每个芯片110通过线140导电连接到基板120。包括堆叠的芯片110和线140的基板120的上表面由密封剂150如环氧成型混合物(EMC)密封，且基板120的下表面粘附焊料球160作为至外电路的安装装置。
图1中，参考数字112表示垫，122表示电极终端，124表示球焊盘，和126表示电路布线。
然而，传统芯片堆叠封装具有如下几个缺点：由于使用金属线来使信号连接到每个芯片致使运行速度相对慢；由于基板上需要额外的区域给引线键合致使封装的尺寸不能更紧凑；以及由于在每个芯片的焊盘上需要用于引线键合的间隙致使封装的高度不能更低。
为了克服上面描述的与传统芯片堆叠封装相关的问题，已经提出了采用穿透硅通道(在下文称TSV)的芯片堆叠封装。
图2为说明TSV芯片堆叠封装的截面图。如图所示，在TSV芯片堆叠封装200中，通过在每个芯片210中形成孔洞且用导电层填充该孔洞来形成TSV 270，且此后由TSV 270在芯片210之间形成导电连接。
在图2中，参考数字212表示垫，220表示基板，222表示电极终端，224表示球焊盘，226表示电路布线和260表示焊料球。
如图1所示，TSV芯片堆叠封装200将不需要基板上的额外的区域来提供给引线键合的导电连接和不需要芯片之间存在间隙来提供给芯片和基板之间的引线键合。因此，当与图1所示的传统封装100比较时，因为基板和芯片之间的信号连接长度缩短，TSV芯片堆叠封装200减小了尺寸和高度，以及因此可提高其中封装的芯片的运行速度。
如图1所示，在堆叠与非快速存储芯片的情况下，采用引线键合来实现这种芯片堆叠封装，现参考图3，通过对芯片310a、310b的芯片选择垫进行彼此不同的引线键合使得电极终端322a、322b(也就是Vcc端和Vss端)引线键合到芯片310a、310b如图3所示，从而在封装的器件运行期间能够进行芯片选择。
然而，在TSV芯片堆叠封装的情况下，在器件的运行期间选择特定的芯片是不可能，因为在TSV芯片堆叠封装中没有形成引线键合如图3所示。因此，为了芯片选择，TSV芯片堆叠封装需要新颖的连接结构。
此外，在传统芯片堆叠封装中，芯片选择需要随堆叠的芯片的数量增加而增加芯片选择垫的数量。
然而，如果芯片选择垫的数量增加，由于提供给个体芯片的垫片数量增加使得芯片尺寸不可避免地增加了，且这会阻止该封装自身以及应用该封装的产品的理想的最小化。
发明内容
本发明的实施例涉及一种TSV芯片堆叠封装，其在器件运行期间有利于芯片选择。
同样，本发明的实施例涉及一种TSV芯片堆叠封装，其能够实现大量芯片堆叠而不增加芯片尺寸。
在一实施例中，TSV芯片堆叠封装可包括：基板；多个堆叠在基板上的芯片，其具有芯片选择垫、穿透硅通道和分别连接芯片选择垫和穿透硅通道的重布线，穿透硅通道各自相连；以及贴装在基板的下表面的外部连接终端，其中每个堆叠的芯片中形成重布线以作为芯片选择垫和穿透硅通道之间的连接结构，其在每个芯片中都与其他的不同。
在该实施例中，可堆叠四个芯片。
每个堆叠的芯片具有第一和第二芯片选择垫、第一至第三穿透硅通道和以各不相同的结构连接第一和第二芯片选择垫与第一至第三穿透硅通道的两个重布线。
第一穿透硅通道安置在第一和第二芯片选择垫之间，且第二和第三穿透硅通道分别安置在第一和第二芯片选择垫外部。
第一至第三穿透硅通道被施加Vss或Vcc信号。
在该实施例中，可堆叠八个芯片。
每个堆叠的芯片具有第一至第三芯片选择垫、第一至第四穿透硅通道和以各不相同的结构连接第一至第三芯片选择垫和第一至第四穿透硅通道的三个重布线。
第一和第二穿透硅通道安置在第一和第二芯片选择垫之间，且第三和第四穿透硅通道安置在第二和第三芯片选择垫之间。
第一至第四穿透硅通道被施加Vss或Vcc信号。
该外部连接终端为焊料球。
附图说明
图1为说明传统芯片堆叠封装的截面图。
图2为说明穿透硅通道芯片堆叠封装的截面图。
图3为说明在传统芯片堆叠封装中芯片选择的附图。
图4为说明与本发明的一实施例一致的穿透硅通道芯片堆叠封装的截面图。
图5为图4中A部分的放大图，该图说明与本发明的一实施例一致的穿透硅通道芯片堆叠封装中的芯片选择。
图6为说明与本发明的另一实施例一致的穿透硅通道芯片堆叠封装的截面图。
图7为说明与本发明的另一实施例一致的穿透硅通道芯片堆叠封装中的芯片选择的表格。
具体实施方式
本发明的优选示范例是指一种芯片堆叠封装，在其中TSV形成于具有至少两个芯片选择垫和至少两个用于连接TSV和芯片选择垫的重布线的每一芯片中。芯片采用TSV堆叠。这时，在每个芯片中形成重布线以使得堆叠的芯片在TSV和芯片选择垫之间具有连接结构，这些结构各不相同。
通过这些操作，由于堆叠的芯片在TSV和芯片选择垫之间具有各不相同的连接结构，通过使所加信号到达TSV，包括各芯片中不同重布线，这可以有利于甚至器件运行期间的芯片选择。
因此，在本发明的一实施例中，由于具有利于芯片选择的优点和通过使用TSV芯片堆叠封装结构而减小封装的尺寸和高度以及提高运行速度的优点，可实现高性能产品。同样，在本发明的一实施例中，由于堆叠芯片具有TSV和芯片选择垫之间各不相同的连接结构，所以没必要增加芯片选择垫的数量且因而阻止因芯片选择垫的数量增加而增加的芯片尺寸。
在下文中，将参考随后的附图描述与本发明的一实施例一致的芯片堆叠封装。
图4为说明与本发明一实施例一致的TSV芯片堆叠封装的截面图，和图5为图4中所示的A部分的放大图，该图说明与本发明一实施例一致的TSV芯片堆叠封装的芯片选择。
TSV芯片堆叠封装400具有四个芯片410a至410d堆叠在基板420上，尽管可堆叠的芯片数量不仅限于4个。提供给芯片410a至410d中的每个芯片的TSV 470a、470b和470c都安排得相互接触。焊料球460贴装到基板420的下表面作为外部连接终端。
在这里，基板420设有电路布线426，其包括安置在基板420上表面的电极终端422和安置在基板420下表面的球焊盘424。
可堆叠2n(n为大于2的整数如4、8、16、32等)数量的芯片，且因而在一实施例中堆叠四个芯片410a至410d如图4-5所示。此外，堆叠的芯片410a至410d中每个芯片都设有第一芯片选择垫(CS1)412和第二芯片选择垫(CS2)414。
在TSV 470a、470b和470c中，第一TSV 470a安置在芯片410a至410d的每个芯片中的第一芯片选择垫412和第二芯片选择垫414之间，且第二TSV 470b和第三TSV 470c分别安置在芯片410a至410d的每个芯片中的第一芯片选择垫412和第二芯片选择垫414的外面。
形成堆叠的芯片410a至410d的每个芯片都具有重布线480来相互连接第一和第二芯片选择垫(CS1)412和(CS2)414与TSV 470a、470b和470c。形成重布线480使得三个TSV 470a、470b和470c中只有两个连接到第一和第二芯片选择垫412和414，且特别地使得对一个芯片的第一和第二芯片选择垫412和414的连接结构不同于至少临近堆叠的芯片或所有其他堆叠的芯片410a至410d。
例如，形成安置在最下面的第一芯片410a使得它的重布线480连接第一TSV 470a到第一和第二芯片选择垫412和414。形成安置在第一芯片410a上面的第二芯片410b使得它的重布线480连接第一TSV 470a到第一芯片选择垫412和连接第三TSV 470c到第二芯片选择垫414。形成安置在第二芯片410b上面的第三芯片410c使得它的重布线480连接第一TSV 470a到第二芯片选择垫414和连接第二TSV 470b到第一芯片选择垫412。形成安置在最上面的第四芯片410d使得它的重布线480连接第二TSV 470b到第一芯片选择垫412和连接第三TSV 470c到第二芯片选择垫414。
在与本发明一实施例一致的TSV芯片堆叠封装400中，在芯片410a至410d的每个芯片中第一和第二芯片选择垫412和414通过第一至第三TVS470a至470c以及在芯片410a至410d的每个芯片中不同形成的重布线480来连接基板420的Vcc和Vss终端，且芯片选择由Vcc和Vss信号的不同变化来形成，所述Vcc和Vss信号通过Vcc和Vss终端提供给芯片。
例如，如图5所示，在只提供Vcc信号给第一TSV 470a的情况下选择第一芯片410a；在分别提供Vcc信号和Vss信号给第一TSV 470a和第二TSV470b的情况下选择第三芯片410c；在分别提供Vcc信号和Vss信号给第一TSV 470a和第三TSV 470c的情况下选择第二芯片410b；以及在分别提供Vcc信号和Vss信号给第二TSV 470b和第三TSV 470c的情况下选择第四芯片410d。
如上面所描述，如图4-5所示TSV芯片堆叠封装能有利于在器件运行期间的芯片选择，通过使信号提供给TSV包括在每个堆叠的芯片中不同的重布线，该芯片选择在形式上与采用引线键合堆叠的传统芯片中的选择相似如图1和3所示。
因此，依照本发明的一实施例的所述结构提供了采用TSV堆叠芯片而允许甚至在器件运行期间都有利于芯片选择。
图6和7为说明与本发明的另一实施例一致的TSV芯片堆叠封装及其芯片选择的截面图。
参考图6，与本发明的另一实施例一致的TSV芯片堆叠封装600具有一种结构，在该结构中八个芯片610a至610h堆叠在具有电路布线626的基板620上，该电路布线626包括电极终端622和球焊盘624，使得提供给芯片610a至610h中的每个芯片的TSV 670a至670d为相互接触，且焊料球660贴装到基板620的下表面的球焊盘624，作为外部连接终端。
堆叠的芯片610a至610h中每个都设有第一芯片选择垫(CS1)612、第二芯片选择垫(CS2)614和第三芯片选择垫(CS3)616。同时，堆叠的芯片610a至610h中每个芯片都设有在第一和第二芯片选择垫612和614之间形成的第一和第二TSV 670a和670b，以及在第二和第三芯片选择垫614和616之间形成的第三和第四TSV 670c和670d。
此外，堆叠的芯片610a至610h中每个芯片都设有重布线680用于连接第一至第三芯片选择垫612、614和616与第一至第四TSV 670a至670d。形成重布线680使得利用堆叠的芯片610a至610h中的每个芯片中各不相同的连接结构来连接第一至第三芯片选择垫612、614和616与第一至第四TSV670a至670d。
例如，形成第一芯片610a的重布线680使得连接第二TSV 670b到第一芯片选择垫612，连接第四TSV 670d到第二芯片选择垫614，和连接第三TSV 670c到第三芯片选择垫616。形成第二芯片610b的重布线680使得连接第二TSV 670b到第一芯片选择垫612，连接第四TSV 670d到第二芯片选择垫614，和连接第四TSV 670d到第三芯片选择垫616。形成第三芯片610c的重布线680使得连接第二TSV 670b到第一芯片选择垫612，连接第三TSV670c到第二芯片选择垫614，和连接第三TSV 670c到第三芯片选择垫616。形成第四芯片610d的重布线680使得连接第二TSV 670b到第一芯片选择垫612，连接第三TSV 670c到第二芯片选择垫614，和连接第四TSV 670d到第三芯片选择垫616。
形成第五芯片610e的重布线680使得连接第一TSV 670a到第一芯片选择垫612，连接第四TSV 670d到第二芯片选择垫614，和连接第三TSV 670c到第三芯片选择垫616。形成第六芯片610f的重布线680使得连接第一TSV670a到第一芯片选择垫612，连接第四TSV 670d到第二芯片选择垫614，和连接第四TSV 670d到第三芯片选择垫616。形成第七芯片610g的重布线680使得连接第一TSV 670a到第一芯片选择垫612，连接第三TSV 670c到第二芯片选择垫614，和连接第三TSV 670c到第三芯片选择垫616。最后，形成第八芯片610h的重布线680使得连接第一TSV 670a到第一芯片选择垫612，连接第三TSV 670c到第二芯片选择垫614，和连接第四TSV 670d到第三芯片选择垫616。
在与本发明的另一实施例一致的TSV芯片堆叠封装600中，在芯片610a至610h中的每个芯片中第一至第三芯片选择垫612、614和616通过第一至第四TSV 670a至670d和在芯片610a至610h中的每个芯片中不同形成的重布线680来连接到基板620的Vcc和Vss终端。通过Vcc和Vss终端提供Vcc和Vss信号的不同变化来形成芯片选择。
例如，如图7所示，在提供Vcc信号给第一芯片选择垫612、提供Vcc信号给第二芯片选择垫614和提供Vss信号给第三芯片选择垫616的情况下选择第一芯片610a；在提供Vcc信号给第一芯片选择垫612、提供Vcc信号给第二芯片选择垫614和也提供Vcc信号给第三芯片选择垫616的情况下选择第二芯片610b；在提供Vcc信号给第一芯片选择垫612、提供Vss信号给第二芯片选择垫614和提供Vss信号给第三芯片选择垫616的情况下选择第三芯片610c；以及在提供Vcc信号给第一芯片选择垫612、提供Vss信号给第二芯片选择垫614和提供Vcc信号给第三芯片选择垫616的情况下选择第四芯片610d。
此外，在提供Vss信号给第一芯片选择垫612、提供Vcc信号给第二芯片选择垫614和提供Vss信号给第三芯片选择垫616的情况下选择第五芯片610e；在提供Vss信号给第一芯片选择垫612、提供Vcc信号给第二芯片选择垫614和也提供Vcc信号给第三芯片选择垫616的情况下选择第六芯片610f；在提供Vss信号给第一芯片选择垫612、提供Vss信号给第二芯片选择垫614和也提供Vss信号给第三芯片选择垫616的情况下选择第七芯片610g；以及在提供Vss信号给第一芯片选择垫612、提供Vss信号给第二芯片选择垫614和提供Vcc信号给第三芯片选择垫616的情况下选择第八芯片610h。
通过提供信号给包括在每个堆叠的芯片中不同的重布线的TSV，如图6-7所示的TSV芯片堆叠封装在运行器件期间同样可有利于芯片选择。特别地，由于如图6-7所示(也如图4-5所示)的TSV芯片堆叠封装不通过增加芯片选择垫的数量来构建，而通过在芯片选择垫之间安置两个TSV和使得采用重布线的连接结构在每个芯片中不同，所以不必增加芯片选择垫的数量，且因而能够阻止芯片尺寸增加。
从上面的描述已很明白，依照本发明的一实施例，因为在每个堆叠的芯片中形成不同的用来连接芯片选择垫和TSV的重布线，所以可以实现一种TSV芯片堆叠封装，其在器件运行期间有利于芯片选择。因此，通过使用与本发明一实施例一致的TSV芯片堆叠封装结构，在器件运行期间可有利于芯片选择且封装的尺寸和高度相对缩小而运行速度相对提高，因此可以实现高性能产品。
同时，由于通过在TSV和芯片选择垫之间建立彼此不同的连接结构来形成芯片选择，所以不必增加芯片选择垫的数量，能阻止源于芯片选择垫的数量增加而增加的芯片尺寸，这与本发明的一实施例一致。
尽管已经描述了本发明的一具体实施例来举例说明，本领域的技术人员将可以理解在不脱离由权利要求所界定的本发明的精神和范围的情况下，可以做出各种改变、添加和代替。
本申请要求优先于2007年6月20日申请的韩国专利申请号10-2007-0060260，它在此处别全文引用作为参考。

Claims (11)

1.一种穿透硅通道芯片堆叠封装，包括：
基板；
多个堆叠在该基板上的芯片，每个芯片具有芯片选择垫、穿透硅通道和分别连接该芯片选择垫和该穿透硅通道的重布线，其中每个芯片的该穿透硅通道都相应地与临近堆叠的芯片的该穿透硅通道连接；和
外部连接终端，其贴装在基板的下表面，
其中形成在每个堆叠的芯片中的该重布线，以在该芯片选择垫和该穿透硅通道之间建立连接，使得连接该芯片选择垫和该穿透硅通道的连接结构对于每个堆叠的芯片不相同。
2.如权利要求1所述的穿透硅通道芯片堆叠封装，其中堆叠在基板上的芯片的总数为2n，n为大于等于2的整数。
3.如权利要求2所述的穿透硅通道芯片堆叠封装，其中堆叠在该基板上的芯片总数为4个。
4.如权利要求3所述的穿透硅通道芯片堆叠封装，其中每个所述堆叠的芯片设有第一和第二芯片选择垫、第一到第三穿透硅通道和两个重布线，使得第一和第二芯片选择垫与第一至第三穿透硅通道之间的连接对每个芯片都不同。
5.如权利要求4所述的穿透硅通道芯片堆叠封装，其中第一穿透硅通道安置在第一和第二芯片选择垫之间，以及第二和第三穿透硅通道分别安置在第一和第二芯片选择垫外面。
6.如权利要求5所述的穿透硅通道芯片堆叠封装，其中第一至第三穿透硅通道被施加Vss或Vcc信号。
7.如权利要求2所述的穿透硅通道芯片堆叠封装，其中堆叠在基板上的所述芯片的总数为8个。
8.如权利要求7所述的穿透硅通道芯片堆叠封装，其中每个所述堆叠的芯片设有第一至第三芯片选择垫、第一至第四穿透硅通道和三个重布线，使得第一至第三芯片选择垫与第一至第四穿透硅通道之间的连接对每个芯片都不同。
9.如权利要求8所述的穿透硅通道芯片堆叠封装，其中第一和第二穿透硅通道安置在第一和第二芯片选择垫之间，且第三和第四穿透硅通道安置在第二和第三芯片选择垫之间。
10.如权利要求9所述的穿透硅通道芯片堆叠封装，其中第一至第四穿透硅通道被施加Vss或Vcc信号。
11.如权利要求1所述的穿透硅通道芯片堆叠封装，其中外部连接终端为焊料球。
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