US20120043664A1 - Implementing multiple different types of dies for memory stacking - Google Patents

Implementing multiple different types of dies for memory stacking Download PDF

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Publication number
US20120043664A1
US20120043664A1 US12/861,056 US86105610A US2012043664A1 US 20120043664 A1 US20120043664 A1 US 20120043664A1 US 86105610 A US86105610 A US 86105610A US 2012043664 A1 US2012043664 A1 US 2012043664A1
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Prior art keywords
dies
arrays
tsvs
vias
silicon
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US12/861,056
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Paul W. Coteus
Kyu-hyoun Kim
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GlobalFoundries Inc
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International Business Machines Corp
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Priority to US12/861,056 priority Critical patent/US20120043664A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: COTEUS, PAUL W., KIM, KYU-HYOUN
Priority to US13/364,346 priority patent/US8343804B2/en
Publication of US20120043664A1 publication Critical patent/US20120043664A1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
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Abstract

A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to the data processing field, and more particularly, relates to a method and structure for implementing multiple different types of dies for memory stacking.
    • DESCRIPTION OF THE RELATED ART
  • Advanced memory stacking technology is emerging. One example illustrated in FIGS. 1A, and 1B, is a master-slave structure including a printed circuit board (PCB), a master die, and a plurality of slave dies. For example, in the illustrated prior art master-slave, only a specific die, the bottom die labeled master in the stacked package communicates to the outside of the package to save standby power by shutting down circuitries in other dies that are not required to operate. FIG. 1B illustrates the bottom master die, which includes a plurality of arrays and a periphery segment centrally located between the arrays. Multiple through-silicon-vias (TSVs) are placed within the periphery segment.
  • There are two possible ways of die implementations for this structure. One option-A is to use an exactly same die to implement both master and slave, and another option-B is to use completely different dies where the master die has everything but the slave dies has only minimum blocks and also has smaller die size than master die. In option-A, only one type of wafer is necessary but each of the multiple slave dies 1, 2, 3 is larger than required, which results in some wasting of silicon area. In option-B, two different wafers and reticles are required to be manufactured, which results in additional manufacturing cost.
  • A need exists for an improved method for implementing multiple different types of dies for memory stacking. It is desirable to provide such method that is effective and simple to implement and that does not require expensive processing and fabrication techniques.
    • SUMMARY OF THE INVENTION
  • Principal aspects of the present invention are to provide a method and structures for implementing multiple different types of dies for memory stacking. Other important aspects of the present invention are to provide such a method and structure substantially without negative effects and that overcome many of the disadvantages of prior art arrangements.
  • In brief, a method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between the array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies.
  • In accordance with features of the invention, the multiple different types of dies include arrays and the periphery segment dies, arrays only dies, and periphery segment only dies.
  • In accordance with features of the invention, one reticle type includes a plurality of through-silicon-vias (TSVs) placed at boundaries between arrays.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
  • FIGS. 1A, and 1B illustrate a conventional master-slave memory stack structure; and
  • FIGS. 2-18 schematically illustrate structures not to scale for implementing multiple different types of dies for memory stacking in accordance with embodiments of the invention.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which illustrate example embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
  • In accordance with features of the invention, a method and structures are provided for implementing multiple different types of dies for memory stacking.
  • Having reference now to the drawings, in FIGS. 2-18, there are shown structures for implementing multiple different types of dies for memory stacking in accordance with embodiments of the invention. In accordance with features of the invention, a method includes starting with a reticle type or photomask including a pattern for reproducing elements of the memory circuit to be created on a common semiconductor wafer. The image of the reticle pattern is formed onto the common semiconductor wafer, such as a silicon wafer that is coated with a photosensitive material or photoresist, and multiple different types of dies for memory stacking are obtained by scribing the common wafer.
  • Referring now to FIG. 2, there is shown an example first reticle type or photomask generally designated by the reference character 200 in accordance with the preferred embodiment. The first reticle type 200 includes a plurality of arrays 202, and a plurality of periphery segments 204. A plurality of through-silicon-vias (TSVs) 206 is placed at boundaries between array and periphery segments. A first die Type A, 210 indicated in dotted line includes first and second pairs of arrays 202 with one centrally disposed periphery segments 204 between the TSVs 206 and array pairs. Four first die Type A, 210 are included within the example first reticle type 200. Multiple different types of dies, such as die 210 for memory stacking are obtained based upon selected scribing of the dies.
  • Referring now to FIG. 3, there is shown a first scribing example of a semiconductor wafer generally designated by the reference character 300 in accordance with the preferred embodiment including a plurality of the first reticle type 200. The semiconductor wafer 300 is diced or cut along a plurality of scribe lines 302 into a plurality of the first die Type A, 210. Each of the plurality of the first die Type A, 210 can be mounted into a respective package.
  • Referring now to FIG. 4, there is shown a first packaging example generally designated by the reference character 400 in accordance with the preferred embodiment using the first reticle type 200. The first packaging example 400 is a stacked structure including the first die Type A, 210 mounted to printed circuit board (PCB) 402.
  • Referring now to FIG. 5, there is shown another scribing example of the first reticle type 200 generally designated by the reference character 500 in accordance with the preferred embodiment. A second die Type B 502 indicated in dotted line includes only the periphery segment 204 disposed below and including the adjacent TSVs 206. A third die Type C 504 indicated in dotted line includes first and second pairs of arrays 202 disposed below and including the adjacent TSVs 206.
  • Referring now to FIG. 6, there is shown a scribing example of a semiconductor wafer generally designated by the reference character 600 in accordance with the preferred embodiment including a plurality of copies of the first reticle type 200. The semiconductor wafer 300 is diced or cut along a plurality of scribe lines 302 into a plurality of the second dies Type B, 502 and a plurality of the third dies Type C, 504. Each of the second dies Type B, 502 and the third dies Type C, 504 can be mounted into a respective package.
  • Referring now to FIG. 7, there is shown another packaging example generally designated by the reference character 700 in accordance with the preferred embodiment using the first reticle type 200. The packaging example 700 is a stacked structure including the first die Type A, 210 mounted to the printed circuit board (PCB) 402, and a plurality of slave 1, 2, 3 third dies Type C, 504 mounted above the master first die Type A, 210 and connected by TSVs 206 to the master first die Type A, 210.
  • Referring now to FIG. 8, there is shown another packaging example generally designated by the reference character 800 in accordance with the preferred embodiment using the first reticle type 200. The packaging example 800 is a stacked structure including the first die Type A, 210 mounted to the printed circuit board (PCB) 402. The packaging example 800 includes a plurality of slave 1, 2, 3 third dies Type C, 504 and a plurality of slave 4, 5, 6 third dies Type C, 504 respectively mounted above the master first die Type A, 210 and respectively connected to the master first die Type A, 210 by the opposed adjacent TSVs 206 disposed on opposite sides of the periphery 204.
  • Referring now to FIG. 9, there is shown another packaging example generally designated by the reference character 900 in accordance with the preferred embodiment using the first reticle type 200. The packaging example 900 is a stacked structure including the second die Type B, 502 mounted to the printed circuit board (PCB) 402. The packaging example 900 includes a plurality of slave 1, 2, 3 third dies Type C, respectively mounted above the second die Type B, 502 and respectively connected to the master second die Type B, 502 by adjacent TSVs 206.
  • Referring now to FIG. 10, there is shown another packaging example generally designated by the reference character 1000 in accordance with the preferred embodiment using the first reticle type 200. The packaging example 1000 is a stacked structure including the second die Type B, 502 disposed at the top of the stack, and a plurality of slave 1, 2, 3 third dies Type C, respectively mounted above the printed circuit board (PCB) 402. The packaging example 1000 includes the plurality of slave 1, 2, 3 third dies Type C respectively connected to the upper master second die Type B, 502 by adjacent TSVs 206. The upper master second die Type B, 502 is connected to the printed circuit board (PCB) 402, for example by wire-bond 1002, as shown.
  • Referring now to FIG. 11, there is shown another scribing example of the first reticle type 200 generally designated by the reference character 1100 in accordance with the preferred embodiment. A fourth die Type D 1102 indicated in dotted line includes first and second pairs of arrays 202 disposed above the periphery segment 204 and including the adjacent TSVs 206. The third die Type C 504 also is shown, as indicated in dotted line includes first and second pairs of arrays 202 disposed below and including the adjacent TSVs 206.
  • Referring now to FIG. 12, there is shown a scribing example of a semiconductor wafer generally designated by the reference character 1200 in accordance with the preferred embodiment including a plurality of copies of the first reticle type 200. The semiconductor wafer 1200 is diced or cut along the plurality of scribe lines 302 into a plurality of the third dies Type C, 504 and a plurality of the fourth dies Type D, 1102. Each of the second dies Type C, 504 and the fourth dies Type D, 1102 can be mounted into a respective package.
  • Referring now to FIG. 13, there is shown an example second reticle type or photomask generally designated by the reference character 1300 in accordance with the preferred embodiment. The second reticle type 1300 includes a plurality of arrays 202, and a plurality of periphery segments 204. A plurality of through-silicon-vias (TSVs) 206 is placed at boundaries between respective first and second pairs of arrays 202 and the periphery segments 204, and a plurality of through-silicon-vias (TSVs) 206 is placed at boundaries between lower third and fourth pairs of array 202. The first die Type A, 210 indicated in dotted line includes the first and second pairs of arrays 202 with one centrally disposed periphery segments 204 between the TSVs 206 and the respective array pairs. A fifth die Type E, 1302 indicated in dotted line includes the lower third and fourth pairs of array 202 and the centrally disposed TSVs 206 between these array pairs. Two first dies Type A, 210, and two fifth dies Type E, 1302 are included within the example second reticle type 1300. Multiple different types of dies, such as dies Type A 210, and fifth dies Type E 1302, for memory stacking are obtained based upon selected scribing of the dies.
  • Referring now to FIG. 14, there is shown a scribing example of a semiconductor wafer generally designated by the reference character 1400 in accordance with the preferred embodiment including a plurality of copies of the second reticle type 1300. The semiconductor wafer 1300 is diced or cut along the plurality of scribe lines 302 into a plurality of the first dies Type A, 210 and a plurality of the fifth dies Type E 1302. Each of the first dies Type A, 210 and the fifth dies Type E 1302 can be mounted into a respective package.
  • Referring now to FIG. 15, there is shown another scribing example of the second reticle type 1300 generally designated by the reference character 1500 in accordance with the preferred embodiment. The second die Type B 502 indicated in dotted line includes only the periphery segment 204 disposed below and including the adjacent TSVs 206. The third die Type C 504 indicated in dotted line includes first and second pairs of arrays 202 disposed below and including the adjacent TSVs 206.
  • Referring now to FIG. 16, there is shown a scribing example of a semiconductor wafer generally designated by the reference character 1600 in accordance with the preferred embodiment including a plurality of copies of the second reticle type 1300. The semiconductor wafer 1300 is diced or cut along the plurality of scribe lines 302 into a plurality of the second dies Type B 502 and a plurality of third die Type C 504. Each of the second dies Type B 502 and the third die Type C 504 can be mounted into a respective package.
  • Referring now to FIG. 17, there is shown another packaging example generally designated by the reference character 1700 in accordance with the preferred embodiment using the second reticle type 1300. The packaging example 1700 is a stacked structure including the first die Type A, 210 mounted to the printed circuit board (PCB) 402, and a plurality of slave 1, 2, 3 fifth dies Type E, 1302 mounted above the master first die Type A, 210 and connected by TSVs 206 to the master first die Type A, 210.
  • Referring now to FIG. 18, there is shown another packaging example generally designated by the reference character 1800 in accordance with the preferred embodiment using the second reticle type 1300. The packaging example 1800 is a stacked structure including the second die Type B, 502 mounted to the printed circuit board (PCB) 402. The packaging example 1800 includes a plurality of slave 1, 2, 3, 4 third dies Type C, respectively mounted above the second die Type B, 502 and respectively connected to the master second die Type B, 502 by adjacent TSVs 206. Note that the packaging example 1800 using the second reticle type 1300 is similar to the packaging example 900 using the first reticle type 200.
  • While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.

Claims (20)

What is claimed is:
1. A method for implementing multiple different types of dies for memory stacking comprising:
providing a reticle type includes a plurality of arrays, and a plurality of periphery segments;
placing a plurality of through-silicon-vias (TSVs) at boundaries between array and periphery segments;
providing a common wafer with said predefined reticle type; and
obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer.
2. The method as recited in claim 1 wherein providing a reticle type includes a plurality of arrays, and a plurality of periphery segments includes providing first and second pairs of arrays on opposed sides of the periphery segment.
3. The method as recited in claim 2 further includes placing said plurality of through-silicon-vias (TSVs) at opposed boundaries between said first and second pairs of arrays and the periphery segment.
4. The method as recited in claim 1 wherein providing a reticle type includes a plurality of arrays, and a plurality of periphery segments includes providing adjacent pairs of arrays spaced apart by a pair of arrays from the periphery segment.
5. The method as recited in claim 4 further includes placing a plurality of through-silicon-vias (TSVs) at a boundary between said adjacent pairs of arrays.
6. The method as recited in claim 1 wherein obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer includes scribing of dies including first and second pair of said arrays and one said periphery segment and said plurality of through-silicon-vias (TSVs) at boundaries between said first and second pair of said arrays and one said periphery segment.
7. The method as recited in claim 1 wherein obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer includes scribing of dies including a plurality of through-silicon-vias (TSVs) and arrays only.
8. The method as recited in claim 1 wherein obtaining multiple different types of the dies based upon selected scribing of dies from the common wafer includes scribing of dies including a plurality of through-silicon-vias (TSVs) and one said periphery segment only.
9. The method as recited in claim 1 includes forming a memory stack with a first die mounted on a printed circuit board (PCB).
10. The method as recited in claim 9 includes obtaining said first die including a plurality of through-silicon-vias (TSVs) and first and second pairs of arrays and one said periphery segment.
11. The method as recited in claim 9 includes obtaining said first die including plurality of through-silicon-vias (TSVs) and one said periphery segment.
12. The method as recited in claim 10 further includes obtaining a plurality of second dies including through-silicon-vias (TSVs) and arrays only; mounting said second dies and said first die in the memory stack connected by said TSVs.
13. The method as recited in claim 11 further includes obtaining a plurality of second dies including through-silicon-vias (TSVs) and arrays only; mounting said second dies and said first die in the memory stack connected by said TSVs.
14. A structure for implementing multiple different types of dies for memory stacking comprising:
a reticle type includes a plurality of arrays, and a plurality of periphery segments;
a plurality of through-silicon-vias (TSVs) being disposed at boundaries between array and periphery segments;
a common wafer being defined with said predefined reticle type; and said multiple different types of the dies being obtained based upon selected scribing of the common wafer.
15. The structure as recited in claim 14 wherein said reticle type includes first and second pairs of arrays on opposed sides of the periphery segment, and said plurality of through-silicon-vias (TSVs) being disposed at opposed boundaries between said first and second pairs of arrays and the periphery segment.
16. The structure as recited in claim 14 wherein said reticle type includes adjacent pairs of arrays spaced apart by a pair of arrays from the periphery segment, and includes a plurality of through-silicon-vias (TSVs) being disposed at a boundary between said adjacent pairs of arrays.
17. The structure as recited in claim 14 wherein said multiple different types of the dies being obtained based upon selected scribing of the common wafer include first and second pair of said arrays and one said periphery segment and said plurality of through-silicon-vias (TSVs) being disposed at opposed boundaries between said first and second pairs of arrays and the periphery segment.
18. The structure as recited in claim 14 wherein said multiple different types of the dies being obtained based upon selected scribing of the common wafer include a plurality of through-silicon-vias (TSVs) and one said periphery segment only.
19. The structure as recited in claim 14 wherein said multiple different types of the dies being obtained based upon selected scribing of the common wafer include a plurality of through-silicon-vias (TSVs) and arrays only.
20. The structure as recited in claim 14 includes a memory stack with a first die mounted on a printed circuit board (PCB), and a plurality of second dies including through-silicon-vias (TSVs) and arrays only; and said second dies mounted on said first die in the memory stack connected by said TSVs.
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US9343449B2 (en) 2012-07-06 2016-05-17 Nvidia Corporation Alternative 3D stacking scheme for DRAMs atop GPUs
US20140145331A1 (en) * 2012-11-27 2014-05-29 Samsung Electronics Co., Ltd. Multi-chip package and manufacturing method thereof
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
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