CN1574320A - 半导体封装元件及其制造方法 - Google Patents

半导体封装元件及其制造方法 Download PDF

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Publication number
CN1574320A
CN1574320A CNA2003101012313A CN200310101231A CN1574320A CN 1574320 A CN1574320 A CN 1574320A CN A2003101012313 A CNA2003101012313 A CN A2003101012313A CN 200310101231 A CN200310101231 A CN 200310101231A CN 1574320 A CN1574320 A CN 1574320A
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Prior art keywords
metallic pattern
welded gasket
metal layer
seed metal
layer
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CNA2003101012313A
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CN100376029C (zh
Inventor
宋镐旭
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种半导体封装元件及其制造方法。该半导体封装元件包括：具有多个小尺寸及以微小间距对齐的焊接垫的半导体芯片、一形成于半导体芯片上以露出焊接垫的平面层、形成于平面层上而且尺寸大于焊接垫尺寸的金属图形，并且至少某些部分的金属图形连接到焊接垫、和介于平面层和金属图形之间的种子金属层。当焊接垫具有小尺寸及以微小间距对齐时，可以使用尺寸大于焊接垫尺寸和覆盖焊接垫区域的金属图形作为焊接垫的连接部分来进行丝键合工艺。因此，可以减少焊接垫区域50～80％，使得可以增加半导体芯片中的芯片数目。

Description

半导体封装元件及其制造方法
技术领域
本发明涉及一种半导体封装元件及其制造方法，特别是可以缩小焊接垫面积的半导体封装件及其制造方法。
背景技术
一般而言，通过在晶片上进行薄膜生长工艺将芯片形成在晶片上，然后再利用晶片切割的方式分成一个一个独立的芯片。为了避免芯片被水气和杂质所污染必须进行保护工艺或模塑工艺。用于连接芯片与外部电路的引线附着在芯片，如此才算完成半导体的芯片封装。
在半导体芯片封装中，芯片占据大部分半导体芯片封装件中空间的芯片尺寸半导体封装是目前已经达到商业化程度的微小元件。芯片尺寸的半导体封装可以增加电路板上的密度和各种集成电路的集成度，例如ASIC(Application Specific Integrated Circuit，专用集成电路)。
图1是传统LOC(Lead on Chip，引线在芯片上)型半导体封装件的横截面图。
如图1所示，传统半导体封装件包括具有接触孔(未图示)的衬底12和用于填充接触孔的连接线15、具有多个焊接垫11的半导体芯片10、位于衬底12和半导体芯片10之间的胶带14、用于连接焊接垫11与连接线15一端的焊接线13、和附着在连接线15另一端的导电球(锡球)17。
在制造具有上述结构的传统半导体封装件时，半导体芯片10必须先使用胶带14附着在衬底12的上表面。然后，半导体芯片10的焊接垫11经由焊接线13电性连接到衬底12的连接线15。
然后，焊接线13和半导体芯片10被模塑件覆盖，以避免水气和杂质渗透到焊接线13和半导体芯片10中。然后，锡球17附着在衬底12的连接线15以便与外部电性连接，如此便完成半导体封装。
在相较于SRAM为更先进的存储器的高性能DRAM中，例如DDR或DDR-2，由于芯片的功能很多，因此必须增加焊接垫的数目。此外，由于芯片的尺寸持续不断地缩小，因此也必须制造微小尺寸的焊接垫，这样会使得包括丝键合步骤的封装工艺变得更困难，从而也会造成封装工艺的可靠性降低。
发明内容
为了解决现有技术所出现的上述问题，因此本发明的目的是提供一种半导体封装元件及其制造方法，可以完成具有微小尺寸焊接垫的封装工艺。
为了达到这个目的，所提供的半导体封装元件包括：一具有多个小尺寸及以微小间距对齐的焊接垫的半导体芯片、一形成在半导体芯片上以露出焊接垫的平面层、一形成在平面层上并具有尺寸大于焊接垫尺寸的金属图形、和一介于平面层和金属图形之间的种子金属层(seed metal layer)。其中至少某些部分的金属图形连接到焊接垫。
一氧化物层介于平面层和种子金属层之间以释放所产生的应力。
金属图形和种子金属层的总厚度约为1～10μm。
种子金属层具有包括Ti-NiV-Cu层的三层堆叠结构而金属图形包括Al-Ag合金或Cu-Ag合金。
焊接垫的长宽尺寸为10×10μm。
金属图形对齐焊接垫的左右方向或上下方向，或相对于焊接垫的左右方向或上下方向以锯齿状的方式交错彼此对齐。如果金属图形呈交错对齐时，金属图形具有稍微的倾斜角度。
根据本发明的另一实施例，提供一种半导体封装元件，其包括：具有多个焊接垫的半导体芯片，该焊接垫具有微小的尺寸且以微小间距对齐；一平面层，形成在半导体芯片上并具有开口以便露出焊接垫；一种子金属层和金属图形，依序形成在平面层上而且其尺寸大于焊接垫的尺寸，并且至少某些部分的种子金属层和金属图形连接到焊接垫，且种子金属层和金属图形对齐焊接垫的左右方向或上下方向；和一氧化物层，介于平面层和种子金属层之间以释放所产生的应力。
根据本发明又一实施例，提供一种半导体封装元件，其包括：具有多个焊接垫的半导体芯片，该焊接垫具有小尺寸并以微小间距对齐；一平面层，形成在半导体芯片上并具有开口以便露出焊接垫；一种子金属层和金属图形，依序形成在平面层上而且其尺寸大于焊接垫的尺寸，其中至少某些部分的种子金属层和金属图形连接到焊接垫，且种子金属层和金属图形相对于焊接垫的左右方向或上下方向以锯齿状的方式交错彼此对齐；和一氧化物层，介于平面层和种子金属层之间以释放所产生的应力。
种子金属层和金属图形交错对齐并形成稍微的倾斜角度。
根据本发明另一实施例，提供一种半导体封装元件的制造方法，该方法包括下列步骤：制备具有多个小尺寸及以微小间距对齐的焊接垫的半导体芯片，形成一平面层于半导体芯片上以露出焊接垫，形成一种子金属层在具有平面层的衬底的整个表面上，形成阻焊图形于种子金属层上使得至少某些部分的阻焊图形露出焊接垫，形成露出阻焊图形并填满形成于阻焊图形之间的间隙的金属图形，去除阻焊图形，和使用金属图形作为掩模蚀刻种子金属层。
本发明还包括在平面层和种子金属层之间形成氧化物层的步骤以释放所产生的应力。
阻焊图形的厚度为金属图形厚度的1～1.7倍。
种子金属层是由Ti、NiV和Cu层依序堆叠而成。
附图说明
下面参考附图进一步详细说明本发明，本发明的上述目的、特征和优点将更明显，在附图中：
图1是传统LOC型半导体封装件的示图；
图2是根据本发明实施例半导体封装件的平面图；
图3是图2中沿着A-B线的横截面图；
图4A～4C是根据本发明实施例半导体封装件的制造方法的横截面图；和
图5是根据本发明另一实施例半导体封装件的平面图。
具体实施方式
接下来，本发明的优选实施例将参考相关附图加以说明。在接下来的说明和图示中，将使用相同的参考标记来表示相同或是类似的元件，并省略相同或类似元件的重复说明。
图2是根据本发明实施例的半导体封装件的平面图，而图3是图2沿着A-B线的横截面图。
如图2和3所示，本发明的半导体封装件包括：具有多个焊接垫21的半导体芯片20，焊接垫21具有小尺寸并以微小间距对齐；第一和第二平面层22和23，形成于半导体芯片20上以便露出焊接垫21；一种子金属层26a和金属图形27，依序形成在第二平面层23上，并且至少其某些部分覆盖焊接垫区域；和一氧化物层24，介于第二平面层23和种子金属层26a之间以便释放所产生的应力。
至少某些部分的金属图形27对齐焊接垫的左右方向和/或上下方向并且覆盖焊接垫区域。
图4A～4C是根据本发明实施例的半导体封装件的制造方法的横截面图。
如图4A所示，在制造具有上述结构的半导体封装件时，必须先提供具有焊接垫21的半导体芯片20。此时，焊接垫的尺寸很小并以微小间距对齐，这意味着无法使用传统方法来封装焊接垫21或进行探针测试。举例来说，焊接垫21的长宽尺寸小于30×30μm，优选只有10×10μm。此外，虽然图3所示的焊接垫21为长方形，但是焊接垫21可以形成为任何形状例如圆形。
然后，第一平面层22，第二平面层23和氧化物层24依序形成在半导体芯片20的整个表面上。之后，第二平面层23和氧化物层24选择性地蚀刻以形成开口25露出焊接垫21。这时，氧化物层24释放由外部因素所产生的应力。氧化物层24是由聚酰亚胺为基的材料所制成。
然后，利用溅射工艺在整个衬底包括开口25的表面上形成种子金属层26。此时，使用具有良好导电性和黏着特性的材料，将种子金属层26制作成具有Ti-NiV-Cu层的三层堆叠结构。
接下来，在种子金属层26的整个表面上涂布阻焊薄膜(未图示)之后，进行曝光显影工艺以便形成具有预定形状的阻焊图形30。这时，阻焊图形30露出焊接垫21而且其尺寸大于焊接垫区域的尺寸。
然后，如图4B所示，包括Al-Ag合金或Cu-Ag合金的金属层(未图示)沉积在具有阻焊图形30的半导体芯片上。之后，利用蚀刻工艺蚀刻金属层，直到阻焊图形30的上表面露出来，因此形成填满形成于阻焊图形之间的空隙的金属图形27。这时，阻焊图形30的厚度约为金属图形27厚度的1～1.7倍。
此外，在封装工艺期间，连接到焊接线(未图示)的金属图形27覆盖焊接垫21，所以金属图形27的尺寸大于焊接垫21的尺寸。金属图形27对齐焊接垫21的左右方向和/或上下方向。
然后，在去除阻焊图形之后，使用金属图形27作为掩模蚀刻种子金属层，如图4C所示。这时，金属图形27和剩余种子金属层26a的总厚度约为1～10μm。
根据本发明，覆盖焊接垫区域的金属图形的尺寸大于焊接垫的尺寸，所以即使具有小尺寸的焊接垫以微小间距彼此对齐，也可以利用金属图形来进行包括丝键合工艺的封装工艺。
图5是根据本发明另一实施例的半导体封装件的平面图，其中焊接垫31以锯齿状的方式彼此交错对齐。
根据本实施例，至少某些部分的金属图形37(其为焊接垫31的连接部分)覆盖焊接垫区域，并且金属图形37的剩下部分相对于焊接垫31的左右方向或上下方向以锯齿状的方式呈水平对齐，或形成稍微倾斜角度的对齐。参考数字30表示半导体芯片。
因此，根据本发明，即使焊接垫具有小尺寸且以微小间距彼此对齐，也可以通过使用具有大于焊接垫尺寸的尺寸并覆盖焊接垫区域的金属图形，或通过使用覆盖焊接垫区域并沿特定方向延伸的金属图形，对焊接垫进行包括丝键合工艺的封装工艺。
如上所述，在由于焊接垫具有小尺寸且以微小间距彼此对齐而使得封装工艺不容易进行或操作性降低的情形时，本发明通过使用尺寸大于焊接垫尺寸和覆盖焊接垫区域的金属图形作为焊接垫的连接部分，对焊接垫进行包括丝键合工艺的封装工艺。
此外，本发明可以使用覆盖焊接垫区域并沿特定方向延伸的金属图形作为焊接垫的连接部分来进行封装工艺。
因此，本发明可以将焊接垫区域减小50～80％，因此可以增加半导体芯片中的芯片数目。
本发明上述优选实施例仅作为解释目的，对于任何本领域内的技术人员，都有可能在不偏离本权利要求的保护范围和精神的条件下进行各种修改、变更、取代或附加。

Claims (18)

1.一种半导体封装元件，包括：
一具有多个焊接垫的半导体芯片，该焊接垫具有小尺寸并以微小间距对齐；
一平面层，形成在该半导体芯片上以露出该焊接垫；
金属图形，形成在该平面层上而且具有大于该焊接垫尺寸的尺寸，并且该金属图形的至少某些部分连接到该焊接垫；以及
一种子金属层，介于该平面层和该金属图形之间。
2.如权利要求1所述的半导体封装元件，其中一氧化物层介于该平面层和该种子金属层之间以释放所产生的应力。
3.如权利要求1所述的半导体封装元件，其中该金属图形和该种子金属层的总厚度约为1～10μm。
4.如权利要求1所述的半导体封装元件，其中该种子金属层具有包括Ti-NiV-Cu层的三层堆叠结构。
5.如权利要求1所述的半导体封装元件，其中该焊接垫的长宽尺寸为10×10μm。
6.如权利要求1所述的半导体封装元件，其中该金属图形包括Al-Ag合金或Cu-Ag合金。
7.如权利要求1所述的半导体封装元件，其中该金属图形对齐该焊接垫的左右方向或上下方向。
8.如权利要求1所述的半导体封装元件，其中该金属图形以锯齿状的方式相对于该焊接垫的左右方向或上下方向彼此交错对齐。
9.如权利要求9所述的半导体封装元件，其中该金属图形以预定角度倾斜。
10.一种半导体封装元件，包括：
一具有多个焊接垫的半导体芯片，该焊接垫具有小尺寸并以微小间距对齐；
一平面层，形成在该半导体芯片上并具有开口以露出该焊接垫；
一种子金属层和金属图形，依序形成在该平面层上，而且其具有大于该焊接垫尺寸的尺寸，并且至少某些部分的该种子金属层和该金属图形连接到该焊接垫，该种子金属层和该金属图形相对于该焊接垫的左右方向或上下方向对齐；以及
一氧化物层，介于该平面层和该种子金属层之间以释放所产生的应力。
11.如权利要求10所述的半导体封装元件，其中该金属图形包括Al-Ag合金或Cu-Ag合金。
12.如权利要求10所述的半导体封装元件，其中该种子金属层具有包括Ti-NiV-Cu层的三层堆叠结构。
13.一种半导体封装元件，包括：
一具有多个焊接垫的半导体芯片，该焊接垫具有小尺寸并以微小间距对齐；
一平面层，形成在该半导体芯片上并具有开口以露出该焊接垫；
一种子金属层和金属图形，依序形成在该平面层上，而且其具有大于该焊接垫尺寸的尺寸，至少某些部分的该种子金属层和该金属图形连接到该焊接垫，该种子金属层和该金属图形以锯齿状的方式相对于该焊接垫的左右方向或上下方向彼此交错对齐；以及
一氧化物层，介于该平面层和该种子金属层之间以释放所产生的应力。
14.如权利要求13所述的半导体封装元件，其中该种子金属层和该金属图形以稍微倾斜角度交错对齐。
15.一种半导体封装元件的制造方法，该方法包括下列步骤：
提供一具有多个焊接垫的半导体芯片，该焊接垫具有小尺寸并以微小间距对齐；
形成一平面层于该半导体芯片上以露出该焊接垫；
形成一种子金属层于具有该平面层的衬底的整个表面上；
形成阻焊图形于该种子金属层上使得该阻焊图形的至少某些部分露出焊接垫；
形成金属图形，用于露出该阻焊图形并填满形成于该阻焊图形之间的间隙；
去除该阻焊图形；以及
使用该金属图形作为掩模蚀刻该种子金属层。
16.如权利要求15所述的方法，还包括在该平面层和该种子金属层之间形成一氧化物层的步骤以释放所产生的应力。
17.如权利要求15所述的方法，其中该阻焊图形的厚度为该金属图形厚度的1～1.7倍。
18.如权利要求15所述的方法，其中该种子金属层是由Ti、NiV和Cu层依序堆叠所形成的。
CNB2003101012313A 2003-05-24 2003-10-13 半导体封装元件及其制造方法 Expired - Lifetime CN100376029C (zh)

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