CN1131556C - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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CN1131556C
CN1131556C CN98105595A CN98105595A CN1131556C CN 1131556 C CN1131556 C CN 1131556C CN 98105595 A CN98105595 A CN 98105595A CN 98105595 A CN98105595 A CN 98105595A CN 1131556 C CN1131556 C CN 1131556C
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韩圣英
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Hanwha Aerospace Co Ltd
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Abstract

一种制造半导体封装的方法，包括以下步骤：将要被绝缘的各内引线附着在半导体芯片上；在所述半导体芯片上及所述各内引线的上表面上形成绝缘层，其中所述绝缘层具有一开口，通过该开口暴露出作为所述半导体芯片的连接端的焊盘和暴露出所述内引线靠近所述焊盘的末端部分；以及在所述开口中形成导电层，以将所述焊盘电连接到所述内引线的所述末端部分。

Description

半导体封装及其 制造方法
技术领域
本发明涉及半导体封装，尤其涉及半导体芯片和引线由导电层而不是由金属丝连接的半导体封装及其制造方法。
背景技术
在半导体封装中，半导体芯片由引线架支承，该引线架的每条引线把半导体芯片电连接到外部电路。
参照图1的典型半导体封装，一种存储器器件的半导体芯片12安装在衬垫11上，引线架的各内引线14用诸如双面绝缘胶带之类的粘接物质13在半导体芯片12的外围处粘附到衬垫11上。而且，半导体芯片12和内引线14用金属丝焊接，然后，所得的结构用压模材料16密封。
由于半导体芯片尺寸的减小，难于用金属丝焊接法连接小尺寸的半导体芯片与引线。即，随着半导体芯片的小型化，内引线之间的距离，即间距，减小了。因此，难于把金属丝准确地焊接到间距细微的内引线上。对于0.2毫米或更小的内引线间距，不能采用金属丝焊接法，因此不能保证半导体封装的可靠性。
发明内容
为了解决以上问题，本发明的目的是提供一种由导电层而不是由金属丝连接半导体芯片和内引线的、从而用于细微间距内引线的半导体封装制造方法，及提供一种使用该方法的半导体封装。
因此，为实现上述目的，提供一种制造半导体封装的方法，包括以下步骤：(a)要被绝缘的各内引线附着在半导体芯片边沿上；(b)在所述半导体芯片上和所述各内引线的各上表面上形成绝缘层，其中所述绝缘层具有一开口，通过此开口暴露出作为所述半导体芯片的连接端的焊盘(bonding pad)和暴露出所述内引线靠近所述焊盘的末端部分；以及(c)在所述开口中形成导电层以将所述焊盘电连接到所述内引线的所述末端部分。
这里，步骤(b)包括以下子步骤：在不存在焊盘的半导体芯片上表面上形成第一绝缘层；以及在第一绝缘层的上表面上及在除各内引线末端之外的各内引线上表面所述末端部分一侧上形成第二绝缘层。
最好，所述第二绝缘层由至少二层组成。
还有，最好第一绝缘层的上表面与内引线平齐。
按照本发明的另一方面，提供一种半导体封装，包括：各内引线；具有连接端焊盘半导体芯片，内引线附着在所述半导体芯片的边沿上；绝缘层，覆盖在除去所述内引线靠近所述焊盘的末端部分之外的所述内引线上及覆盖在所述半导体芯片上不存在所述焊盘的那一部分上的绝缘层；以及把所述各内引线的所述预定部分电连接到所述焊盘的导电层。
附图说明
通过参考附图详细叙述本发明的优选实施例，本发明的上述目的和各种优点将变得更为明显。在这些附图中：
图1是常规半导体封装的截面图；
图2至8用于说明本发明一实施例的半导体封装制造方法；以及
图9和10用于说明本发明另一实施例的半导体封装制造方法。
具体实施方式
按照本发明，半导体芯片和各内引线由导电层来电连接。现在来参考图2至8描述按照本发明一实施例的半导体封装制造方法。
参考图2，引线架的各内引线34附着在半导体芯片32表面的边沿上，在所述表面上形成一焊盘32a即电连接端。最好，所述各内引线34用诸如双面绝缘胶带之类的绝缘粘接物质来附着。
然后，如图3所示，在不存在各焊盘32a的半导体芯片32的那一部分上表面上形成第一绝缘层35。于是，通过各开口38暴露出各焊盘32a。最好，第一绝缘层35的上表面与各内引线34的上表面平齐。
最好，第一绝缘层35由聚酰胺族(polyamide group)材料形成。第一绝缘层35可用分送方法(dispensing method)形成，这种方法多次涂敷绝缘材料以形成预定的图案。作为另一种可供选择的方法，可通过粘贴具有预定图案的绝缘带来形成该绝缘层。
接着，参考图4，在第一绝缘层35的上表面上和在各内引线34的除了其末端部分34a之外的各上表面预定区域上形成各第二绝缘层36。因此，通过各开口38仍然暴露出半导体芯片32的各焊盘32a，各内引线末端的上表面部分34a也是暴露的。第二绝缘层36所用的材料及形成方法与第一绝缘层35的相同。
为方便起见，第一和第二绝缘层35和36是分别形成的。
其次，如图5所示，各第三绝缘层37形成在各第二绝缘层36的上表面之上。第三绝缘层37增加了开口38的深度。第三绝缘层37所用的材料及形成方法与第一和第二绝缘层35和36的相同。
参考图6，当第一、第二和第三绝缘层35、36和37全部形成时，把导电电镀材料注入开口38以形成导电层39。导电层39覆盖各内引线34暴露的上表面部分34a(见图4)、半导体芯片32的各焊盘32a、和各第三层37的上表面。
然后，参考图7，除去各第三绝缘层37和在各第三缘层37上的部分导电层39。这是为了避免因覆盖在第三绝缘层37上表面的导电层的过度蔓延而造成各相邻引线之间的电气短路。
于是，导电层39将各内引线34电连接到了各焊盘32a。
最后，如图8所示，已形成各第一和第二绝缘层35和36的半导体芯片32和各内引线34用压模材料31压模，从而完成了封装。此时，内引线34的另一末端向外伸出。
按照本实施例，半导体芯片32和各内引线34由导电层39而不是由各常规的金属丝连接。
本发明可采用于各种半导体封装。例如，在制造如图9所示的半导体封装中，将半导体芯片320附着到衬垫322上。即，内引线340用绝缘胶330粘贴到衬垫322的边沿而不是粘贴到半导体芯片320。
然后，用与前述方法相同的方式用导电层390连接半导体芯片320的焊盘321和内引线340。制成的半导体封装示于图10中。
按照本发明，半导体芯片和各内引线由导电层连接，因而提高了精度。因此，实现了具有细微间距的各内引线的连接，从而增加了半导体封装的可靠性。

Claims (9)

1.一种制造半导体封装的方法，包括以下步骤：
(a)将要被绝缘的各内引线附着在半导体芯片的边沿上；
(b)在所述半导体芯片上和所述各内引线的上表面上形成绝缘层，其中所述绝缘层具有一开口，通过所述开口暴露出作为所述半导体芯片的连接端的焊盘和暴露出所述内引线靠近所述焊盘的末端部分；以及
(c)在所述开口中形成导电层，以将所述焊盘电连接到所述内引线的所述末端部分。
2.如权利要求1所述的方法，其中所述步骤(a)包括由绝缘胶把所述各内引线粘附到所述半导体芯片的边沿的步骤。
3.如权利要求1所述的方法，其中所述步骤(a)包括由绝缘胶将所述内引线粘附到安放所述半导体芯片的衬垫的边沿的子步骤。
4.如权利要求1所述的方法，其中所述步骤(b)包括以下子步骤：
在不存在所述焊盘的所述半导体芯片的那一部分上表面上形成所述第一绝缘层；以及
在所述第一绝缘层的上表面上和在所述各内引线上的一部分上形成所述第二绝缘层，所述各内引线上的一部分为所述末端部分一侧除所述各内引线所述末端部分之外的上表面。
5.如权利要求4所述的方法，其中所述第二绝缘层由至少二层组成。
6.如权利要求4所述的方法，其中所述第一绝缘层的上表面与所述内引线的上表面平齐。
7.如权利要求1所述的方法，其中所述步骤(c)包括除去所述导电层的一部分和所述绝缘层的一部分的子步骤，从而通过除去所述导电层的一部分和所述绝缘层的一部分来防止接触相应内导线的各个导电层发生电气短路。
8.一种半导体封装，包括：
各内引线；
具有作为连接端的焊盘的半导体芯片，所述各内引线附着在该半导体芯片的边沿上，所述半导体芯片与所述各内引线绝缘；
绝缘层，覆盖在除所述内引线靠近所述焊盘的末端部分之外的所述内引线上及覆盖在所述半导体芯片上不存在所述焊盘的那一部分上；以及
将所述各内引线的所述末端部分电连接到所述焊盘的导电层。
9.如权利要求8所述的半导体封装，其中所述绝缘层由多层组成。
CN98105595A 1997-04-28 1998-03-16 半导体封装及其制造方法 Expired - Fee Related CN1131556C (zh)

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CN100446229C (zh) * 2004-06-10 2008-12-24 三洋电机株式会社 半导体装置及其制造方法
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JP3699271B2 (ja) 2005-09-28
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US6310389B1 (en) 2001-10-30
JPH10303227A (ja) 1998-11-13
KR19980078349A (ko) 1998-11-16

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