KR20040100770A - 반도체 패키지장치 및 그 제조 방법 - Google Patents

반도체 패키지장치 및 그 제조 방법 Download PDF

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Publication number
KR20040100770A
KR20040100770A KR1020030033237A KR20030033237A KR20040100770A KR 20040100770 A KR20040100770 A KR 20040100770A KR 1020030033237 A KR1020030033237 A KR 1020030033237A KR 20030033237 A KR20030033237 A KR 20030033237A KR 20040100770 A KR20040100770 A KR 20040100770A
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South Korea
Prior art keywords
bonding pad
semiconductor package
metal layer
seed metal
metal pattern
Prior art date
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KR1020030033237A
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English (en)
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KR100541677B1 (ko
Inventor
송호욱
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020030033237A priority Critical patent/KR100541677B1/ko
Priority to US10/655,206 priority patent/US6998720B2/en
Priority to TW092124529A priority patent/TWI234247B/zh
Priority to CNB2003101012313A priority patent/CN100376029C/zh
Publication of KR20040100770A publication Critical patent/KR20040100770A/ko
Priority to US11/315,061 priority patent/US7226814B2/en
Application granted granted Critical
Publication of KR100541677B1 publication Critical patent/KR100541677B1/ko

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Abstract

본 발명은 본딩패드영역을 최소화할 수 있는 반도체 패키지 장치 및 그 제조 방법에 관해 개시한 것이다.
개시된 본 발명에 따른 반도체 패키지장치는 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩과, 반도체 칩 위에 형성되며 본딩패드를 노출시키는 평탄화막과, 평탄화막 위에 형성되며 적어도 일부분이 본딩패드와 연결되고 본딩패드보다 크기가 더 크게 구현되는 금속 패턴과, 평탄화막과 금속 패턴 사이에 개재되는 씨드메탈층을 포함한다.
본 발명에서는 본딩패드가 미세 크기 및 미세 간격을 가진 경우, 상기 본딩패드와 연결되는 연결부로서, 적어도 상기 본딩패드를 덮고 상기 본딩패드보다 사이즈가 큰 금속 패턴을 이용하여 와이어 본딩 공정을 수행 가능하다. 따라서, 본딩패드영역을 50∼80% 이상 감소시킬 수 있으며, 이에 따라 반도체 칩 내 칩수를 증가시킬 수 있다.

Description

반도체 패키지장치 및 그 제조 방법{semiconductor package device and fabrication method thereof}
본 발명은 반도체 패키지 및 그 제조 방법에 관한 것으로, 보다 구체적으로는 본딩패드영역을 최소화할 수 있는 반도체 패키지장치 및 그 제조 방법에 관한 것이다.
일반적으로 널리 알려진 바와 같이, 웨이퍼의 박막 성장 기법에 의해 제조된 칩(chip)을 웨이퍼로부터 절단(sawing)분리한 다음, 분리된 칩을 실드(shield)나 몰딩(molding)으로 외부의 습기나 불순물로부터 보호되고 또한 외부회로와의 접속을 위한 리드를 부착한 패키지 형태로 상품화된다.
이러한 패키지중 대부분의 공간을 칩이 차지하는 정도의 크기로 몰딩되는 칩크기의 패키지는 그 자체가 단일한 미소 소자(micro device)로 상품화되어 회로기판에 있어서의 실장밀도를 높이고 응용 주문형 집적회로(ASIC:Application Specific IC)등 각종 집적회로에서의 집적도를 높이는 데 유용하다.
도 1은 종래 기술에 따른 엘오씨(Lead On Chip)타입의 반도체 패키지의 단면도이다.
종래 기술에 따른 반도체 패키지는, 도 1에 도시된 바와 같이, 관통홀(미도시) 및 관통홀을 채우는 배선(15)이 각각 형성된 기판(12)과, 다수개의 본딩패드(11)가 구비된 반도체 칩(10)과, 기판(12)과 반도체 칩(10) 사이에 개재되는 접착테이프(14)와, 본딩패드(11)와 배선(15)의 일단을 연결시키는 본딩와이어(13)와, 배선(15)의 타단에 부착되는 도전성 볼(17)로 구성된다.
상기 구성을 갖는 종래 기술에 따른 반도체 패키지의 제조방법은, 먼저, 기판(12) 위에 접착테이프(14)를 이용하여 반도체 칩(10)을 부착시킨 다음, 반도체 칩(10)의 본딩패드(11)와 기판(12)의 배선(15)과의 전기적 연결을 위하여 본딩와이어(13)를 형성한다.
이 후, 외부의 먼지나 습기를 차단하기 위해, 본딩와이어(13) 및 반도체칩(10)을 덮도록 몰딩체(19)를 형성한 다음, 외부와의 전기적 연결을 위하여 기판(12)의 배선(15) 상에 솔더볼(17)을 부착시키어 패키지 제조를 완료한다.
에스램(SRAM)에서 진보된 메모리소자인 디디알(DDR) 또는 디디알2(DDR2)등과 같은 고성능 디램(DRAM)은 칩의 여러 기능(function)이 늘어나게 되고, 이는 곧 패드수에 있어서 많은 증가를 요구하게 된다. 또한, 칩 크기의 감소를 감안하면, 본딩패드의 미세화는 더욱 진행하게 되어 와이어본딩 등의 패키징 공정은 점점 더 어려워지고 신회성을 확보하기가 곤란한 문제점이 있었다.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본딩패드가 미세화된 경우에도 패키징 공정을 적용할 수 있는 반도체 패키지장치 및 그 제조 방법을 제공함에 있다.
도 1은 종래 기술에 따른 반도체 패키지 및 그 제조 방법을 설명하기 위한 공정단면도.
도 2는 본 발명의 일실시예에 따른 따른 반도체 패키지장치를 보인 반도체 칩 평면도.
도 3은 도 3의 AB선을 따라 절단한 단면도.
도 4a 내지 도 4c는 본 발명의 일실시예에 따른 반도체 패키지장치의 제조 방법을 설명하기 위한 공정단면도.
도 5은 본 발명의 다른 실시예에 따른 따른 반도체 패키지장치를 보인 평면도.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 패키지장치는 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩과, 반도체 칩 위에 형성되며 본딩패드를 노출시키는 평탄화막과, 평탄화막 위에 형성되며 적어도 일부분이 본딩패드와 연결되고 본딩패드보다 크기가 크게 구현되는 금속 패턴과, 평탄화막과 금속 패턴 사이에 개재되는 씨드메탈층을 포함한 것을 특징으로 한다.
상기 평탄화막과 씨드메탈층 사이에는 스트레스 완화용 산화막이 개재된다.
상기 금속패턴과 상기 씨드 메탈층의 총두께는 1∼10㎛를 가진다.
상기 씨드 메탈층은 Ti/NiV/Cu의 3중 적층막 구조를 가지며, 금속 패턴은 알루미늄-은(Al-Ag) 합금 및 구리-은(Cu-Ag) 합금 중 어느 하나의 재질을 이용한다.
상기 본딩패드는 10 ×10㎛ (가로×세로)크기를 가진다.
상기 금속 패턴은 상기 본딩패드를 기준으로 좌우 및 상하 중 어느 하나의 방향으로 배열된 구조를 가지거나, 또는 상기 본딩패드를 기준으로 좌우 및 상하 중 어느 하나의 방향으로 하나씩 교차 배열된다. 이때, 상기 교차 배열은 비스듬한 경사각을 가지고 배열된다.
본 발명에 따른 반도체 패키지장치는 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩과, 반도체 칩 위에 형성되며 본딩패드를 노출시키는 개구부를 가진 평탄화막과, 평탄화막 위에 차례로 형성되며 적어도 일부분이 본딩패드를 덮고 본딩패드를 기준으로 좌우 및 상하 방향으로 배열된 구조를 이루는 씨드메탈층 및 금속 패턴과, 평탄화막과 씨드메탈층 사이에 개재된 스트레스 완화용 산화막을 포함한 것을 특징으로 한다.
본 발명에 따른 반도체 패키지장치는 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩과, 반도체 칩 위에 형성되며 본딩패드를 노출시키는 개구부를 가진 평탄화막과, 평탄화막 위에 차례로 형성되며 적어도 일부분이 본딩패드를 덮고 본딩패드를 기준으로 좌우 및 상하 중 어느 하나의 방향으로 하나씩 교차 배열된 씨드메탈층 및 금속 패턴과, 평탄화막과 씨드메탈층 사이에 개재된 스트레스 완화용 산화막을 포함한 것을 특징으로 한다.
상기 씨드메탈층 및 금속 패턴은 비스듬한 경사각을 가지고 교차배열된다.
본 발명에 따른 반도체 패키지장치의 제조 방법은 미세 간격 및 미세 크기로배열된 본딩패드가 다수개 구비된 반도체 칩을 제공하는 단계와, 반도체 칩 위에 본딩패드를 노출시키는 개구부를 가진 평탄화막을 형성하는 단계와, 평탄화막이 구비된 기판 전면에 씨드메탈층을 형성하는 단계와, 씨드메탈층 위에 적어도 일부분이 본딩패드를 노출시키는 솔더레지스트 패턴을 형성하는 단계와, 결과물 상에 솔더 레지스트 패턴 표면을 노출시키고 솔더 레지스트 패턴 사이를 채우는 금속 패턴을 형성하는 단계와, 솔더 레지스트 패턴을 제거하는 단계와, 금속 패턴을 마스크로 하여 씨드메탈층을 식각하는 단계를 포함한 것을 특징으로 한다.
상기 평탄화막과 상기 씨드메탈층 사이에 스트레스 완화용 산화막을 개재시키는 단계를 추가한다.
상기 솔더 레지스트 패턴은 상기 금속 패턴보다 1∼1.7배 두껍게 형성한다. 상기 씨드 메탈층은 Ti막, NiV막 및 Cu막을 차례로 적층하여 형성한다.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.
도 2는 본 발명의 일실시예에 따른 따른 반도체 패키지장치를 보인 반도체 칩의 평면도이다. 또한, 도 3은 도 3의 AB선을 따라 절단한 단면도이다.
본 발명에 따른 반도체 패키지는, 도 2 및 도 3에 도시된 바와 같이, 미세 간격 및 미세 크기로 배열된 본딩패드(21)가 다수개 구비된 반도체 칩(20)과, 반도체 칩(20) 위에 형성되며 본딩패드(21)를 노출시키는 각각의 제 1및 제 2평탄화막(22)(23)과, 제 2 평탄화막(23) 위에 차례로 형성되며 적어도 일부분이 본딩패드영역을 덮는 씨드메탈층 및 금속 패턴(26a)(27)과, 제 2평탄화막(23)과 씨드메탈층(26a) 사이에 개재된 스트레스 완화용 산화막(24)을 포함하여 구성된다.
이때, 상기 금속패턴(27)은 적어도 일부분은 본딩패드영역을 덮으면서 좌우 및/또는 상하 방향으로 배열된 구조를 가진다.
도 4a 내지 도 4c는 본 발명에 따른 반도체 패키지의 제조 방법을 설명하기 위한 공정단면도이다.
상기 구성을 가진 본 발명에 따른 반도체 패키지의 제조 방법은, 도 4a에 도시된 바와 같이, 본딩패드(21)들이 구비된 반도체 칩(20)을 제공한다. 이때, 상기 본딩패드(21)들은 미세 크기 및 미세 간격을 가진 것으로서, 통상적인 방법으로는 패키징 또는 프로브 테스트가 불가능한 배열 상태를 의미한다. 예를 들면, 상기 본딩패드(2)들은 가로×세로가 30×30㎛ 이하의 크기, 바람직하게는 10×10㎛ 크기를 가진다. 또한, 상기 본딩패드(21)는, 도 3에서는 사각 형상인 것을 보였으나, 상기 사각 형상 이외에 원형 형상을 가질 수도 있다.
이어, 상기 반도체 칩 전면에 제 1평탄화막(22), 제 2평탄화막(23) 및 스트레스 완화용 산화막(24)을 차례로 형성한 다음, 이들 막을 선택 식각하여 상기 본딩패드(21)를 노출시키는 개구부(25)를 형성한다. 이때, 상기 스트레스 완화용 산화막(24)은 외부의 충격 등으로 인한 스트레스를 완화시켜 주는 역할을 하는 것으로서, 주로 폴리이미드(polyimide) 계열을 이용한다.
그런 다음, 상기 개구부(25)을 포함한 기판 전면에 스퍼터링 방식을 적용하여 씨드메탈층(seed metal layer)(26)을 형성한다. 이때, 상기 씨드메탈층(26)은 전도성 및 접착력이 우수한 물질로서, Ti/NiV/Cu의 3중 적층 구조를 이용한다.
이 후, 상기 씨드메탈층 전면에 네거티브형 솔더 레지스트막(미도시)을 도포한 다음, 노광 및 현상 공정을 진행하여 소정 형상의 솔더 레지스트 패턴(30)을 형성한다. 이때, 상기 솔더 레지스트 패턴(30)은 본딩패드(21)를 노출시키며, 적어도 본딩패드영역의 사이즈보다는 크게 패터닝한다.
이어, 도 4b에 도시된 바와 같이, 상기 솔더 레지스트 패턴(30)이 구비된 반도체 칩 위에 알루미늄-은(Al-Ag) 합금 또는 구리-은(Cu-Ag) 합금 등을 이용한 금속막(미도시)을 증착한 다음, 상기 솔더 레지스트 패턴(30) 상면을 노출시키는 시점까지 금속막을 식각하여 상기 솔더 레지스트 패턴들 사이의 공간을 채우는 금속 패턴(27)을 형성한다. 이때, 상기 솔더 레지스트 패턴(30)은 상기 금속 패턴(27)보다 1∼1.7배 두껍게 형성한다.
한편, 상기 금속 패턴(27)은 이 후의 패키징 공정 시 본딩와이어(미도시)와 연결되는 영역으로서, 적어도 본딩패드(21)를 덮으면서 상기 본딩패드(21)의 사이즈보다 크게 제작되며, 상기 본딩패드(21)를 기준으로 좌우 및/또는 상하 중 어느 하나의 방향으로 배열된다.
그런 다음, 상기 솔더 레지스트 패턴을 제거한 다음, 도 4c에 도시된 바와 같이, 상기 금속 패턴(27)을 마스크로 하여 상기 씨드메탈층을 식각한다. 이때, 상기 금속 패턴(27) 및 잔류된 씨드 메탈층의 총두께는 1∼10㎛로 한다.
본 발명에서는 본딩패드가 미세 크기 및 미세 간격을 가진 경우, 상기 본딩패드영역을 덮고 적어도 상기 본딩패드의 크기보다 크게 제작된 금속 패턴을 형성함으로써, 상기 금속 패턴을 이용하여 와이어본딩 등의 패키징 공정을 진행할 수있다.
도 5은 본 발명의 다른 실시예에 따른 반도체 패키지장치에서, 본딩패드 연결부의 보인 반도체 칩 평면도로서, 지그재그 형태로 배열된 것을 보인 것이다.
본 발명의 다른 실시예에 따른 반도체 패키지의 본딩 패드 연결부인 금속 패턴(37)은, 적어도 일부분은 본딩패드영역을 덮고 타부분은 본딩패드(31)를 기준으로 좌우 또는 상하 방향으로 수평 또는 비스듬한 경사각을 가지고 하나씩 교차 배열(지그재그 형태)된다. 미설명된 도면부호 30은 반도체 칩을 각각 나타낸 것이다.
본 발명에 따르면, 본딩패드가 미세 크기 및 미세 간격을 가진 경우, 적어도 본딩패드영역을 덮고 본딩패드의 크기보다 크게 제작된 금속패턴을 이용하거나, 적어도 본딩패드영역을 덮고 타부분으로 길게 배열되도록 제작된 금속 패턴을 이용하여 상기 본딩패드와의 와이어본딩 등의 패키징 공정을 진행할 수 있다.
이상에서와 같이, 본 발명은 본딩패드가 미세 크기 및 미세 간격을 가지고 있어 패키징 공정이 불가능하거나 작업성이 저하되는 경우, 상기 본딩패드와 연결되는 연결부로서, 적어도 본딩패드영역을 덮고 본딩패드의 사이즈보다 크게 제작된 금속패턴을 이용하여 상기 본딩패드와의 와이어본딩 등의 패키징 공정을 진행할 수 있다.
또는, 본 발명은 상기 연결부로서, 적어도 본딩패드영역을 덮고 타부분으로 길게 배열되도록 제작된 금속 패턴을 이용하여 패키징 공정을 진행할 수 있다.
따라서, 본 발명에서는 본딩패드영역을 50∼80% 이상 감소시킬 수 있으며,이에 따라 반도체 칩 내 칩수를 증가시킬 수 있는 이점이 있다.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.

Claims (18)

  1. 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩과,
    상기 반도체 칩 위에 형성되며, 상기 본딩패드를 노출시키는 평탄화막과,
    상기 평탄화막 위에 형성되며, 적어도 일부분이 상기 본딩패드와 연결되고 상기 본딩패드보다 크기가 크게 구현되는 금속 패턴과,
    상기 평탄화막과 상기 금속 패턴 사이에 개재되는 씨드메탈층을 포함한 것을 특징으로 하는 반도체 패키지장치.
  2. 제 1항에 있어서, 상기 평탄화막과 상기 씨드메탈층 사이에는 스트레스 완화용 산화막이 개재된 것을 특징으로 하는 반도체 패키지장치.
  3. 제 1항에 있어서, 상기 금속패턴과 상기 씨드 메탈층의 총두께는 1∼10㎛인 것을 특징으로 하는 반도체 패키지장치.
  4. 제 1항에 있어서, 상기 씨드 메탈층은 Ti/NiV/Cu의 3중 적층막 구조를 가진 것을 특징으로 하는 반도체 패키지장치.
  5. 제 1항에 있어서, 상기 본딩패드는 10 ×10㎛(가로×세로) 크기를 가진 것을 특징으로 하는 반도체 패키지장치.
  6. 제 1항에 있어서, 상기 금속 패턴의 재질은 알루미늄-은(Al-Ag) 합금 및 구리-은(Cu-Ag) 합금 중 어느 하나인 것을 특징으로 하는 반도체 패키지장치.
  7. 제 1항에 있어서, 상기 금속 패턴은 상기 본딩패드를 기준으로 좌우 및 상하 중 어느 하나의 방향으로 배열된 구조를 가진 것을 특징으로 하는 반도체 패키지장치.
  8. 제 1항에 있어서, 상기 금속 패턴은 상기 본딩패드를 기준으로 좌우 및 상하 중 어느 하나의 방향으로 하나씩 교차 배열된 것을 특징으로 하는 반도체 패키지장치.
  9. 제 8항에 있어서, 상기 금속 패턴은 비스듬한 경사각을 가지고 교차배열된 것을 특징으로 하는 반도체 패키지장치.
  10. 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩과,
    상기 반도체 칩 위에 형성되며, 상기 본딩패드를 노출시키는 개구부를 가진 평탄화막과,
    상기 평탄화막 위에 차례로 형성되며, 적어도 일부분이 상기 본딩패드와 연결되고 상기 본딩패드보다 크기가 크게 구현되며, 상기 본딩패드를 기준으로 좌우및 상하 방향으로 배열된 구조를 이루는 씨드메탈층 및 금속 패턴과,
    상기 평탄화막과 상기 씨드메탈층 사이에 개재된 스트레스 완화용 산화막을 포함한 것을 특징으로 하는 반도체 패키지장치.
  11. 제 10항에 있어서, 상기 금속 패턴의 재질은 알루미늄-은(Al-Ag) 합금 및 구리-은(Cu-Ag) 합금 중 어느 하나인 것을 특징으로 하는 반도체 패키지장치.
  12. 제 10항에 있어서, 상기 씨드 메탈층은 Ti/NiV/Cu의 3중 적층막 구조를 가진 것을 특징으로 하는 반도체 패키지장치.
  13. 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩과,
    상기 반도체 칩 위에 형성되며, 상기 본딩패드를 노출시키는 개구부를 가진 평탄화막과,
    상기 평탄화막 위에 차례로 형성되며, 적어도 일부분이 상기 본딩패드와 연결되고 상기 본딩패드의 크기보다 크게 구현되며, 상기 본딩패드를 기준으로 좌우 및 상하 중 어느 하나의 방향으로 하나씩 교차 배열된 씨드메탈층 및 금속 패턴과,
    상기 평탄화막과 상기 씨드메탈층 사이에 개재된 스트레스 완화용 산화막을 포함한 것을 특징으로 하는 반도체 패키지장치.
  14. 제 13항에 있어서, 상기 씨드메탈층 및 금속 패턴은 비스듬한 경사각을 가지고 교차배열된 것을 특징으로 하는 반도체 패키지장치.
  15. 미세 간격 및 미세 크기로 배열된 본딩패드가 다수개 구비된 반도체 칩을 제공하는 단계와,
    상기 반도체 칩 위에 상기 본딩패드를 노출시키는 개구부를 가진 평탄화막을 형성하는 단계와,
    상기 평탄화막이 구비된 기판 전면에 씨드메탈층을 형성하는 단계와,
    상기 씨드메탈층 위에 적어도 일부분이 상기 본딩패드를 노출시키는 솔더레지스트 패턴을 형성하는 단계와,
    상기 결과물 상에 솔더 레지스트 패턴 표면을 노출시키고, 상기 솔더 레지스트 패턴 사이를 채우는 금속 패턴을 형성하는 단계와,
    상기 솔더 레지스트 패턴을 제거하는 단계와,
    상기 금속 패턴을 마스크로 하여 상기 씨드메탈층을 식각하는 단계를 포함한 것을 특징으로 하는 반도체 패키지장치의 제조 방법.
  16. 제 15항에 있어서, 상기 평탄화막과 상기 씨드메탈층 사이에 스트레스 완화용 산화막을 개재시키는 단계를 추가하는 것을 특징으로 하는 반도체 패키지장치의 제조 방법.
  17. 제 15항에 있어서, 상기 솔더 레지스트 패턴은 상기 금속 패턴보다 1∼1.7배두껍게 형성하는 것을 특징으로 하는 반도체 패키지장치의 제조 방법.
  18. 제 15항에 있어서, 상기 씨드 메탈층은 Ti막, NiV막 및 Cu막을 차례로 적층하여 형성하는 것을 특징으로 하는 반도체 패키지장치의 제조 방법.
KR1020030033237A 2003-05-24 2003-05-24 반도체 패키지장치 및 그 제조 방법 KR100541677B1 (ko)

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TW092124529A TWI234247B (en) 2003-05-24 2003-09-05 Semiconductor package device and method for fabricating the same
CNB2003101012313A CN100376029C (zh) 2003-05-24 2003-10-13 半导体封装元件及其制造方法
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