JP5340047B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP5340047B2 JP5340047B2 JP2009140880A JP2009140880A JP5340047B2 JP 5340047 B2 JP5340047 B2 JP 5340047B2 JP 2009140880 A JP2009140880 A JP 2009140880A JP 2009140880 A JP2009140880 A JP 2009140880A JP 5340047 B2 JP5340047 B2 JP 5340047B2
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Description
本発明の第1の実施形態に係る半導体集積回路装置及びその設計方法について図面を参照しながら詳細に説明する。
図3は第1の実施形態の第1変形例に係る半導体集積回路装置の平面構成を示している。
第2変形例として、図3に示した、四角格子状に配置された第1のパッド301と、千鳥状に配置された第2のパッド302とについて、パッドの表層部分ではなく、パッドと接続された下側の金属層(下位金属層)の形状を、それぞれ半導体チップ100の一辺と平行な四角形、及び該四角形を45°回転した四角形とすることによっても、第1変形例と同様の効果を得ることができる。なお、この場合に、各パッド301、302の表層部分(上位金属層)の形状は、四角形、多角形又は円形等の形状変更が可能となる。
以下、第1の実施形態に係る半導体集積回路装置の設計方法を図6のフローチャートと共に説明する。
図8は第1の実施形態の第4変形例に係る半導体集積回路装置の一隅部の平面構成を示している。
以下、本発明の第2の実施形態に係る半導体集積回路装置及びその設計方法について、図面を参照しながら詳細に説明する。
図13は第2の実施形態の第1変形例に係る半導体集積回路装置の要部の平面構成を示している。
図14は第2の実施形態の第2変形例に係る半導体集積回路装置の要部の平面構成を示している。
図15は第2の実施形態の第3変形例に係る半導体集積回路装置の平面構成を示している。
図16は第2の実施形態の第4変形例に係る半導体集積回路装置の平面構成を示している。
101 第1のパッド
102 第2のパッド
103 第1のパッド間配線
104 第2のパッド間配線
105 入出力セル
201 保護膜
202 バンプ
205 金属めっき層
301 第1のパッド
302 第2のパッド
302a 交点
411 配線
412 パッド
413 パッド
414 パッド
501 アナログコア
502 パッド
601 パッド
602 入出力セル
603 パッド間配線
702 (第1の)入出力セル
703 第2の入出力セル
704 第3の入出力セル
705 電源容量セル
706 電源配線
707 ESD保護セル
Claims (6)
- 辺に沿って複数の入出力セルを有する半導体チップと、
前記半導体チップの表面上に形成された複数のパッドと、
前記半導体チップの表面上に形成され、且つ前記複数の入出力セルの少なくとも一部と前記複数のパッドの少なくとも一部とを電気的に接続する配線とを備え、
前記複数のパッドは、前記半導体チップの中央部において四角格子状に配置された第1のパッド群と、前記半導体チップの4つの隅部において千鳥状に配置された第2のパッド群と、前記半導体チップの2つの隅部に挟まれた四角格子状の第3のパッド群とからなり、
前記第1のパッド群及び前記第3のパッド群のパッドの形状は四角形であり、前記第2のパッド群のパッドの形状は四角形を45°回転した形状であり、
パッド下部領域又はパッド周辺部の指定面積領域において、アナログ素子が存在する領域にはパッドが配置されないことを特徴とする半導体集積回路装置。 - 前記半導体チップの前記パッド下部領域又は前記パッド周辺部の指定面積領域において、アナログ素子が存在する領域にはパッドが配置されないことを特徴とする請求項1に記載の半導体集積回路装置。
- 前記半導体チップの前記パッド下部領域又は前記パッド周辺部の指定面積領域において、配線密度の高い領域にはパッドが配置されないことを特徴とする請求項1又は2に記載の半導体集積回路装置。
- 前記複数のパッドについて、前記半導体チップの外周一列、又は二列以上の複数列が電源端子であることを特徴とする請求項1〜3のいずれか1項に記載の半導体集積回路装置。
- 前記複数のパッドについて、四角格子状に配置されたパッドは電源端子として使用し、千鳥状に配置された領域のパッドは信号端子として使用することを特徴とする請求項1〜4のいずれか1項に記載の半導体集積回路装置。
- 前記第1のパッド群及び前記第3のパッド群のパッドの表層金属層の形状は四角形であり、前記第2のパッド群のパッドの表層第二金属層又はその下位金属層の形状は四角形を45°回転した形状であることを特徴とする請求項1〜5のいずれか1項に記載の半導体集積回路装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009140880A JP5340047B2 (ja) | 2009-06-12 | 2009-06-12 | 半導体集積回路装置 |
CN201080010258.XA CN102341905B (zh) | 2009-06-12 | 2010-01-27 | 半导体集成电路装置及其设计方法 |
PCT/JP2010/000442 WO2010143326A1 (ja) | 2009-06-12 | 2010-01-27 | 半導体集積回路装置及びその設計方法 |
US13/220,860 US8456025B2 (en) | 2009-06-12 | 2011-08-30 | Semiconductor chip having staggered arrangement of bonding pads |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009140880A JP5340047B2 (ja) | 2009-06-12 | 2009-06-12 | 半導体集積回路装置 |
Publications (3)
Publication Number | Publication Date |
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JP2010287758A JP2010287758A (ja) | 2010-12-24 |
JP2010287758A5 JP2010287758A5 (ja) | 2011-02-10 |
JP5340047B2 true JP5340047B2 (ja) | 2013-11-13 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009140880A Expired - Fee Related JP5340047B2 (ja) | 2009-06-12 | 2009-06-12 | 半導体集積回路装置 |
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US (1) | US8456025B2 (ja) |
JP (1) | JP5340047B2 (ja) |
CN (1) | CN102341905B (ja) |
WO (1) | WO2010143326A1 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US8627256B2 (en) * | 2011-04-25 | 2014-01-07 | Lsi Corporation | Method for computing IO redistribution routing |
US20130256883A1 (en) * | 2012-03-27 | 2013-10-03 | Intel Mobile Communications GmbH | Rotated semiconductor device fan-out wafer level packages and methods of manufacturing rotated semiconductor device fan-out wafer level packages |
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