JP4685601B2 - 実装基板および半導体装置 - Google Patents
実装基板および半導体装置 Download PDFInfo
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- JP4685601B2 JP4685601B2 JP2005331708A JP2005331708A JP4685601B2 JP 4685601 B2 JP4685601 B2 JP 4685601B2 JP 2005331708 A JP2005331708 A JP 2005331708A JP 2005331708 A JP2005331708 A JP 2005331708A JP 4685601 B2 JP4685601 B2 JP 4685601B2
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- JP
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- Prior art keywords
- semiconductor chip
- mounting substrate
- pattern
- mounting
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 96
- 239000000758 substrate Substances 0.000 title claims description 53
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 7
- 238000009751 slip forming Methods 0.000 claims description 5
- 239000012466 permeate Substances 0.000 claims 2
- 230000000694 effects Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000035515 penetration Effects 0.000 description 5
- 230000002349 favourable effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09772—Conductors directly under a component but not electrically connected to the component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
101 絶縁層
102,102A,102B,102C 絶縁パターン(ソルダーレジストパターン)
103 ダミーパターン(ソルダーレジストパターン)
104,104A,104B 接続パッド
200 半導体チップ
201 チップ本体
202,202A,202B 接続部
Claims (9)
- 半導体チップをフリップチップ実装する実装基板であって、
前記半導体チップが接続される複数の接続パッドと、
前記接続パッドの一部を覆うように形成される絶縁パターンと、
前記半導体チップの下に浸透されるアンダーフィルの流れを制御する複数のダミーパターンと、を有し、
前記複数のダミーパターンが、互い違いの格子状に配列され、
前記絶縁パターンと、前記ダミーパターンは、ソルダーレジスト材料よりなることを特徴とする実装基板。 - 前記複数の接続パッドは、前記半導体チップの周縁部に対応して略四角形に配列される第1の接続パッドと、前記第1の接続パッドに囲まれるように設置される第2の接続パッドとを含むことを特徴とする請求項1記載の実装基板。
- 前記第2の接続パッドは、前記半導体チップの電源ラインまたは接地ラインに接続されることを特徴とする請求項2記載の実装基板。
- 前記絶縁パターンは、複数の前記第1の接続パッドの第1の端部を覆うように連続的に形成される第1の絶縁パターンと、複数の前記第1の接続パッドの第2の端部を覆うように連続的に形成される第2の絶縁パターンと、複数の前記第2の接続パッドの端部を個別に覆うように形成される複数の第3の絶縁パターンと、を含むことを特徴とする請求項2または3記載の実装基板。
- 前記ダミーパターンは、前記第2の接続パッドの近傍に配置されることを特徴とする請求項4記載の実装基板。
- 前記ダミーパターンは、平面視した場合に略長方形状に形成されることを特徴とする請求項1乃至5のうち、いずれか1項記載の実装基板。
- 前記ダミーパターンを平面視した場合の、前記略長方形状の長手方向である第1の方向の一辺の長さをa、当該第1の方向に隣接して設置されるダミーパターンの間隔をXとした場合、0.1X≦a≦10Xを満たすことを特徴とする請求項6記載の実装基板。
- 前記ダミーパターンを平面視した場合の、前記第1の方向に直交する第2の方向の一辺の長さをbとした場合、0.1X≦b≦10Xを満たすことを特徴とする請求項7記載の実装基板。
- 半導体チップが実装基板にフリップチップ実装されてなる半導体装置であって、
前記実装基板は、
前記半導体チップが接続される複数の接続パッドと、
前記接続パッドの一部を覆うように形成される絶縁パターンと、
前記半導体チップの下に浸透されるアンダーフィルの流れを制御する複数のダミーパターンと、を有し、
前記複数のダミーパターンが、互い違いの格子状に配列され、
前記絶縁パターンと、前記ダミーパターンは、ソルダーレジスト材料よりなることを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005331708A JP4685601B2 (ja) | 2005-11-16 | 2005-11-16 | 実装基板および半導体装置 |
US11/560,076 US7838998B2 (en) | 2005-11-16 | 2006-11-15 | Mounting substrate and semiconductor device |
TW095142178A TW200746378A (en) | 2005-11-16 | 2006-11-15 | Mounting substrate and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005331708A JP4685601B2 (ja) | 2005-11-16 | 2005-11-16 | 実装基板および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007142037A JP2007142037A (ja) | 2007-06-07 |
JP4685601B2 true JP4685601B2 (ja) | 2011-05-18 |
Family
ID=38057301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005331708A Active JP4685601B2 (ja) | 2005-11-16 | 2005-11-16 | 実装基板および半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7838998B2 (ja) |
JP (1) | JP4685601B2 (ja) |
TW (1) | TW200746378A (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100730077B1 (ko) * | 2005-11-25 | 2007-06-19 | 삼성전기주식회사 | 이미지센서 모듈과 카메라모듈 패키지 |
US8410571B2 (en) * | 2006-07-12 | 2013-04-02 | United Microelectronics Corp. | Layout of dummy patterns |
JP2008227076A (ja) * | 2007-03-12 | 2008-09-25 | Nec Electronics Corp | 半導体装置 |
US8301624B2 (en) * | 2009-03-31 | 2012-10-30 | Yahoo! Inc. | Determining user preference of items based on user ratings and user features |
JP5340047B2 (ja) * | 2009-06-12 | 2013-11-13 | パナソニック株式会社 | 半導体集積回路装置 |
US8536718B2 (en) * | 2010-06-24 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit packaging system with trenches and method of manufacture thereof |
JP6214030B2 (ja) * | 2013-06-27 | 2017-10-18 | 太陽誘電株式会社 | 回路基板、回路モジュール、回路基板の製造方法及び回路モジュールの製造方法 |
KR102214512B1 (ko) * | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
US11152532B2 (en) * | 2017-07-26 | 2021-10-19 | Oki Electric Industry Co., Ltd. | Method of manufacturing driven element chip, driven element chip, exposing device, and image forming apparatus |
TW202343485A (zh) * | 2017-11-29 | 2023-11-01 | 日商大日本印刷股份有限公司 | 配線基板及配線基板之製造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08298269A (ja) * | 1995-04-25 | 1996-11-12 | Toshiba Microelectron Corp | 半導体装置及びその製造方法 |
JPH0945731A (ja) * | 1995-05-22 | 1997-02-14 | Hitachi Chem Co Ltd | 半導体チップの接続構造及びこれに用いる配線基板 |
JPH09232474A (ja) * | 1996-02-27 | 1997-09-05 | Sharp Corp | Fpc上のベアチップicの樹脂封止構造およびその製造方法 |
JP2000208544A (ja) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | ベアicチップおよび半導体装置 |
JP2003023035A (ja) * | 2001-07-05 | 2003-01-24 | Sharp Corp | 半導体装置 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
JP2004221320A (ja) * | 2003-01-15 | 2004-08-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015554A (ja) | 1999-06-30 | 2001-01-19 | Fujitsu Ten Ltd | 基板の部品実装構造 |
JP2004207296A (ja) | 2002-12-24 | 2004-07-22 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2005175261A (ja) | 2003-12-12 | 2005-06-30 | Fujitsu Ten Ltd | 基板の電子部品実装構造および方法 |
-
2005
- 2005-11-16 JP JP2005331708A patent/JP4685601B2/ja active Active
-
2006
- 2006-11-15 TW TW095142178A patent/TW200746378A/zh unknown
- 2006-11-15 US US11/560,076 patent/US7838998B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08298269A (ja) * | 1995-04-25 | 1996-11-12 | Toshiba Microelectron Corp | 半導体装置及びその製造方法 |
JPH0945731A (ja) * | 1995-05-22 | 1997-02-14 | Hitachi Chem Co Ltd | 半導体チップの接続構造及びこれに用いる配線基板 |
JPH09232474A (ja) * | 1996-02-27 | 1997-09-05 | Sharp Corp | Fpc上のベアチップicの樹脂封止構造およびその製造方法 |
JP2000208544A (ja) * | 1999-01-14 | 2000-07-28 | Toshiba Corp | ベアicチップおよび半導体装置 |
JP2003023035A (ja) * | 2001-07-05 | 2003-01-24 | Sharp Corp | 半導体装置 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
JP2004221320A (ja) * | 2003-01-15 | 2004-08-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW200746378A (en) | 2007-12-16 |
US20070108628A1 (en) | 2007-05-17 |
US7838998B2 (en) | 2010-11-23 |
JP2007142037A (ja) | 2007-06-07 |
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